DS92LV010A Bus LVDS 3.3/5.0V Single Transceiver General Description The DS92LV010A is one in a series of transceivers designed specifically for the high speed, low power proprietary bus backplane interfaces. The device operates from a single 3.3V or 5.0V power supply and includes one differential line driver and one receiver. To minimize bus loading the driver outputs and receiver inputs are internally connected. The logic interface provides maximum flexibility as 4 separate lines are provided (DIN, DE, RE, and ROUT). The device also features flow through which allows easy PCB routing for short stubs between the bus pins and the connector. The driver has 10 mA drive capability, allowing it to drive heavily loaded backplanes, with impedance as low as 27 Ohms. The driver translates between TTL levels (single-ended) to Low Voltage Differential Signaling levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition the differential signaling provides common mode noise rejection of ± 1V. The receiver threshold is ± 100mV over a ± 1V common mode range and translates the low voltage differential levels to standard (CMOS/TTL) levels. Features n n n n n n n n n n n n Bus LVDS Signaling (BLVDS) Designed for Double Termination Applications Balanced Output Impedance Lite Bus Loading 5pF typical Glitch free power up/down (Driver disabled) 3.3V or 5.0V Operation ± 1V Common Mode Range ± 100mV Receiver Sensitivity High Signaling Rate Capability (above 100 Mbps) Low Power CMOS design Product offered in 8 lead SOIC package Industrial Temperature Range Operation Connection Diagram DS100052-1 Order Number DS92LV010ATM See NS Package Number M08A Block Diagram DS100052-2 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100052 www.national.com DS92LV010A Bus LVDS 3.3/5.0V Single Transceiver May 1998 Absolute Maximum Ratings (Notes 1, 2) SOIC If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Derate SOIC Package Supply Voltage (VCC) −0.3V to (VCC + 0.3V) Driver Input Voltage (DIN) −0.3V to (VCC + 0.3V) Receiver Output Voltage (ROUT) −0.3V to (VCC + 0.3V) Bus Pin Voltage (DO/RI ± ) −0.3V to + 3.9V Driver Short Circuit Current ESD (HBM 1.5 kΩ, 100 pF) Storage Temperature Range −65˚C to +150˚C Lead Temperature 6.0V Enable Input Voltage (DE, RE) 1025 mW 8.2 mW/˚C (Soldering, 4 sec.) 260˚C Recommended Operating Conditions Min Continuous > 2.0 kV Max Units Supply Voltage (VCC), or 3.0 3.6 V Supply Voltage (VCC) 4.5 5.5 V Receiver Input Voltage 0.0 2.9 V Operating Free Air Temperature −40 +85 ˚C Min Typ Max Units 140 250 360 mV 3 30 mV 1 1.25 1.65 V 5 50 mV −12 −20 mA Maximum Package Power Dissipation at 25˚C DC Electrical Characteristics (Notes 2, 3) TA = −40˚C to +85˚C unless otherwise noted, VCC = 3.3V ± 0.3V Symbol Parameter VOD Output Differential Voltage ∆VOD VOD Magnitude Change VOS Offset Voltage ∆VOS Offset Magnitude Change IOSD Output Short Circuit Current VOH Voltage Output High Conditions Pin RL = 27Ω, Figure 1 DO+/RI+, DO−/RI− VO = 0V, DE = VCC 2.8 3 V Inputs Open VID = +100 mV I 2.8 3 V Inputs Shorted 2.8 3 V Inputs Terminated, RL = 27Ω 2.8 3 V 0.1 0.4 V −5 −35 −85 mA +100 mV VOL Voltage Output Low IOL = 2.0 mA, VID = −100 mV IOS Output Short Circuit Current VOUT = 0V, VID = +100 mV VTH Input Threshold High DE = 0V VTL Input Threshold Low IIN Input Current VIH Minimum Input High Voltage VIL Maximum Input Low Voltage = −400 µA R OUT DO+/RI+, DO−/RI− −100 DE = 0V, VIN = +2.4V, or 0V −20 VCC = 0V, VIN = +2.4V, or 0V −20 DIN, DE, RE IIH Input High Current VIN = VCC or 2.4V IIL Input Low Current VIN = GND or 0.4V VCL Input Diode Clamp Voltage ICLAMP = −18 mA ICCD Power Supply Current mV ±1 ±1 +20 µA +20 µA 2.0 VCC V GND 0.8 V ± 10 ± 10 µA ±1 ±1 −1.5 DE = RE = VCC , RL = 27Ω µA V 20 mA 5 8 mA DE = 0V, RE = VCC 3 7.5 mA DE = VCC , RE = 0V, RL = 27Ω 16 22 mA DE = RE = 0V ICCZ ICC 2 V CC −0.8 13 ICCR www.national.com OH DC Electrical Characteristics (Notes 2, 3) (Continued) TA = −40˚C to +85˚C unless otherwise noted, VCC = 3.3V ± 0.3V Symbol Coutput Parameter Conditions Pin Capacitance @ BUS Pins Min DO+/RI+, DO−/RI− Typ Max Units 5 pF DC Electrical Characteristics (Notes 2, 3) TA = −40˚C to +85˚C unless otherwise noted, VCC = 5.0V ± 0.5V Symbol Parameter VOD Output Differential Voltage ∆VOD VOD Magnitude Change VOS Offset Voltage ∆VOS Offset Magnitude Change IOSD Output Short Circuit Current VOH Voltage Output High Conditions Pin RL = 27Ω, Figure 1 DO+/RI+, DO−/RI− Typ Max Units 145 270 390 mV 3 30 mV 1 1.35 1.65 V 5 50 mV −12 −20 mA VO = 0V, DE = VCC 4.3 5.0 V Inputs Open VID = +100 mV IOH = −400 µA 4.3 5.0 V Inputs Shorted 4.3 5.0 V Inputs Terminated, RL = 27Ω 4.3 5.0 V 0.1 0.4 −35 −90 −130 mA +100 mV VOL Voltage Output Low IOL = 2.0 mA, VID = −100 mV IOS Output Short Circuit Current VOUT = 0V, VID = +100 mV VTH Input Threshold High DE = 0V VTL Input Threshold Low IIN Input Current ROUT DO+/RI+, DO−/RI− −100 DE = 0V, VIN = +2.4V, or 0V −20 VCC = 0V, VIN = +2.4V, or 0V −20 VIH Minimum Input High Voltage VIL Maximum Input Low Voltage IIH Input High Current VIN = VCC or 2.4V IIL Input Low Current VIN = GND or 0.4V VCL Input Diode Clamp Voltage ICLAMP = −18 mA ICCD Power Supply Current DIN, DE, RE +20 µA +20 µA 2.0 VCC V GND 0.8 V ± 10 ± 10 µA −1.5 DE = RE = VCC, RL = 27Ω DE = RE = 0V ICCZ DE = 0V, RE = VCC ICC DE = VCC , RE = 0V, RL = 27Ω Capacitance @ BUS Pins V CC DO+/RI+, DO−/RI− V mV ±1 ±1 ±1 ±1 ICCR Coutput Min µA −0.8 V 17 25 mA 6 10 mA 3 8 mA 20 25 mA 5 pF Note 1: “Absolute Maximum Ratings” are these beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground except VOD, VID, VTH and VTL unless otherwise specified. Note 3: All typicals are given for VCC = +3.3V or 5.0 V and TA = +25˚C, unless otherwise stated. Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF) > 2.0 kV EAT (0Ω, 200 pF) > 300V. Note 5: CL includes probe and fixture capacitance. Note 6: Generator waveforms for all tests unless otherwise specified: f = 1MHz, ZO = 50Ω, tr, tf ≤ 6.0ns (0%–100%) on control pins and ≤ 1.0ns for RI inputs. Note 7: The DS92LV010A is a current mode device and only function with datasheet specification when a resistive load is applied between the driver outputs. Note 8: For receiver TRI-STATE ® delays, the switch is set to VCC for tPZL, and tPLZ and to GND for tPZH, and tPHZ. 3 www.national.com AC Electrical Characteristics (Note 6) TA = −40˚C to +85˚C, VCC = 3.3V ± 0.3V Symbol Parameter Conditions Min Typ Max Units 1.0 3.0 5.0 ns 1.0 2.8 5.0 ns DIFFERENTIAL DRIVER TIMING REQUIREMENTS tPHLD Differential Prop. Delay High to Low tPLHD Differential Prop. Delay Low to High tSKD Differential SKEW |t tTLH Transition Time Low to High tTHL Transition Time High to Low tPHZ Disable Time High to Z tPLZ Disable Time Low to Z tPZH Enable Time Z to High tPZL Enable Time Z to Low PHLD RL = 27Ω, Figures 2, 3 CL = 10 pF - tPLHD| RL = 27Ω, Figures 4, 5 CL = 10 pF 0.2 1.0 ns 0.3 2.0 ns 0.3 2.0 ns 4.5 9.0 ns 0.5 5.0 10.0 ns 2.0 5.0 7.0 ns 1.0 4.5 9.0 ns 2.5 5.0 12.0 ns 2.5 5.5 10.0 ns 0.5 DIFFERENTIAL RECEIVER TIMING REQUIREMENTS tPHLD Differential Prop. Delay High to Low tPLHD Differential Prop. Delay Low to High Figures 6, 7 CL = 10 pF tSKD Differential SKEW |t 0.5 2.0 ns tr Rise Time 1.5 4.0 ns tf Fall Time 1.5 4.0 ns tPHZ Disable Time High to Z 4.0 6.0 ns tPLZ Disable Time Low to Z 2.0 5.0 7.0 ns tPZH Enable Time Z to High 2.0 7.0 13.0 ns tPZL Enable Time Z to Low 2.0 6.0 10.0 ns Min Typ Max Units 0.5 2.7 4.5 ns 0.5 2.5 4.5 ns PHLD - tPLHD| RL = 500Ω, Figures 8, 9 CL = 10 pF (Note 8) AC Electrical Characteristics 2.0 (Note 6) TA = −40˚C to +85˚C, VCC = 5.0V ± 0.5V Symbol Parameter Conditions DIFFERENTIAL DRIVER TIMING REQUIREMENTS tPHLD Differential Prop. Delay High to Low tPLHD Differential Prop. Delay Low to High tSKD Differential SKEW |t tTLH Transition Time Low to High tTHL Transition Time High to Low tPHZ Disable Time High to Z tPLZ Disable Time Low to Z tPZH Enable Time Z to High tPZL Enable Time Z to Low PHLD RL = 27Ω, Figures 2, 3 CL = 10 pF - tPLHD| RL = 27Ω, Figures 4, 5 CL = 10 pF 0.2 1.0 ns 0.3 2.0 ns 0.3 2.0 ns 3.0 7.0 ns 0.5 5.0 10.0 ns 2.0 4.0 7.0 ns 1.0 4.0 9.0 ns 2.5 5.0 12.0 ns 2.5 4.6 10.0 ns 0.5 DIFFERENTIAL RECEIVER TIMING REQUIREMENTS tPHLD Differential Prop. Delay High to Low tPLHD Differential Prop. Delay Low to High Figures 6, 7 CL = 10 pF tSKD Differential SKEW |t 0.4 2.0 ns tr Rise Time 1.2 2.5 ns tf Fall Time 1.2 2.5 ns www.national.com PHLD - tPLHD| 4 AC Electrical Characteristics (Note 6) (Continued) TA = −40˚C to +85˚C, VCC = 5.0V ± 0.5V Symbol Parameter Conditions Min Typ Max Units RL = 500Ω, Figures 8, 9 CL = 10 pF (Note 8) 2.0 4.0 6.0 ns 2.0 4.0 6.0 ns DIFFERENTIAL RECEIVER TIMING REQUIREMENTS tPHZ Disable Time High to Z tPLZ Disable Time Low to Z tPZH Enable Time Z to High 2.0 5.0 9.0 ns tPZL Enable Time Z to Low 2.0 5.0 7.0 ns Test Circuits and Timing Waveforms DS100052-3 FIGURE 1. Differential Driver DC Test Circuit DS100052-4 FIGURE 2. Differential Driver Propagation Delay and Transition Time Test Circuit DS100052-5 FIGURE 3. Differential Driver Propagation Delay and Transition Time Waveforms 5 www.national.com Test Circuits and Timing Waveforms (Continued) DS100052-6 FIGURE 4. Driver TRI-STATE Delay Test Circuit DS100052-7 FIGURE 5. Driver TRI-STATE Delay Waveforms DS100052-8 FIGURE 6. Receiver Propagation Delay and Transition Time Test Circuit DS100052-9 FIGURE 7. Receiver Propagation Delay and Transition Time Waveforms www.national.com 6 Test Circuits and Timing Waveforms (Continued) DS100052-10 FIGURE 8. Receiver TRI-STATE Delay Test Circuit DS100052-11 FIGURE 9. Receiver TRI-STATE Delay Waveforms TRI-STATE Delay Waveforms Typical Bus Application Configurations DS100052-12 Bi-Directional Half-Duplex Point-to-Point Applications DS100052-13 Multi-Point Bus Applications • Application Information There are a few common practices which should be implied when designing PCB for BLVDS signaling. Recommended practices are: Keep drivers and receivers as close to the (BLVDS port side) connector as possible. • Use at least 4 layer PCB board (BLVDS signals, ground, power and TTL signals). 7 www.national.com Application Information • (Continued) Bypass each BLVDS device and also use distributed bulk capacitance. Surface mount capacitors placed close to power and ground pins work best. Two or three multilayer ceramic (MLC) surface mount capacitors (0.1 µF, and 0.01 µF in parallel should be used between each VCC and ground. The capacitors should be as close as possible to the VCC pin. • Use the termination resistor which best matches the differential impedance of your transmission line. • Leave unused LVDS receiver inputs open (floating) TABLE 1. Functional Table MODE SELECTED DE RE DRIVER MODE H H RECEIVER MODE L L TRI-STATE MODE L H LOOP BACK MODE H L TABLE 2. Transmitter Mode INPUTS DE DI TABLE 3. Receiver Mode OUTPUTS INPUTS DO+ DO− RE OUTPUT (RI+)-(RI−) H L L H L L ( < −100 mV) L H H H L L H ( > +100 mV) H H 2 > & > 0.8 X X L 100 mV > & > −100 mV X L X Z Z H X Z L = Low state H = High state X = High or Low logic state Z = High impedance state L = Low state H = High state TABLE 4. Device Pin Description Pin Name Pin # Input/Output DIN 2 I DO ± /RI ± 6, 7 I/O LVDS Driver Outputs/LVDS Receiver Inputs ROUT 3 O TTL Receiver Output RE 5 I Receiver Enable TTL Input (Active Low) DE 1 I Driver Enable TTL Input (Active High) GND 4 NA Ground VCC 8 NA Power Supply www.national.com Description TTL Driver Input 8 9 DS92LV010A Bus LVDS 3.3/5.0V Single Transceiver Physical Dimensions inches (millimeters) unless otherwise noted Order Number DS92LV010ATM See NS Package Number M08A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. 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