TP3155 Time Slot Assignment Circuit General Description Features The TP3155 is a monolithic CMOS logic circuit designed to generate transmit and receive frame synchronization pulses for up to 8 COMBOTM CODEC/Filters. Each frame sync pulse may be independently assigned to a time slot in a frame of up to 32 time slots. Assignments are controlled by loading in an 8-bit word via a simple serial interface port. This control interface is compatible with that used on the TP3020/TP3021 and 2910/2911 CODECs, enabling an easy upgrade to COMBO CODEC/Filters to be made. Y Y Y Y Y Y Y Controls up to 8 COMBO CODEC/Filters Independent transmit and receive time slot assignments 8-channel unidirectional mode Up to 32 time slots per frame Serial control interface compatible with TP3020/TP3021 CODECs LS TTL and CMOS compatible inputs 5 mW, 5V operation Typical Application TL/H/5118 – 1 TRI-STATEÉ is a registered trademarks of National Semiconductor Corp. COMBOTM is a trademark of National Semiconductor Corp. C1995 National Semiconductor Corporation TL/H/5118 RRD-B30M115/Printed in U. S. A. TP3155 Time Slot Assignment Circuit September 1993 Absolute Maximum Ratings Operating Temperature Range (Ambient) b 25§ C to a 125§ C 7V Storage Temperature Range (Ambient) b 65§ C to a 150§ C VCC a 0.3V to GND b0.3V Maximum Lead Temperature (Soldering, 10 seconds) 300§ C If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. VCC Relative to GND Voltage at Any Input or Output ESD rating to be determined. DC Electrical Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e 5.0V g 5%; TA e 0§ C to a 70§ C by correlation with 100% electrical testing at TA e 25§ C. All other limits are assured by correlation with other production tests and/ or product design and characterization. Typicals specified at VCC e 5.0V, TA e 25§ C. Parameter Conditions Min Input Voltage Levels VIH, Logic High VIL, Logic Low Typ Max Units 0.7 V V 2.0 Input Currents All Inputs Except MODE MODE VIL k VIN k VIH VIN e 0V Output Voltage Levels VOH, Logic High VOL, Logic Low b1 b 100 FSX and FSR Outputs, IOH e 3 mA FSX and FSR Outputs, IOL e 5 mA TSX Output, IOL e 5 mA Power Dissipation Operating Current 1 2.4 BCLK e 2.048 MHz, All Outputs Open-Circuit 1 mA mA 0.4 0.4 V V V 1.5 mA Timing Specifications Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e 5.0V g 5%, TA e 0§ C to a 70§ C by correlation with 100% electrical testing at TA e 25§ C. All other limits are assured by correlation with other production tests and/ or product design and characterization. Typicals specified at VCC e 5.0V, TA e 25§ C. All timing parameters are measured at VOH e 2.0V and VOL e 0.7V. See Definitions and Timing Conventions section for test methods information. Conditions Min tPC Symbol Period of Clock Parameter BCLK, CLKC 480 Max Units ns tWCH Width of Clock High BCLK, CLKC 160 ns tWCL Width of Clock Low BCLK, CLKC 160 ns tSDC Set-Up Time from DC to CLKC 50 ns tHCD Hold Time from CLKC to DC 50 ns tSCC Set-Up Time from CS to CLKC tHCC Hold Time from CLKC to CS tSCHC tHCHC 30 ns 100 ns Set-Up Time from Channel Select to CLKC 50 ns Hold Time from Channel Select to CLKC 50 ns tDBF Delay Time from BCLK Low to FSX/R 0 – 3 High or Low tHSYNC Hold Time from BCLK to Frame Sync tSSYNC Set-Up Time from Frame Sync to BCLK CL e 50 pF tDTL Delay to TSX Low CL e 50 pF tDTH Delay to TSX High RL e 1k to VCC tRC, tFC Rise and Fall Time of Clock BCLK, CLKC 2 100 ns 50 ns 100 ns 30 140 ns 140 ns 50 ns Block Diagram TL/H/5118 – 2 Timing Diagrams Control Interface TL/H/5118 – 3 Output TL/H/5118 – 4 3 Connection Diagrams Dual-In-Line Package Plastic Chip Carrier (PCC) Package TL/H/5118–5 Order Number TP3155V See NS Package Number V20A TL/H/5118 – 6 Top View Order Number TP3155N See NS Package Number N20A Pin Descriptions Symbol FSX1 Description A conventional CMOS frame sync output which is normally low, and goes active-high for 8 cycles of BCLK when a valid transmit time slot assignment is made. FSR1 A conventional CMOS frame sync output which is normally low, and goes active-high for 8 cycles of BCLK when a valid receive time slot assignment is made. FSX0 A transmit frame sync output similar to pin 1. A receive frame sync output similar to pin 2. An open-drain N-channel output which is normally high impedance but pulls low during any active transmit time slot. FSR0 TSX DC The input for an 8-bit serial control word. X is the first bit clocked in. CLKC The clock input for the control interface. The active-low chip select for the control interface. The mode select input. When left open-circuit or connected to VCC, mode 1 is selected, and when connected to GND, mode 2 is selected. The 0V ground connection to the device. CS MODE GND Symbol BCLK Description The bit clock input, which should run at the same rate as that for the COMBO CODEC/ Filter COMBO. XSYNC The transmit TS0 sync pulse input. Must be synchronous with BCLK. RSYNC/CH2 The function of this input is determined by the MODE input (pin 9). In mode 1 this is the receive TS0 sync pulse, RSYNC, which must be synchronous with BCLK. In mode 2 this is the CH2 input for the MSB of the channel select word. CH1 The input for the next significant bit of the channel select word. CH0 The input for the LSB of the channel select word, which defines the frame sync output affected by the following control word. FSX3 A transmit frame sync output similar to pin 1. FSR3 FSX2 FSR2 VCC 4 A receive frame sync output similar to pin 2. A transmit frame sync output similar to pin 1. A receive frame sync output similar to pin 2. The positive supply to the device. 5V g 5%. Functional Description OPERATING MODES TSX OUTPUT The TP3155 control interface requires an 8-bit serial control word which is compatible with the TP3020/TP3021 and 2910/2911 CODECs. Two bits, X and R, define which of the two groups of frame sync outputs, FSX0 to FSX3 or FSR0 to FSR3, is affected by the control word, and a 6-bit assignment field specifies the selected time slot, from 0 to 31. A frame sync output is active-high for one time slot, which is always 8 cycles of BCLK. A frame may consist of any number of time slots up to 32. If a timeslot is assigned which is beyond the number of time slots in a frame, the FSX or FSR output to which it was assigned will remain inactive. Two modes of operation are available. Mode 1 is for systems requiring different time slot assignments for the transmit and receive direction of each channel. Mode 1 is selected by leaving pin 9 (MODE) open-circuit or connecting it to VCC. In this case, Pin 13 is the RSYNC input which defines the start of each receive frame, and the four outputs, FSR0 – FSR3, are assigned with respect to RSYNC. The XSYNC input defines the start of each transmit frame and outputs FSX0– FSX3 are assigned with respect to XSYNC. XSYNC may have any phase relationship with RSYNC. Inputs CH0 and CH1 select the channel, from 0 to 3 (see Table Ia). Mode 2 provides the option of assigning all 8 frame sync outputs with respect to the XSYNC input. Mode 2 is selected by connecting pin 9 (MODE) to GND. This makes the TP3155 TSAC useful for either an 8-channel undirectional controller or for systems in which the transmit and receive directions of each channel are always assigned to the same time slot as the other, i.e., the FSX and FSR inputs on the COMBO CODEC/Filter are hard-wired together. In this case, logical selection of the channel to be assigned is made via inputs CH0, CH1 and CH2 (see Table Ib). In mode 1 (separate transmit and receive assignments), this output pulls low whenever any FSX output pulse is being generated. In mode 2, this output pulls low whenever any FSX or FSR output is being generated. At all other times it is open-circuit, allowing the TSX outputs of a number of TSACS to be wire-ANDed together with a common pull-up resistor. This signal can be used to control the TRI-STATEÉ enable input of a line driver to buffer the transmit PCM bus from the CODEC/Filters to the backplane. TABLE Ia. Control Mode 1 (TP3020/TP3021 Compatible) X R T5 T4 T3 T2 T1 T0 X is the first bit clocked into the DC input. Control Data Format POWER-UP INITIALIZATION During power-up, all frame sync outputs, FSX0– FSX3 and FSR0 – FSR3, are inhibited and held low. No outputs will go active until a valid time slot assignment is made. LOADING CONTROL DATA During the loading of control data, the binary code for the selected channel must be set on inputs CH0 and CH1 (and CH2 in mode 2), see Tables Ia and Ib. Control data is clocked into the DC input on the falling edges of CLKC while CS is low. A new time slot assignment is transferred to the selected assignment register on the high going transition of CS. The new assignment is re-synchronized to the system clock such that the new FS output pulses will start at the next complete valid time slot after the rising edge of CS. T5 T4 T3 T2 T1 T0 Time Slot 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 1 X 1 1 X 1 1 X 1 1 X 0 1 X 0 1 2 : 30 31 (Note 1) CH1 CH0 Channel Selected 0 0 1 1 0 1 0 1 Assign to FSx0 and/or FSR0 Assign to FSx1 and/or FSR1 Assign to FSx2 and/or FSR2 Assign to FSx3 and/or FSR3 X R Action 0 0 1 1 0 1 0 1 Assign time slot to both selected FSX and FSR Assign time slot to selected FSX only Assign time slot to selected FSR only Disable both selected FSX and FSR TABLE Ib. Control Mode 2 TIME SLOT COUNTER OPERATION At the start of TS0 of each transmit frame, defined by the first falling edge of BCLK after XSYNC goes high, the transmit time slot counter is reset to 000000 and begins to increment once every 8 cycles of BCLK. Each count is compared with the 4 transmit assignment registers and, on finding a match, a frame sync pulse is generated at that FSX output. Similarly, the first falling edge of BCLK after RSYNC goes high defines the start of receive TS0, and outputs FSR0 – FSR3 are generated with respect to TS0 when the receive time slot counter matches the appropriate receive assignment register. CH2 CH1 CH0 Channel Selected 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Assign to FSX0 Assign to FSX1 Assign to FSX2 Assign to FSX3 Assign to FSR0 Assign to FSR1 Assign to FSR2 Assign to FSR3 X R 0 0 1 1 0 1 0 1 Action ( Assign time slot to selected output Disable selected output Note 1: When T5 e 1, then the appropriate FSX or FSR output is inactive. 5 Definitions and Timing Conventions Rise Time DEFINITIONS VIH VIL VOH VOL Threshold Region Valid Signal Invalid Signal VIH is the d.c. input level above which an input level is guaranteed to appear as a logical one. This parameter is to be measured by performing a functional test at reduced clock speeds and nominal timing, (i.e. not minimum setup and hold times or output strobes), with the high level of all driving signals set to VIH and maximum supply voltages applied to the device. Fall Time Pulse Width High VIL is the d.c. input level below which an input level is guaranteed to appear as a logical zero to the device. This parameter is measured in the same manner as VIH but with all driving signal low levels set to VIL and minimum supply voltages applied to the device. Pulse Width Low VOH is the minimum d.c. output level to which an output placed in a logical one state will converge when loaded at the maximum specified load current. Setup Time VOL is the maximum d.c. output level to which an output placed in a logical zero state will converge when loaded at the maximum specified load current. The threshold region is the range of input voltages between VIL and VIH. A signal is Valid if it is in one of the valid logic states, (i.e. above VIH or below VIL). In timing specifications, a signal is deemed valid at the instant it enters a valid state. A signal is Invalid if it is not in a valid logic state, i.e. when it is in the threshold region between VIL and VIH. In timing specifications, a signal is deemed Invalid at the instant it enters the threshold region. Hold Time Delay Time TIMING CONVENTIONS For the purposes of this timing specification the following conventions apply: Input Signals All input signals may be characterized as: VL e 0.4V, VH e 2.4V, tR k 10 ns, tF k 10ns. Period The period of clock signal is designated as tPxx where xx represents the mnemonic of the clock signal being specified. 6 Rise times are designated as tRyy, where yy represents a mnemonic of the signal whose rise time is being specified. tRyy is measured from VIL to VIH. Fall times are designated as tFyy, where yy represents a mnemonic of the signal whose fall time is being specified. tFyy is measured from VIH to VIL. The high pulse width is designated as tWzzH, where zz represents the mnemonic of the input or output signal whose pulse width is being specified. High pulse widths are measured from VIH to VIH. The low pulse width is designated as tWzzL, where zz represents the mnemonic of the input or output signal whose pulse width is being specified. Low pulse widths are measured from VIL to VIL. Setup times are designated as tSwwxx, where ww represents the mnemonic of the input signal whose setup time is being specified relative to a clock or strobe input represented by mnemonic xx. Setup times are measured from the ww Valid to xx Invalid. Hold times are designated as tHxxww, where ww represents the mnemonic of the input signal whose hold time is being specified relative to a clock or strobe input represented by mnemonic xx. Hold times are measured from xx Valid to ww Invalid. Delay times are designated as tDxxyy[ lHlL] , where xx represents the mnemonic of the input reference signal and yy represents the mnemonic of the output signal whose timing is being specified relative to xx. The mnemonic may optionally be terminated by an H or L to specify the high going or low going transition of the output signal. Maximum delay times are measured from xx Valid to yy Valid. Minimum delay times are measured from xx Valid to yy Invalid. This parameter is tested under the load conditions specified in the Conditions column of the Timing Specifications section of this data sheet. Applications Information Alternatively, eight full-length bits can be obtained by inverting the BCLK to the combo devices, thereby aligning rising edges of BCLK and FSX/R. Figure 2 shows typical timing for the control data interface. Figure 3 shows the digital interconnections of a typical line card application. A combination of the TP3155 TSAC and any CODEC/Filter COMBO from the TP3052/3/4/7 or TP3064/7 series will result in data timing as shown in Figure 1 . Although the FSx output pulse goes high before BCLK goes high, the Dx output of the combo remains in the TRI-STATE mode until both are high. The eight bit period is shortened to prevent a bus clash, just as it is on the TP3020/1 CODECs. TL/H/5118 – 7 FIGURE 1. Transmit Data Timing TL/H/5118 – 8 FIGURE 2. Control Data Timing 7 FIGURE 3. Digital Interconnections on a Typical Synchronous Line Card TL/H/5118 – 9 Application Information (Continued) 8 Physical Dimensions inches (millimeters) Molded Dual-In-Line Package (N) Order Number TP3155N NS Package Number N20A 9 TP3155 Time Slot Assignment Circuit Physical Dimensions inches (millimeters) (Continued) Lit. Ý113982 Plastic Chip Carrier Package (V) Order Number TP3155V NS Package Number V20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: (a49) 0-180-530 85 86 Email: cnjwge @ tevm2.nsc.com Deutsch Tel: (a49) 0-180-530 85 85 English Tel: (a49) 0-180-532 78 32 Fran3ais Tel: (a49) 0-180-532 93 58 Italiano Tel: (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.