NSC ADC1173CIMTC

ADC1173
8-Bit, 3-Volt, 15MSPS, 33mW A/D Converter
General Description
Key Specifications
The ADC1173 is a low power, 15 MSPS analog-to-digital
converter that digitizes signals to 8 bits while consuming just
33 mW of power (typ). The ADC1173 uses a unique architecture that achieves 7.6 Effective Bits. Output formatting is
straight binary coding.
The excellent DC and AC characteristics of this device, together with its low power consumption and +3V single supply
operation, make it ideally suited for many video, imaging and
communications applications, including use in portable
equipment. Furthermore, the ADC1173 is resistant to latchup
and the outputs are short-circuit proof. The top and bottom of
the ADC1173’s reference ladder is available for connections,
enabling a wide range of input possibilities.
The ADC1173 is offered in SOIC (EIAJ) and TSSOP. It is designed to operate over the commercial temperature range of
-20˚C to +75˚C.
Features
n
n
n
n
n
Internal Sample-and-Hold Function
Single +3V Operation
Internal Reference Bias Resistors
Industry Standard Pinout
TRI-STATE ® Outputs
n Resolution
8 Bits
n Maximum Sampling Frequency
15 MSPS (min)
n THD
−56 dB (typ)
n DNL
± 0.8 LSB (max)
n ENOB at 3.58 MHz Input
7.6 Bits (typ)
n Guaranteed No Missing Codes
n Differential Phase
n Differential Gain
n Power Consumption
0.5 Degree (max)
1.5% (typ)
33mW (typ)
(excluding reference current)
Applications
n
n
n
n
n
n
n
n
Video Digitization
Digital Still Cameras
Set Top Boxes
Camcorders
Personal Computer Video
Digital Television
CCD Imaging
Electro-Optics
Ordering Information
ADC1173CIJM
SOIC (EIAJ)
ADC1173CIJMX
SOIC (EIAJ) (tape & reel)
ADC1173CIMTC
TSSOP
ADC1173CIMTCX
TSSOP (tape & reel)
Pin Configuration
DS100890-1
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS100890
www.national.com
ADC1173 8-Bit, 3-Volt, 15MSPS, 33mW A/D Converter
February 1999
Block Diagram
DS100890-2
Pin Descriptions and Equivalent Circuits
Pin
No.
Symbol
19
VIN
Analog signal input. Conversion range is VRB to
VRT.
16
VRTS
Reference Top Bias with internal pull-up resistor.
Short this pin to VRT to self bias the reference
ladder.
VRT
Analog Input that is the high (top) side of the
reference ladder of the ADC. Nominal range is 1.0V
to AVDD. Voltage on VRT and VRB inputs define the
VIN conversion range. Bypass well. See Section 2.0
for more information.
VRB
Analog Input that is the low (bottom) side of the
reference ladder of the ADC. Nominal range is 0V
to 2.0V. Voltage on VRT and VRB inputs define the
VIN conversion range. Bypass well. See Section 2.0
for more information.
17
23
www.national.com
Equivalent Circuit
Description
2
Pin Descriptions and Equivalent Circuits
Equivalent Circuit
(Continued)
Pin
No.
Symbol
22
VRBS
1
OE
CMOS/TTL compatible Digital input that, when low,
enables the digital outputs of the ADC1173. When
high, the outputs are in a high impedance state.
12
CLK
CMOS/TTL compatible digital clock Input. VIN is
sampled on the falling edge of CLK input.
Description
Reference Bottom Bias with internal pull down
resistor. Short to VRB to self bias the reference
ladder.
D0-D7
Conversion data digital Output pins. D0 is the LSB,
D7 is the MSB. Valid data is output just after the
rising edge of the CLK input. These pins are
enabled by bringing the OE pin low.
11, 13
DVDD
Positive digital supply pin. Connect to a clean, quiet
voltage source of +3V. AVDD and DVDD should have
a common source and be separately bypassed with
a 10µF capacitor and a 0.1µF ceramic chip
capacitor. See Section 3.0 for more information.
2, 24
DVSS
The ground return for the digital supply. AVSS and
DVSS should be connected together close to the
ADC1173.
14,
15, 18
AVDD
Positive analog supply pin. Connected to a clean,
quiet voltage source of +3V. AVDD and DVDD should
have a common source and be separately bypassed
with a 10 µF capacitor and a 0.1 µF ceramic chip
capacitor. See Section 3.0 for more information.
20, 21
AVSS
The ground return for the analog supply. AVSS and
DVSS should be connected together close to the
ADC1173 package.
3 thru
10
3
www.national.com
Absolute Maximum Ratings (Note 1)
ESD Susceptibility (Note 5)
Human Body Model
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
AVDD, DVDD
AVDD to VSS
CLK, OE Voltage
DVSS to DVDD
Input Current (Note 3)
± 25mA
Package Input Current
(Note 3)
Package Dissipation at 25˚C
−65˚C to +150˚C
Operating Ratings(Notes 1, 2)
−0.05 to (AVDD + 0.05V)
Digital Output Voltage
300˚C
Storage Temperature
−0.3V to 6.5V
VRT, VRB
200V
Soldering Temp., Infared, 10
sec. (Note 6)
6.5V
Voltage on Any Pin
2000V
Machine Model
−20˚C ≤ TA ≤ +75˚C
Temperature Range
AVDD, DVDD
+2.7V to +3.6V
|AVSS -DVSS|
0V to 100 mV
± 50mA
VRT
1.0V to AVDD
(Note 4)
VRB
0V to 2.0V
VIN Voltage Range
VRB to VRT
Converter Electrical Characteristics
The following specifications apply for AVDD = DVDD = +3.0VDC, OE = 0V, VRT = +2.0V, VRB = 0V, CL = 20 pF, fCLK = 15MHz
at 50% duty cycle. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25˚C (Notes 7, 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
Units
± 0.5
± 0.4
± 1.3
± 0.85
LSB( max)
0
(max)
DC Accuracy
INL
Integral Non Linearity
DNL
Differential Non Linearity
Missing Codes
LSB( max)
EOT
Top Offset
−12
mV
EOB
Bottom Offset
+1.0
mV
0.5
Degree
1.5
%
Video Accuracy
DP
Differential Phase Error
DG
Differential Gain Error
fin = 3.58 MHz sine wave
fin = 3.58 MHz sine wave
Analog Input and Reference Characteristics
VIN
CIN
Input Range
VIN Input Capacitance
2.0
VIN
= 1.5V + 0.7Vrms
(CLK
LOW)
4
(CLK
HIGH)
11
VRB
VRT
V(min)
V(max)
pF
RIN
Input Resistance
>1
MΩ
BW
Analog Input Bandwidth
120
MHz
RRT
Top Reference Resistor
360
RREF
Reference Ladder
Resistance
300
RRB
Bottom Reference Resistor
IREF
VRT to VRB
Ω(min)
400
Ω(max)
Ω
90
VRT = VRTS, VRB = VRBS
4.2
VRT = VRTS,VRB = AVSS
4.8
1.56
mA
Reference Ladder Current
VRT
Reference Top Self Bias
Voltage
VRT connected to VRTS
VRB connected to VRBS
VRB
Reference Bottom Self Bias
Voltage
VRB connected to VRBS
VRTS VRBS
Ω
200
Self Bias Voltage Delta
www.national.com
VRT connected to VRTS
0.36
VRT connected to VRTS,
VRB connected to VRBS
1.2
VRT connected to VRTS,
VRB connected to VSS
1.38
4
mA
1.45
1.65
V(min)
V(max)
0.32
V(min)
0.40
V(max)
1.1
1.3
µAmin
µAmax
V
Converter Electrical Characteristics
(Continued)
The following specifications apply for AVDD = DVDD = +3.0VDC, OE = 0V, VRT = +2.0V, VRB = 0V, CL = 20 pF, fCLK = 15MHz
at 50% duty cycle. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25˚C (Notes 7, 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
Units
Analog Input and Reference Characteristics
VRT VRB
Reference Voltage Delta
2
1.0
V(min)
VA
V(max)
Power Supply Characteristics
IADD
Analog Supply Current
IDDD
Digital Supply Curretn
IAVDD +
IDVDD
Total Operating Current
Power Consumption
DVDD = AVDD = 3.6V
DVDD = AVDD = 3.6V
DVDD AVDD = 3.6V,
DVDD = AVDD = 3.6V, CLK Low
(Note 10)
DVDD = AVDD = 3.6V
6.8
mA
2.3
9.1
mA
11
5.8
33
mA
mA
40
mW
CLK, OE Digital Input Characteristics
VIH
Logical High Input Voltage
VIL
Logical Low Input Voltage
IIH
Logical High Input Current
IIL
Logic Low Input Current
CIN
Logic Input Capacitance
DVDD = AVDD = 3.6V
DVDD = AVDD = 3.6V
VIH = DVDD = AVDD = 3.6V
VIL = 0V, DVDD = AVDD = 3.6V
2.2
V (min)
0.8
V (max)
5
µA
−5
µA
5
pF
Digital Output Characteristics
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
IOZH,
IOZL
Tri-State ® Leakage Current
DVDD = 2.7V, IOH = −360µA
DVDD = 2.7V, IOH = −1.1mA
DVDD = 2.7V, IOL = 1.6mA
DVDD = 3.6V, OE = DVDD,
VOL = 0V or VOH = DVDD
2.4
V(min)
2.1
1.9
V(min)
0.32
0.6
V(max)
± 20
µA
AC Electrical Characteristics
fC1
Maximum Conversion Rate
20
fC2
Minimum Conversion Rate
1
MHz
tOD−0
Output Delay
CLK high to low data valid
28
ns(max)
tOD−1
Output Delay
CLK low to high data valid
24
Pipline Delay (Latency)
15
ns(max)
Clock
Cycles
2.5
tDS
Sampling (Aperture) Delay
tAJ
Aperture Jitter
tOH
Output Hold Time
CLK high to data invalid
15
ns
tEN
OE Low to Data Valid
Loaded as in Figure 2
22
ns
tDIS
OE High to High Z State
Loaded as in Figure 2
fIN = 1.31 MHz
fIN = 3.58 MHz
fIN = 7.5 MHz
fIN = 1.31 MHz
fIN = 3.58 MHz
fIN = 7.5 MHz
fIN = 1.31 MHz
fIN = 3.58 MHz
fIN = 7.5 MHz
fIN = 1.31 MHz
fIN = 3.58 MHz
fIN = 7.5 MHz
fIN = 1.31 MHz
fIN = 3.58 MHz
fIN = 7.5 MHz
12
ns
ENOB
Effective Number of Bits
SINAD
Signal-to- Noise & Distortion
SNR
Signal-to-Noise Ratio
SFDR
Spurious Free Dynamic
Range
THD
Total Harmonic Distortion
CLK low to acquissition of data
MHz(min)
5
3
ns
30
ps rms
7.7
7.6
7.4
7.0
Bits (min)
49
47.7
46.5
43
dB(min)
49
48.7
48.0
44
dB(min)
65
55
51
dB
−62
−54
−51
dB
www.national.com
Converter Electrical Characteristics
(Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND = AVSS = DVSS = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than AVSS or DVSS, or greater than AVDD or DVDD), the current at that pin should
be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of
25 mA to two.
Note 4: The absolute maximum junction temperatures (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance θJA, and the ambient temperature, TA, and can be calculated using the formula PDMAX = (TJmax - TA )/θJA. In the 24-pin
TSSOP, θJA is 92˚C/W, so PDMAX = 1,358 mW at 25˚C and 815 mW at the maximum operating ambient temperature of 75˚C. (Typical thermal resistance, θJA, of
this part is 98˚C/W for the EIAJ SOIC). Note that the power dissipation of this device under normal operation will typically be about 49 mW (33 mW quiescent power
+ 13 mW reference ladder power + 3 mW due to 1 TTL loan on each digital output. The values for maximum power dissipation listed above will be reached only when
the ADC1173 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5kΩ resistor. Machine model is 220 pf discharged through ZERO Ω.
Note 6: See AN450, ″Surface Mounting Methods and Their Effect on Product Reliability″, or the section entitled ″Surface Mount″ found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: The analog inputs are protected as shown below. Input voltage magnitudes up to 6.5V or to 500 mV below GND will not damage this device. However, errors
in the A/D conversion can occur if the input goes above VDD or below GND by more than 50 mV. As an example, if AVDD is 2.7VDC, the full-scale input voltage must
be ≤2.75VDC to ensure accurate conversions.
DS100890-10
Note 8: To guarantee accuracy, it is required that AVDD and DVDD be well bypassed. Each supply pin must be decoupled with separate bypass capacitors.
Note 9: Typical figures are at TJ = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality
Level).
Note 10: At least two clock cycles must be presented to the ADC1173 after power up. See Section 4.0 for details.
www.national.com
6
Typical Performance Characteristics
INL vs Temperature
DNL vs Temperature
DS100890-21
DS100890-20
SNR vs fIN
SNR vs Temperature
THD vs Temperature
SINAD/ENOB vs Temp
DS100890-23
DS100890-33
SINAD/ENOB vs fIN
SFDR vs fIN
DS100890-24
Differential Gain vs Temperature
DS100890-26
DS100890-29
DS100890-31
Differential Phase vs Temperature
DS100890-22
Spectral Response
DS100890-27
IDDD + IADD vs fCLK
DS100890-28
7
DS100890-32
www.national.com
Typical Performance Characteristics
(Continued)
tOD vs Temperature
DS100890-25
SAMPLING (APERTURE) DELAY is that time required after
the fall of the clock input for the sampling switch to open. The
Sample/Hold circuit effectively stops capturing the input signal and goes into the ″hold″ mode tDS after the clock goes
low.
SIGNAL TO NOISE RATIO (SNR) is the ratio of the rms
value of the input signal to the rms value of the other spectral
components below one-half the sampling frequency, not including harmonics or dc.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) Is the ratio of the rms value of the input signal to the
rms value of all of the other spectral components below half
the clock frequency, including harmonics but excluding dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input
signal and the peak spurious signal, where a spurious signal
is any signal present in the output spectrum that is not
present at the input.
TOP OFFSET is the difference between the positive reference voltage and the input voltage that just causes the output code to transition to full scale and is defined as EOT =
VFT − VRT. Where VFT is the full scale transition input voltage. Note that this is different from the normal Full Scale Error.
TOTAL HARMONIC DISTORTION (THD) is the ratio of the
rms total of the first six harmonic components, to the rms
value of the input signal.
Specification Definitions
ANALOG INPUT BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops
3 dB below its low frequency value for a full scale input. The
test is performed with fIN equal to 100 KHz plus integer multiples of fCLK. The input frequency at which the output is −3
dB relative to the low frequency input signal is the full power
bandwidth.
APERTURE JITTER is the time uncertainty of the sampling
point (tDS), or the range of variation in the sampling delay.
BOTTOM OFFSET is the difference between the input voltage that just causes the output code to transition to the first
code and the negative reference voltage. Bottom offset is
defined as EOB = VZT - VRB, where VZT is the first code transition input voltage. Note that this is different from the normal
Zero Scale Error.
DIFFERENTIAL GAIN ERROR is the percentage difference
between the output amplitudes of a high frequency reconstructed sine wave at two different dc levels.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
DIFFERENTIAL PHASE ERROR is the difference in the output phase of a reconstructed small signal sine wave at two
different dc levels.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as (SINAD 1.76) / 6.02 and says that the converter is equivalent to a
perfect ADC of this (ENOB) number of bits.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from zero
scale (1⁄2LSB below the first code transition) through positive
full scale (1⁄2LSB above the last code transition). The deviation of any given code from this straight line is measured
from the center of that code value. The end poinnt test
method is used.
OUTPUT DELAY is the time delay after the rising edge of
the input clock before the data update is present at the output pins.
OUTPUT HOLD TIME is the length of time that the output
data is valid after the rise of the input clock.
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and the availability of that
conversion result at the output. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay.
www.national.com
8
Timing Diagram
DS100890-11
FIGURE 1. ADC1173 Timing Diagram
DS100890-12
FIGURE 2. tEN, tDISTest Circuit
9
www.national.com
you desire to eliminate these adjustments, you should reduce the signal swing to avoid clipping at the ADC1173 output that can result from normal tolerances of all system components. With no adjustments, the nominal value for the
amplifier feedback resistor is 510Ω and the 5.1k resistor at
the inverting input should be changed to 860Ω and returned
to +3V rather than to the Offset Adjust potentiometer.
Functional Description
The ADC1173 uses a new, unique architecture to achieve
7.4 effective bits at and maintains superior dynamic performance up to 1⁄2 the clock frequency.
The analog signal at VIN that is within the voltage range set
by VRT and VRB are digitized to eight bits at up to 20 MSPS.
Input voltages below VRB will cause the output word to consist of all zeroes. Input voltages above VRT will cause the
output word to consist of all ones. VRT has a range of 1.0 Volt
to the analog supply voltage, AVDD, while VRB has a range of
0 to 2.0 Volts. VRT should always be at least 1.0 Volt more
positive than VRB.
If VRT and VRTS are connected together and VRB and VRBS
are connected together, the nominal values of VRT and VRB
are 1.56V and 0.36V, respectively. If VRT and VRTS are connected together and VRB is grounded, the nominal value of
VRT is 1.38V.
Data is acquired at the falling edge of the clock and the digital equivalent of the data is available at the digital outputs 2.5
clock cycles plus tOD later. The ADC1173 will convert as long
as the clock signal is present at pin 12. The Output Enable
pin OE, when low, enables the output pins. The digital outputs are in the high impedance state when the OE pin is
high.
2.0 Reference Inputs
The reference inputs VRT (Reference Top) and VRB (Reference Bottom) are the top and bottom of the reference ladder.
Input signals between these two voltages will be digitized to
8 bits. External voltages applied to the reference input pins
should be within the range specified in the Operating Ratings
table (1.0V to AVDD for VRT and 0V to (AVDD - 1.0V) for VRB).
Any device used to drive the reference pins should be able to
source sufficient current into the VRT pin and sink sufficient
current from the VRB pin.
The reference ladder can be self-biased by connecting VRT
to VRTS and connecting VRB to VRBS to provide top and bottom reference voltages of approximately 1.56V and 0.36V,
respectively, with VCC = 3.0V. This connection is shown in
Figure 3. If VRT and VRTS are tied together, but VRB is tied to
analog ground, a top reference voltage of approximately
1.38V is generated. The top and bottom of the ladder should
be bypassed with 10µF tantalum capacitors located close to
the reference pins.
The reference self-bias circuit of Figure 3 is very simple and
performance is adequate for many applications. Superior
performance can generally be achieved by driving the reference pins with a low impedance source.
By forcing a little current into or out of the top and bottom of
the ladder, as shown in Figure 4, the top and bottom reference voltages can be trimmed. The resistive divider at the
amplifier inputs can be replaced with potentiometers. The
LMC662 amplifier shown was chosen for its low offset voltage and low cost. Note that a negative power supply is
needed for these amplifiers as their outputs may be required
to go slightly negative to force the required reference
voltages.
Applications Information
1.0 The Analog Input
The analog input of the ADC1173 is a switch followed by an
integrator. The input capacitance changes with the clock
level, appearing as 4 pF when the clock is low, and 11 pF
when the clock is high. Since a dynamic capacitance is more
difficult to drive than a fixed capacitance, choose an amplifier
that can drive this type of load. The CLC409, CLC440,
LM6152, LM6154, LM6181 and LM6182 have been found to
be excellent devices for driving the ADC1173. Do not drive
the input beyond the supply rails.
Figure 3 shows an example of an input circuit using the
LM6181. This circuit has both gain and offset adjustments. If
www.national.com
10
Applications Information
(Continued)
DS100890-13
FIGURE 3. Simple, Low Component Count, Self -Bias Reference application. Because of resistor tolerances, the
reference voltages can vary by as much as 6%. Choose an amplifier that can drive a dynamic capacitance (see text).
11
www.national.com
Applications Information
(Continued)
DS100890-14
FIGURE 4. Better defining the ADC Reference Voltage. Self-bias is still used, but the reference voltages are trimmed
by providing a small trim current with the operational amplifiers.
www.national.com
12
Applications Information
(Continued)
DS100890-15
FIGURE 5. Driving the reference to force desired values requires driving with a low impedance source, provided by
the transistors. Note that pins 16 and 22 are not connected.
possible to the converter’s power supply pins. Leadless chip
capacitors are preferred because they have low lead inductance.
If reference voltages are desired that are more than a few
tens of millivolts from the self-bias values, the circuit of Figure 5 will allow forcing the reference voltages to whatever
levels are desired. This circuit provides the best performance
because of the low source impedance of the transistors.
Note that the VRTS and VRBS pins are left floating.
VRT can be anywhere between VRB + 1.0V and the analog
supply voltage, and VRB can be anywhere between ground
and 1.0V below VRT. To minimize noise effects and ensure
accurate conversions, the total reference voltage range (VRT
- VRB) should be a minimum of 1.0V and a maximum of
about VA. Best performance can be realized with VRT = 1.56
and VRB = 0.36V.
While a single voltage source should be used for the analog
and digital supplies of the ADC1173, these supply pins
should be well isolated from each other to prevent any digital
noise from being coupled to the analog power pins. A 47
Ohm resistor is recommend between the analog and digital
supply lines, with a ceramic capacitor close to the analog
supply pin. Avoid inductive components in the analog supply
line.
The converter digital supply should not be the supply that is
used for other digital circuitry on the board. It should be the
same supply used for the A/D analog supply.
3.0 Power Supply Considerations
Many A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A
10µF tantalum or aluminum electrolytic capacitor should be
placed within an of inch (2.5 centimeters) of the A/D power
pins, with a 0.1 µF ceramic chip capacitor placed as close as
As is the case with all high speed converters, the ADC1173
should be assumed to have little power supply rejection, especially when self-biasing is used by connecting VRT and
VRTS together.
No pin should ever have a voltage on it that is in excess of
the supply voltages or below ground, not even on a trasient
13
www.national.com
Applications Information
the high frequency components of the digital switching currents, directing them away from the analog pins. The relatively lower frequency analog ground currents do not see a
significant impedance across this narrow ground connection.
(Continued)
basis. This can be a problem upon application of power to a
circuit. Be sure that the supplies to circuits driving the CLK,
OE, analog input and reference pins do not come up any
faster than does the voltage at the ADC1173 power pins.
Generally, analog and digital lines should cross each other at
90 degrees to avoid getting digital noise into the analog path.
In video (high frequency) systems, however, avoid crossing
analog and digital lines altogether. Clock lines should be isolated from ALL other lines, analog and digital. Even the generally accepted 90 degree crossing should be avoided as
even a little coupling can cause problems at high frequencies. Best performance at high frequencies and at high resolution is obtained with a straight signal path.
4.0 The ADC1173 Clock
Although the ADC1173 is tested and its performance is guaranteed with a 15MHz clock, it typically will function with clock
frequencies from 1MHz to 20MHz.
If continuous conversions are not required, power consumption can be reduced somewhat by stopping the clock at a
logic low when the ADC1173 is not being used. This reduces
the current drain in the ADC1173’s digital circuitry from a
typical value of 2.3mA to about 100µA.
Note that powering up the ADC1173 with the clock stopped
may not save power, as it will result in an increased current
flow (by as much as 170%) in the reference ladder. In some
cases, this may increase the ladder current above the specified limit. Toggling the clock twice at 1MHz or higher and returning it to the low state will eliminate the excess ladder current.
An alternative power-saving technique is to power up the
ADC1173 with the clock active, then halt the clock in the low
state after two clock cycles. Stopping the clock in the high
state is not recommended as a power-saving technique.
Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit in
which they are used. Inductors should not be placed side by
side, not even with just a small part of their bodies being beside each other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter’s input and ground should be connected
to a very clean point in the analog ground return.
5.0 Layout and Grounding
Proper grounding and proper routing of all signals is essential to ensure accurate conversion. Separate analog and
digital ground planes that are connected beneath the
ADC1173 are required to meet data sheet limits. The analog
and digital grounds may be in the same layer, but should be
separated from each other. The analog and digital ground
planes should never overlap each other.
Capacitive coupling between the typically noisy digital
ground plane and the sensitive analog circuitry can lead to
poor performance that may seem impossible to isolate and
remedy. The solution is to keep the analog circuity well separated from the digital circuitry and from the digital ground
plane.
Digital circuits create substantial supply and ground transients. The logic noise thus generated could have significant
impact upon system noise performance. The best logic family to use in systems with A/D converters is one which employs non-saturating transistor designs, or has low noise
characteristics, such as the 74HC(T) and 74AC(T)Q families.
Worst noise generators are logic families that draw the largest supply current transients during clock or signal edges,
like the 74F and the 74AC(T) families. In general, slower
logic families, such as 74LS and 74HC(T), will produce less
high frequency noise than do high speed logic families, such
as the 74F and 74AC(T) families.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane volume.
An effective way to control ground noise is by connecting the
analog and digital ground planes together beneath the ADC
with a copper trace that is very narrow (about 3/16 inch)
compared with the rest of the ground plane. This narrowing
beneath the converter provides a fairly high impedance to
www.national.com
DS100890-16
FIGURE 6. Layout example showing separate analog
and digital ground planes connected below the
ADC1173.
Figure 6 gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference components, etc.)
should be placed on or over the analog ground plane. All
digital circuitry and I/O lines should be placed over the digital
ground plane.
6.0 Dynamic Performance
The ADC1173 is ac tested and its dynamic performance is
guaranteed. To meet the published specifications, the clock
source driving the CLK input must be free of jitter. For best
ac performance, isolating the ADC clock from any digital circuitry should be done with adequate buffers, as with a clock
tree. See Figure 7.
14
Applications Information
(Continued)
DS100890-17
FIGURE 7. Isolating the ADC clock from Digital Circuitry.
dynamic capacitance is more difficult to drive than is a fixed
capacitance, and should be considered when choosing a
driving device. The CLC409, CLC440, LM6152, LM6154,
LM6181 and LM6182 have been found to be excellent devices for driving the ADC1173 analog input.
Driving the VRT pin or the VRB pin with devices that can
not source or sink the current required by the ladder. As
mentioned in section 2.0, care should be taken to see that
any driving devices can source sufficient current into the VRT
pin and sink sufficient current from the VRB pin. If these pins
are not driven with devices than can handle the required current, these reference pins will not be stable, resulting in a reduction of dynamic performance.
Using a clock source with excessive jitter, using an excessively long clock signal trace, or having other signals coupled to the clock signal trace. This will cause the
sampling interval to vary, causing excessive output noise
and a reduction in SNR performance. Simple gates with RC
timing is generally inadequate as a clock source.
Input test signal contains harmonic distortion that interferes with the measurement of dynamic signal to noise
ratio. Harmonic and other interfering signals can be removed by inserting a filter at the signal input. Suitable filters
are shown in Figure 8 and Figure 9. The circuit of Figure 8
has cutoff of about 5.5 MHz and is suitable for input frequencies of 1 MHz to 5 MHz. The circuit of Figure 9 has a cutoff
of about 11 MHz and is suitable for input frequencies of 5
MHz to 10 MHz. These filters should be driven by a generator of 75 Ohm source impedance and terminated with a 75
ohm resistor.
It is good practice to keep the ADC clock line as short as
possible and to keep it well away from any other signals.
Other signals can introduce jitter into the clock signal.
7.0 Common Application Pitfalls
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 50mV below the ground pins or 50mV above the
supply pins. Exceeding these limits on even a transient basis
can cause faulty or erratic operation. It is not uncommon for
high speed digital circuits (e.g., 74F and 74AC devices) to
exhibit undershoot that goes more than a volt below ground.
A resistor of 50Ω in series with the offending digital input will
usually eliminate the problem.
Care should be taken not to overdrive the inputs of the
ADC1173. Such practice may lead to conversion inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current is
required from DVDD and DGND. These large charging current spikes can couple into the analog section, degrading dynamic performance. Buffering the digital data outputs (with
an 74ACQ541, for example) may be necessary if the data
bus to be driven is heavily loaded. Dynamic performance
can also be improved by adding 47Ω series resistors at each
digital output, reducing the energy coupled back into the
converter output pins.
Using an inadequate amplifier to drive the analog input.
As explained in Section 1.0, the capacitance seen at the input alternates between 4 pF and 11 pF with the clock. This
DS100890-18
FIGURE 8. 5.5 MHz Low Pass Filter to Eliminate Harmonics at the Signal Input.
DS100890-19
FIGURE 9. 11 MHz Low Pass filter to eliminate harmonics at the signal input.
Use at input frequencies of 5 MHz to 10 MHz
15
www.national.com
Physical Dimensions
inches (millimeters) unless otherwise noted
24-Lead Package JM
Ordering Number ADC1173CIJM
NS Package Number M24D
www.national.com
16
ADC1173 8-Bit, 3-Volt, 15MSPS, 33mW A/D Converter
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
24-Lead Package TC
Ordering Number ADC1173CIMTC
NS Package Number MTC24
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: [email protected]
www.national.com
National Semiconductor
Europe
Fax: +49 (0) 1 80-530 85 86
Email: [email protected]
Deutsch Tel: +49 (0) 1 80-530 85 85
English Tel: +49 (0) 1 80-532 78 32
Français Tel: +49 (0) 1 80-532 93 58
Italiano Tel: +49 (0) 1 80-534 16 80
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
Email: [email protected]
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.