PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs ² General Description Features The PC16550D is an improved version of the original 16450 Universal Asynchronous Receiver/Transmitter (UART). Functionally identical to the 16450 on powerup (CHARACTER mode)* the PC16550D can be put into an alternate mode (FIFO mode) to relieve the CPU of excessive software overhead. In this mode internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit modes. All the logic is on chip to minimize system overhead and maximize system efficiency. Two pin functions have been changed to allow signalling of DMA transfers. The UART performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt). The UART includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (216b1), and producing a 16 c clock for driving the internal transmitter logic. Provisions are also included to use this 16 c clock to drive the receiver logic. The UART has complete MODEM-control capability, and a processor-interrupt system. Interrupts can be programmed to the user’s requirements, minimizing the computing required to handle the communications link. The UART is fabricated using National Semiconductor’s advanced M2CMOS process. Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y *Can also be reset to 16450 Mode under software control. ² Note: This part is patented. Y Capable of running all existing 16450 software. Pin for pin compatible with the existing 16450 except for CSOUT (24) and NC (29). The former CSOUT and NC pins are TXRDY and RXRDY, respectively. After reset, all registers are identical to the 16450 register set. In the FIFO mode transmitter and receiver are each buffered with 16 byte FIFO’s to reduce the number of interrrupts presented to the CPU. Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data. Holding and shift registers in the 16450 Mode eliminate the need for precise synchronization between the CPU and serial data. Independently controlled transmit, receive, line status, and data set interrupts. Programmable baud generator divides any input clock by 1 to (216 b 1) and generates the 16 c clock. Independent receiver clock input. MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD). Fully programmable serial-interface characteristics: Ð 5-, 6-, 7-, or 8-bit characters Ð Even, odd, or no-parity bit generation and detection Ð 1-, 1(/2-, or 2-stop bit generation Ð Baud generation (DC to 1.5M baud). False start bit detection. Complete status reporting capabilities. TRI-STATEÉ TTL drive for the data and control buses. Line break generation and detection. Internal diagnostic capabilities: Ð Loopback controls for communications link fault isolation Ð Break, parity, overrun, framing error simulation. Full prioritized interrupt system controls. Basic Configuration TL/C/8652 – 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corp. C1995 National Semiconductor Corporation TL/C/8652 RRD-B30M75/Printed in U. S. A. PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs June 1995 Table of Contents 8.0 REGISTERS (Continued) 1.0 ABSOLUTE MAXIMUM RATINGS 8.3 Programmable Baud Generator 2.0 DC ELECTRICAL CHARACTERISTICS 8.4 Line Status Register 8.5 FIFO Control Register 8.6 Interrupt Identification Register 8.7 Interrupt Enable Register 8.8 Modem Control Register 8.9 Modem Status Register 8.10 Scratchpad Register 8.11 FIFO Interrupt Mode Operation 8.12 FIFO Polled Mode Operation 3.0 AC ELECTRICAL CHARACTERISTICS 4.0 TIMING WAVEFORMS 5.0 BLOCK DIAGRAM 6.0 PIN DESCRIPTIONS 7.0 CONNECTION DIAGRAMS 8.0 REGISTERS 8.1 Line Control Register 8.2 Typical Clock Circuits 9.0 TYPICAL APPLICATIONS 2 1.0 Absolute Maximum Ratings Temperature Under Bias b 65§ C to a 150§ C All Input or Output Voltages with Respect to VSS b 0.5V to a 7.0V Power Dissipation 2.0 Note: Maximum ratings indicate limits beyond which permanent damage may occur. Continuous operation at these limits is not intended and should be limited to those conditions specified under DC electrical characteristics. 0§ C to a 70§ C Storage Temperature 1W DC Electrical Characteristics TA e 0§ C to a 70§ C, VDD e a 5V g 10%, VSS e 0V, unless otherwise specified. Symbol Parameter Conditions Min Max Units VILX Clock Input Low Voltage b 0.5 VIHX Clock Input High Voltage 2.0 VIL Input Low Voltage b 0.5 0.8 V VIH Input High Voltage 2.0 VDD V VOL Output Low Voltage IOL e 1.6 mA on all (Note 1) VOH Output High Voltage IOH e b1.0 mA (Note 1) ICC(AV) Average Power Supply Current VDD e 5.5V, TA e 25§ C No Loads on output SIN, DSR, DCD, CTS, RI e 2.0V All other inputs e 0.8V IIL Input Leakage ICL Clock Leakage IOZ TRI-STATE Leakage VILMR MR Schmitt VIL VIHMR MR Schmitt VIH 0.8 V VDD V 0.4 2.4 V V VDD e 5.5V, VSS e 0V All other pins floating. VIN e 0V, 5.5V VDD e 5.5V, VSS e 0V VOUT e 0V, 5.25V 1) Chip deselected 2) WRITE mode, chip selected 15 mA g 10 mA g 10 mA g 20 mA 0.8 V 2.0 V Note 1: Does not apply to XOUT Capacitance TA e 25§ C, VDD e VSS e 0V Symbol CXIN Parameter Conditions Clock Input Capacitance fc e 1 MHz Unmeasured pins returned to VSS Min Typ Max Units 7 9 pF 7 9 pF CXOUT Clock Output Capacitance CIN Input Capacitance 5 7 pF COUT Output Capacitance 6 8 pF CI/O Input/Output Capacitance 10 12 pF 3 3.0 AC Electrical Characteristics TA e 0§ C to a 70§ C, VDD e a 5V g 10% Symbol Parameter Conditions Min Max Units tADS Address Strobe Width 60 ns tAH Address Hold Time 0 ns tAR RD, RD Delay from Address tAS Address Setup Time tAW WR, WR Delay from Address tCH Chip Select Hold Time tCS Chip Select Setup Time tCSR RD, RD Delay from Chip Select (Note 1) 30 ns tCSW WR, WR Delay from Select (Note 1) 30 ns tDH Data Hold Time 30 ns tDS Data Setup Time 30 tHZ RD, RD to Floating Data Delay tMR Master Reset Pulse Width tRA Address Hold Time from RD, RD tRC Read Cycle Delay tRCS Chip Select Hold Time from RD, RD tRD RD, RD Strobe Width tRDD RD, RD to Driver Enable/Disable tRVD Delay from RD, RD to Data tWA Address Hold Time from WR, WR tWC Write Cycle Delay tWCS Chip Select Hold Time from WR, WR tWR WR, WR Strobe Width tXH Duration of Clock High Pulse External Clock (8, Max.) tXL Duration of Clock Low Pulse External Clock (8, Max.) 55 ns RC Read Cycle e tAR a tRD a tRC Write Cycle e tAW a tWR a tWC 280 ns 280 ns WC (Note 1) (Note 1) @ 100 pF loading (Note 3) (Note 1) (Note 1) 30 ns 60 ns 30 ns 0 ns 60 ns 0 ns 100 5000 ns 20 ns 125 ns 20 ns 125 @ 100 pF loading (Note 3) @ 100 (Note 1) ns 60 pF loading (Note 1) ns 60 20 ns ns ns 150 ns 20 ns 100 ns 55 ns Baud Generator 1 216b1 N Baud Divisor tBHD Baud Output Positive Edge Delay 100 pF Load 175 tBLD Baud Output Negative Edge Delay 100 pF Load 175 tHW Baud Output Up Time fX e 8, d 2, 100 pF Load 75 ns tLW Baud Output Down Time fX e 8, d 2, 100 pF Load 100 ns ns ns Receiver tRAI Delay from Active Edge of RD to Reset Interrupt tRINT Delay from RD, RD (RD RBR/or RD LSR) to Reset Interrupt tRXI Delay from RD RBR to RXRDY Inactive tSCD Delay from RCLK to Sample Time tSINT Delay from Stop to Set Interrupt Ð ns 1000 ns 290 ns 100 pF Load (Note 2) 2000 ns 1 RCLK Cycles Note 1: Applicable only when ADS is tied low. Note 2: In the FIFO mode (FCR0 e 1) the trigger level interrupts, the receiver data available indication, the active RXRDY indication and the overrun error indication will be delayed 3 RCLKs. Status indicators (PE, FE, BI) will be delayed 3 RCLKs after the first byte has been received. For subsequently received bytes these indicators will be updated immediately after RDRBR goes inactive. Timeout interrupt is delayed 8 RCLKs. Note 3: Charge and discharge time is determined by VOL, VOH and the external loading. Note 4: These specifications are preliminary. 4 3.0 AC Electrical Characteristics (Continued) Symbol Parameter Conditions Min Max Units 175 ns 250 ns 8 24 BAUDOUT Cycles 16 24 BAUDOUT Cycles 8 8 BAUDOUT Cycles 8 BAUDOUT Cycles 195 ns 200 ns 250 ns 250 ns Transmitter tHR Delay from WR, WR (WR THR) to Reset Interrupt 100 pF Load tIR Delay from RD, RD (RD IIR) to Reset Interrupt (THRE) 100 pF Load tIRS Delay from Initial INTR Reset to Transmit Start tSI Delay from Initial Write to Interrupt (Note 1) tSTI Delay from Stop to Interrupt (THRE) (Note 1) tSXA Delay from Start to TXRDY active 100 pF Load tWXI Delay from Write to TXRDY inactive 100 pF Load tMDO Delay from WR, WR (WR MCR) to Output 100 pF Load tRIM Delay from RD, RD to Reset Interrupt (RD MSR) 100 pF Load tSIM Delay from MODEM Input to Set Interrupt 100 pF Load Modem Control Note 1: This delay will be lengthened by 1 character time, minus the last stop bit time if the transmitter interrupt delay circuit is active. (See FIFO Interrupt Mode Operation). Note 2: These specifications are preliminary. 4.0 Timing Waveforms (All timings are referenced to valid 0 and valid 1) External Clock Input (24.0 MHz Max.) AC Test Points TL/C/8652 – 3 TL/C/8652 – 2 Note 1: The 2.4V and 0.4V levels are the voltages that the inputs are driven to during AC testing. Note 2: The 2.0V and 0.8V levels are the voltages at which the timing tests are made. BAUDOUT Timing TL/C/8652 – 4 5 4.0 Timing Waveforms (Continued) Write Cycle TL/C/8652 – 5 *Applicable Only When ADS is Tied Low. Read Cycle TL/C/8652 – 6 *Applicable Only When ADS is Tied Low. 6 4.0 Timing Waveforms (Continued) Receiver Timing TL/C/8652 – 7 Transmitter Timing TL/C/8652 – 8 MODEM Control Timing TL/C/8652 – 9 Note 1: See Write Cycle Timing Note 2: See Read Cycle Timing 7 4.0 Timing Waveforms (Continued) RCVR FIFO First Byte (This Sets RDR) TL/C/8652 – 10 RCVR FIFO Bytes Other Than the First Byte (RDR Is Already Set) TL/C/8652 – 11 Receiver Ready (Pin 29) FCR0 e 0 or FCR0 e 1 and FCR3 e 0 (Mode 0) TL/C/8652 – 12 Note 1: This is the reading of the last byte in the FIFO. Note 2: If FCR0 e 1, then tSINT e 3 RCLKs. For a timeout interrupt, tSINT e 8 RCLKs. 8 4.0 Timing Waveforms (Continued) Receiver Ready (Pin 29) FCR0 e 1 and FCR3 e 1 (Mode 1) TL/C/8652 – 13 Note 1: This is the reading of the last byte in the FIFO. Note 2: If FCR0 e 1, tSINT e 3 RCLKs. Transmitter Ready (Pin 24) FCR0 e 0 or FCR0 e 1 and FCR3 e 0 (Mode 0) TL/C/8652 – 14 Transmitter Ready (Pin 24) FCR0 e 1 and FCR3 e 1 (Mode 1) TL/C/8652 – 15 9 5.0 Block Diagram TL/C/8652 – 16 Note: Applicable pinout numbers are included within parenthesis. 10 6.0 Pin Descriptions The following describes the function of all UART pins. Some of these descriptions reference internal circuits. In the following descriptions, a low represents a logic 0 (0V nominal) and a high represents a logic 1 ( a 2.4V nominal). A0, A1, A2, Register Select, Pins 26–28: Address signals connected to these 3 inputs select a UART register for the CPU to read from or write to during data transfer. A table of registers and their addresses is shown below. Note that the state of the Divisor Latch Access Bit (DLAB), which is the most significant bit of the Line Control Register, affects the selection of certain UART registers. The DLAB must be set high by the system software to access the Baud Generator Divisor Latches. D7 –D0, Data Bus, Pins 1 – 8: This bus comprises eight TRISTATE input/output lines. The bus provides bidirectional communications between the UART and the CPU. Data, control words, and status information are transferred via the D7 –D0 Data Bus. DCD, Data Carrier Detect, Pin 38: When low, indicates that the data carrier has been detected by the MODEM or data set. The DCD signal is a MODEM status input whose condition can be tested by the CPU reading bit 7 (DCD) of the MODEM Status Register. Bit 7 is the complement of the DCD signal. Bit 3 (DDCD) of the MODEM Status Register indicates whether the DCD input has changed state since the previous reading of the MODEM Status Register. DCD has no effect on the receiver. Register Addresses Note: Whenever the DCD bit of the MODEM Status Register changes state, an interrupt is generated if the MODEM Status Interrupt is enabled. DLAB A2 A1 A0 Register 0 0 0 0 0 X X X X X X X 1 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 1 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 Receiver Buffer (read), Transmitter Holding Register (write) Interrupt Enable Interrupt Identification (read) FIFO Control (write) Line Control MODEM Control Line Status MODEM Status Scratch Divisor Latch (least significant byte) Divisor Latch (most significant byte) DDIS, Driver Disable, Pin 23: This goes low whenever the CPU is reading data from the UART. It can disable or control the direction of a data bus transceiver between the CPU and the UART. DSR, Data Set Ready, Pin 37: When low, this indicates that the MODEM or data set is ready to establish the communications link with the UART. The DSR signal is a MODEM status input whose condition can be tested by the CPU reading bit 5 (DSR) of the MODEM Status Register. Bit 5 is the complement of the DSR signal. Bit 1 (DDSR) of the MODEM Status Register indicates whether the DSR input has changed state since the previous reading of the MODEM Status Register. Note: Whenever the DDSR bit of the MODEM Status Register changes state, an interrupt is generated if the MODEM Status Interrupt is enabled. DTR, Data Terminal Ready, Pin 33: When low, this informs the MODEM or data set that the UART is ready to establish a communications link. The DTR output signal can be set to an active low by programming bit 0 (DTR) of the MODEM Control Register to a high level. A Master Reset operation sets this signal to its inactive (high) state. Loop mode operation holds this signal in its inactive state. INTR, Interrupt, Pin 30: This pin goes high whenever any one of the following interrupt types has an active high condition and is enabled via the IER: Receiver Error Flag; Received Data Available: timeout (FIFO Mode only); Transmitter Holding Register Empty; and MODEM Status. The INTR signal is reset low upon the appropriate interrupt service or a Master Reset operation. MR, Master Reset, Pin 35: When this input is high, it clears all the registers (except the Receiver Buffer, Transmitter Holding, and Divisor Latches), and the control logic of the UART. The states of various output signals (SOUT, INTR, OUT 1, OUT 2, RTS, DTR) are affected by an active MR input (Refer to Table I.) This input is buffered with a TTLcompatible Schmitt Trigger with 0.5V typical hysteresis. OUT 1, Output 1, Pin 34: This user-designated output can be set to an active low by programming bit 2 (OUT 1) of the MODEM Control Register to a high level. A Master Reset operation sets this signal to its inactive (high) state. Loop mode operation holds this signal in its inactive state. In the XMOS parts this will achieve TTL levels. ADS, Address Strobe, Pin 25: The positive edge of an active Address Strobe (ADS) signal latches the Register Select (A0, A1, A2) and Chip Select (CS0, CS1, CS2) signals. Note: An active ADS input is required when the Register Select (A0, A1, A2) and Chip Select (CS0, CS1, CS2) signals are not stable for the duration of a read or write operation. If not required, tie the ADS input permanently low. BAUDOUT, Baud Out, Pin 15: This is the 16 c clock signal from the transmitter section of the UART. The clock rate is equal to the main reference oscillator frequency divided by the specified divisor in the Baud Generator Divisor Latches. The BAUDOUT may also be used for the receiver section by tying this output to the RCLK input of the chip. CS0, CS1, CS2, Chip Select, Pins 12–14: When CS0 and CS1 are high and CS2 is low, the chip is selected. This enables communication between the UART and the CPU. The positive edge of an active Address Strobe signal latches the decoded chip select signals, completing chip selection. If ADS is always low, valid chip selects should stabilize according to the tCSW parameter. CTS, Clear to Send, Pin 36: When low, this indicates that the MODEM or data set is ready to exchange data. The CTS signal is a MODEM status input whose conditions can be tested by the CPU reading bit 4 (CTS) of the MODEM Status Register. Bit 4 is the complement of the CTS signal. Bit 0 (DCTS) of the MODEM Status Register indicates whether the CTS input has changed state since the previous reading of the MODEM Status Register. CTS has no effect on the Transmitter. Note: Whenever the CTS bit of the MODEM Status Register changes state, an interrupt is generated if the MODEM Status Interrupt is enabled. 11 6.0 Pin Descriptions (Continued) OUT 2, Output 2, Pin 31: This user-designated output that can be set to an active low by programming bit 3 (OUT 2) of the MODEM Control Register to a high level. A Master Reset operation sets this signal to its inactive (high) state. Loop mode operation holds this signal in its inactive state. In the XMOS parts this will achieve TTL levels. RCLK, Receiver Clock, Pin 9: This input is the 16 c baud rate clock for the receiver section of the chip. RD, RD, Read, Pins 22 and 21: When RD is high or RD is low while the chip is selected, the CPU can read status information or data from the selected UART register. TXRDY, Mode 0: In the 16450 Mode (FCR0 e 0) or in the FIFO Mode (FCR0 e 1, FCR3 e 0) and there are no characters in the XMIT FIFO or XMIT holding register, the TXRDY pin (24) will be low active. Once it is activated the TXRDY pin will go inactive after the first character is loaded into the XMIT FIFO or holding register. TXRDY, Mode 1: In the FIFO Mode (FCR0 e 1) when FCR3 e 1 and there are no characters in the XMIT FIFO, the TXRDY pin will go low active. This pin will become inactive when the XMIT FIFO is completely full. VDD, Pin 40: a 5V supply. Note: Only an active RD or RD input is required to transfer data from the UART during a read operation. Therefore, tie either the RD input permanently low or the RD input permanently high, when it is not used. VSS, Pin 20: Ground (0V) reference. WR, WR, Write, Pins 19 and 18: When WR is high or WR is low while the chip is selected, the CPU can write control words or data into the selected UART register. RI, Ring Indicator, Pin 39: When low, this indicates that a telephone ringing signal has been received by the MODEM or data set. The RI signal is a MODEM status input whose condition can be tested by the CPU reading bit 6 (RI) of the MODEM Status Register. Bit 6 is the complement of the RI signal. Bit 2 (TERI) of the MODEM Status Register indicates whether the RI input signal has changed from a low to a high state since the previous reading of the MODEM Status Register. Note: Only an active WR or WR input is required to transfer data to the UART during a write operation. Therefore, tie either the WR input permanently low or the WR input permanently high, when it is not used. XIN (External Crystal Input), Pin 16: This signal input is used in conjunction with XOUT to form a feedback circuit for the baud rate generator’s oscillator. If a clock signal will be generated off-chip, then it should drive the baud rate generator through this pin. XOUT (External Crystal Output), Pin 17: This signal output is used in conjunction with XIN to form a feedback circuit for the baud rate generator’s oscillator. If the clock signal will be generated off-chip, then this pin is unused. Note: Whenever the RI bit of the MODEM Status Register changes from a high to a low state, an interrupt is generated if the MODEM Status Interrupt is enabled. RTS, Request to Send, Pin 32: When low, this informs the MODEM or data set that the UART is ready to exchange data. The RTS output signal can be set to an active low by programming bit 1 (RTS) of the MODEM Control Register. A Master Reset operation sets this signal to its inactive (high) state. Loop mode operation holds this signal in its inactive state. SIN, Serial Input, Pin 10: Serial data input from the communications link (peripheral device, MODEM, or data set). SOUT, Serial Output, Pin 11: Composite serial data output to the communications link (peripheral, MODEM or data set). The SOUT signal is set to the Marking (logic 1) state upon a Master Reset operation. TXRDY, RXRDY, Pins 24, 29: Transmitter and Receiver DMA signalling is available through two pins (24 and 29). When operating in the FIFO mode, one of two types of DMA signalling per pin can be selected via FCR3. When operating as in the 16450 Mode, only DMA mode 0 is allowed. Mode 0 supports single transfer DMA where a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA where multiple transfers are made continuously until the RCVR FIFO has been emptied or the XMIT FIFO has been filled. RXRDY, Mode 0: When in the 16450 Mode (FCR0 e 0) or in the FIFO Mode (FCR0 e 1, FCR3 e 0) and there is at least 1 character in the RCVR FIFO or RCVR holding register, the RXRDY pin (29) will be low active. Once it is activated the RXRDY pin will go inactive when there are no more characters in the FIFO or holding register. RXRDY, Mode 1: In the FIFO Mode (FCR0 e 1) when the FCR3 e 1 and the trigger level or the timeout has been reached, the RXRDY pin will go low active. Once it is activated it will go inactive when there are no more characters in the FIFO or holding register. 7.0 Connection Diagrams Dual-In-Line Package TL/C/8652 – 17 Top View Order Number PC16550DN See NS Package Number N40A 12 7.0 Connection Diagrams (Continued) Chip Carrier Package TQFP Package TL/C/8652 – 26 TL/C/8652 – 18 Order Number PC16550DVEF See NS Package Number VEF44A Top View Order Number PC16550DV See NS Package Number V44A TABLE I. UART Reset Configuration Register/Signal Reset Control Reset State Interrupt Enable Register Master Reset 0000 Interrupt Identification Register Master Reset 0000 FIFO Control Master Reset 0000 Line Control Register Master Reset 0000 MODEM Control Register Master Reset 0000 Line Status Register Master Reset 0110 MODEM Status Register Master Reset XXXX SOUT Master Reset High INTR (RCVR Errs) Read LSR/MR Low INTR (RCVR Data Ready) Read RBR/MR Low Read IIR/Write THR/MR Low INTR (THRE) INTR (Modem Status Changes) Read MSR/MR Low OUT 2 Master Reset High RTS Master Reset High DTR Master Reset High OUT 1 Master Reset 0000 0000 0000 0000 0000 0000 High RCVR FIFO MR/FCR1 # FCR0/DFCR0 All Bits Low XMIT FIFO MR/FCR1 # FCR0/DFCR0 All Bits Low Note 1: Boldface bits are permanently low. Note 2: Bits 7–4 are driven by the input signals. 13 (Note 1) 0001 (Note 2) 14 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 4 5 6 7 Data Bit 7 Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2 0 0 0 0 Enable MODEM Status Interrupt (EDSSI) Enable Receiver Line Status Interrupt (ELSI) Enable Transmitter Holding Register Empty Interrupt (ETBEI) IER Enable Received Data Available Interrupt (ERBFI) Interrupt Enable Register 1 DLAB e 0 2 FIFOs Enabled (Note 2) FIFOs Enabled (Note 2) 0 0 Interrupt ID Bit (2) (Note 2) Interrupt ID Bit (1) Interrupt ID Bit (0) IIR ‘‘0’’ if Interrupt Pending Interrupt Ident. Register (Read Only) Note 2: These bits are always 0 in the 16450 Mode. Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received. Data Bit 3 Data Bit 2 2 3 Data Bit 1 1 Data Bit 1 THR Data Bit 0 RBR Data Bit 0 (Note 1) 0 0 DLAB e 0 Transmitter Holding Register (Write Only) 0 DLAB e 0 Receiver Buffer Register (Read Only) Bit No. RCVR Trigger (MSB) RCVR Trigger (LSB) Reserved Reserved DMA Mode Select XMIT FIFO Reset RCVR FIFO Reset FCR FIFO Enable FIFO Control Register (Write Only) Divisor Latch Access Bit (DLAB) Set Break Even Parity Select (EPS) Stick Parity Parity Enable (PEN) Number of Stop Bits (STB) Word Length Select Bit 1 (WLS1) LCR Word Length Select Bit 0 (WLS0) Line Control Register 0 0 0 Loop Out 2 Out 1 Request to Send (RTS) MCR Data Terminal Ready (DTR) MODEM Control Register TABLE II. Summary of Registers Register Address 2 3 4 Error in RCVR FIFO (Note 2) Transmitter Empty (TEMT) Transmitter Holding Register (THRE) Break Interrupt (BI) Framing Error (FE) Parity Error (PE) Overrun Error (OE) LSR Data Ready (DR) Line Status Register 5 Data Carrier Detect (DCD) Ring Indicator (RI) Clear to Send (CTS) Data Set Ready (DSR) Delta Data Carrier Detect (DDCD) Trailing Edge Ring Indicator (TERI) Delta Data Set Ready (DDSR) MSR Delta Clear to Send (DCTS) MODEM Status Register 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 SCR Bit 0 Scratch Register 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 DLL Bit 0 Divisor Latch (LS) 0 DLAB e 1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 DLM Bit 8 Divisor Latch (MS) 1 DLAB e 1 8.0 Registers Bit 3: This bit is the Parity Enable bit. When bit 3 is a logic 1, a Parity bit is generated (transmit data) or checked (receive data) between the last data word bit and Stop bit of the serial data. (The Parity bit is used to produce an even or odd number of 1s when the data word bits and the Parity bit are summed.) Bit 4: This bit is the Even Parity Select bit. When bit 3 is a logic 1 and bit 4 is a logic 0, an odd number of logic 1s is transmitted or checked in the data word bits and Parity bit. When bit 3 is a logic 1 and bit 4 is a logic 1, an even number of logic 1s is transmitted or checked. Bit 5: This bit is the Stick Parity bit. When bits 3, 4 and 5 are logic 1 the Parity bit is transmitted and checked as a logic 0. If bits 3 and 5 are 1 and bit 4 is a logic 0 then the Parity bit is transmitted and checked as a logic 1. If bit 5 is a logic 0 Stick Parity is disabled. Bit 6: This bit is the Break Control bit. It causes a break condition to be transmitted to the receiving UART. When it is set to a logic 1, the serial output (SOUT) is forced to the Spacing (logic 0) state. The break is disabled by setting bit 6 to a logic 0. The Break Control bit acts only on SOUT and has no effect on the transmitter logic. The system programmer may access any of the UART registers summarized in Table II via the CPU. These registers control UART operations including transmission and reception of data. Each register bit in Table II has its name and reset state shown. 8.1 LINE CONTROL REGISTER The system programmer specifies the format of the asynchronous data communications exchange and set the Divisor Latch Access bit via the Line Control Register (LCR). The programmer can also read the contents of the Line Control Register. The read capability simplifies system programming and eliminates the need for separate storage in system memory of the line characteristics. Table II shows the contents of the LCR. Details on each bit follow: Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character. The encoding of bits 0 and 1 is as follows: Bit 1 Bit 0 Character Length 0 0 1 1 0 1 0 1 5 Bits 6 Bits 7 Bits 8 Bits Note: This feature enables the CPU to alert a terminal in a computer communications system. If the following sequence is followed, no erroneous or extraneous characters will be transmitted because of the break. 1. Load an all 0s, pad character, in response to THRE. Bit 2: This bit specifies the number of Stop bits transmitted and received in each serial character. If bit 2 is a logic 0, one Stop bit is generated in the transmitted data. If bit 2 is a logic 1 when a 5-bit word length is selected via bits 0 and 1, one and a half Stop bits are generated. If bit 2 is a logic 1 when either a 6-, 7-, or 8-bit word length is selected, two Stop bits are generated. The Receiver checks the first Stopbit only, regardless of the number of Stop bits selected. 2. Set break after the next THRE. 3. Wait for the transmitter to be idle, (TEMT e 1), and clear break when normal transmission has to be restored. During the break, the Transmitter can be used as a character timer to accurately establish the break duration. TABLE III. Baud Rates, Divisors and Crystals 1.8432 MHz Cystal Baud Rate Decimal Divisor for 16 c Clock 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 128000 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 Ð 3.072 MHz Crystal Percent Error Decimal Divisor for 16 c Clock Ð Ð 0.026 0.058 Ð Ð Ð Ð Ð 0.69 Ð Ð Ð Ð Ð Ð Ð 2.86 Ð 3840 2560 1745 1428 1280 640 320 160 107 96 80 53 40 27 20 10 5 Ð Ð Percent Error Percent Error Ð Ð 0.026 0.034 Ð Ð Ð Ð 0.312 Ð Ð 0.628 Ð 1.23 Ð Ð Ð Ð Ð 23040 15360 10473 8565 7680 3840 1920 920 640 576 480 320 240 160 120 60 30 21 9 Ð Ð Ð Ð Ð Ð Ð Ð Ð Ð Ð Ð Ð Ð Ð Ð Ð 2.04 Ð Note: For baud rates of 250k, 300k, 375k, 500k, 750k and 1.5M using a 24 MHz crystal causes minimal error. 15 18.432 MHz Crystal Decimal Divisor for 16 c Clock 8.0 Registers (Continued) Bit 7: This bit is the Divisor Latch Access Bit (DLAB). It must be set high (logic 1) to access the Divisor Latches of the Baud Generator during a Read or Write operation. It must be set low (logic 0) to access the Receiver Buffer, the Transmitter Holding Register, or the Interrupt Enable Register. 8.2 8.4 TYPICAL CLOCK CIRCUITS TL/C/8652–19 TL/C/8652–20 Typical Crystal Oscillator Network (Note) CRYSTAL RP RX2 C1 C2 3.1 MHz 1 MX 1.5k 10-30 pF 40-60 pF 1.8 MHz 1 MX 1.5k 10-30 pF 40-60 pF LINE STATUS REGISTER This register provides status information to the CPU concerning the data transfer. Table II shows the contents of the Line Status Register. Details on each bit follow. Bit 0: This bit is the receiver Data Ready (DR) indicator. Bit 0 is set to a logic 1 whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO. Bit 0 is reset to a logic 0 by reading all of the data in the Receiver Buffer Register or the FIFO. Bit 1: This bit is the Overrun Error (OE) indicator. Bit 1 indicates that data in the Receiver Buffer Register was not read by the CPU before the next character was transferred into the Receiver Buffer Register, thereby destroying the previous character. The OE indicator is set to a logic 1 upon detection of an overrun condition and reset whenever the CPU reads the contents of the Line Status Register. If the FIFO mode data continues to fill the FIFO beyond the trigger level, an overrun error will occur only after the FIFO is full and the next character has been completely received in the shift register. OE is indicated to the CPU as soon as it happens. The character in the shift register is overwritten, but it is not transferred to the FIFO. Bit 2: This bit is the Parity Error (PE) indicator. Bit 2 indicates that the received data character does not have the correct even or odd parity, as selected by the even-parityselect bit. The PE bit is set to a logic 1 upon detection of a parity error and is reset to a logic 0 whenever the CPU reads the contents of the Line Status Register. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is revealed to the CPU when its associated character is at the top of the FIFO. Bit 3: This bit is the Framing Error (FE) indicator. Bit 3 indicates that the received character did not have a valid Stop bit. Bit 3 is set to a logic 1 whenever the Stop bit following the last data bit or parity bit is detected as a logic 0 bit (Spacing level). The FE indicator is reset whenever the CPU reads the contents of the Line Status Register. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is revealed to the CPU when its associated character is at the top of the FIFO. The UART will try to resynchronize after a framing error. To do this it assumes that the framing error was due to the next start bit, so it samples this ‘‘start’’ bit twice and then takes in the ‘‘data’’. Bit 4: This bit is the Break Interrupt (BI) indicator. Bit 4 is set to a logic 1 whenever the received data input is held in the Spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit a data bits a Parity a Stop bits). The BI indicator is reset whenever the CPU reads the contents of the Line Status Register. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is revealed to the CPU when its associated character is at the top of the FIFO. When break occurs only one zero character is loaded into the FIFO. The next character transfer is enabled after SIN goes to the marking state and receives the next valid start bit. Note: These R and C values are approximate and may vary 2x depending on the crystal characteristics. All crystal circuits should be designed specifically for the system. 8.3 PROGRAMMABLE BAUD GENERATOR The UART contains a programmable Baud Generator that is capable of taking any clock input from DC to 24 MHz and dividing it by any divisor from 2 to 216b1. The output frequency of the Baud Generator is 16 c the Baud [divisor Ý e (frequency input) d (baud rate c 16)]. Two 8-bit latches store the divisor in a 16-bit binary format. These Divisor Latches must be loaded during initialization to ensure proper operation of the Baud Generator. Upon loading either of the Divisor Latches, a 16-bit Baud counter is immediately loaded. Table III provides decimal divisors to use with crystal frequencies of 1.8432 MHz, 3.072 MHz and 18.432 MHz, respectively. For baud rates of 38400 and below, the error obtained is minimal. The accuracy of the desired baud rate is dependent on the crystal frequency chosen. Using a divisor of zero is not recommended. Note: Bits 1 through 4 are the error conditions that produce a Receiver Line Status interrupt whenever any of the corresponding conditions are detected and the interrupt is enabled. 16 8.0 Registers (Continued) TABLE IV. Interrupt Control Functions FIFO Mode Only Interrupt Identification Register Bit 3 Bit 2 Bit 1 Bit 0 Interrupt Set and Reset Functions Priority Level Ð Interrupt Type None Interrupt Source Interrupt Reset Control 0 0 0 1 0 1 1 0 Highest Receiver Line Status None Ð 0 1 0 0 Second Received Data Available Receiver Data Available or Trigger Level Reached Reading the Receiver Buffer Register or the FIFO Drops Below the Trigger Level 1 1 0 0 Second Character Timeout Indication No Characters Have Been Removed From or Input to the RCVR FIFO During the Last 4 Char. Times and There Is at Least 1 Char. in It During This Time Reading the Receiver Buffer Register 0 0 1 0 Third Transmitter Holding Register Empty Transmitter Holding Register Empty Reading the IIR Register (if source of interrupt) or Writing into the Transmitter Holding Register 0 0 0 0 Fourth MODEM Status Clear to Send or Data Set Ready or Ring Indicator or Data Carrier Detect Reading the MODEM Status Register Overrun Error or Parity Error or Framing Error or Break Interrupt Reading the Line Status Register When changing from the FIFO Mode to the 16450 Mode and vice versa, data is automatically cleared from the FIFOs. This bit must be a 1 when other FCR bits are written to or they will not be programmed. Bit 1: Writing a 1 to FCR1 clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift register is not cleared. The 1 that is written to this bit position is self-clearing. Bit 2: Writing a 1 to FCR2 clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift register is not cleared. The 1 that is written to this bit position is self-clearing. Bit 3: Setting FCR3 to a 1 will cause the RXRDY and TXRDY pins to change from mode 0 to mode 1 if FCR0 e 1 (see description of RXRDY and TXRDY pins). Bit 4, 5: FCR4 to FCR5 are reserved for future use. Bit 6, 7: FCR6 and FCR7 are used to set the trigger level for the RCVR FIFO interrupt. Bit 5: This bit is the Transmitter Holding Register Empty (THRE) indicator. Bit 5 indicates that the UART is ready to accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to the CPU when the Transmit Holding Register Empty Interrupt enable is set high. The THRE bit is set to a logic 1 when a character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. The bit is reset to logic 0 concurrently with the loading of the Transmitter Holding Register by the CPU. In the FIFO mode this bit is set when the XMIT FIFO is empty; it is cleared when at least 1 byte is written to the XMIT FIFO. Bit 6: This bit is the Transmitter Empty (TEMT) indicator. Bit 6 is set to a logic 1 whenever the Transmitter Holding Register (THR) and the Transmitter Shift Register (TSR) are both empty. It is reset to a logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode this bit is set to one whenever the transmitter FIFO and shift register are both empty. Bit 7: In the 16450 Mode this is a 0. In the FIFO mode LSR7 is set when there is at least one parity error, framing error or break indication in the FIFO. LSR7 is cleared when the CPU reads the LSR, if there are no subsequent errors in the FIFO. Note: The Line Status Register is intended for read operations only. Writing to this register is not recommended as this operation is only used for factory testing. In the FIFO mode the software must load a data byte in the Rx FIFO via Loopback Mode in order to write to LSR2–LSR4. LSR0 and LSR7 can’t be written to in FIFO mode. 7 6 RCVR FIFO Trigger Level (Bytes) 0 0 1 1 0 1 0 1 01 04 08 14 8.6 INTERRUPT IDENTIFICATION REGISTER In order to provide minimum software overhead during data character transfers, the UART prioritizes interrupts into four levels and records these in the interrupt Identification Register. The four levels of interrupt conditions in order of priority are Receiver Line Status; Received Data Ready; Transmitter Holding Register Empty; and MODEM Status. 8.5 FIFO CONTROL REGISTER This is a write only register at the same location as the IIR (the IIR is a read only register). This register is used to enable the FIFOs, clear the FIFOs, set the RCVR FIFO trigger level, and select the type of DMA signalling. Bit 0: Writing a 1 to FCR0 enables both the XMIT and RCVR FIFOs. Resetting FCR0 will clear all bytes in both FIFOs. 17 8.0 Registers (Continued) Bit 3: This bit controls the Output 2 (OUT 2) signal, which is an auxiliary user-designated output. Bit 3 affects the OUT 2 output in a manner identical to that described above for bit 0. Bit 4: This bit provides a local loopback feature for diagnostic testing of the UART. When bit 4 is set to logic 1, the following occur: the transmitter Serial Output (SOUT) is set to the Marking (logic 1) state; the receiver Serial Input (SIN) is disconnected; the output of the Transmitter Shift Register is ‘‘looped back’’ into the Receiver Shift Register input; the four MODEM Control inputs (DSR, CTS, RI, and DCD) are disconnected; and the four MODEM Control outputs (DTR, RTS, OUT 1, and OUT 2) are internally connected to the four MODEM Control inputs, and the MODEM Control output pins are forced to their inactive state (high). In the loopback mode, data that is transmitted is immediately received. This feature allows the processor to verify the transmit-and received-data paths of the UART. In the loopback mode, the receiver and transmitter interrupts are fully operational. Their sources are external to the part. The MODEM Control Interrupts are also operational, but the interrupts’ sources are now the lower four bits of the MODEM Control Register instead of the four MODEM Control inputs. The interrupts are still controlled by the Interrupt Enable Register. Bits 5 through 7: These bits are permanently set to logic 0. When the CPU accesses the IIR, the UART freezes all interrupts and indicates the highest priority pending interrupt to the CPU. While this CPU access is occurring, the UART records new interrupts, but does not change its current indication until the access is complete. Table II shows the contents of the IIR. Details on each bit follow: Bit 0: This bit can be used in a prioritized interrupt environment to indicate whether an interrupt is pending. When bit 0 is a logic 0, an interrupt is pending and the IIR contents may be used as a pointer to the appropriate interrupt service routine. When bit 0 is a logic 1, no interrupt is pending. Bits 1 and 2: These two bits of the IIR are used to identify the highest priority interrupt pending as indicated in Table IV. Bit 3: In the 16450 Mode this bit is 0. In the FIFO mode this bit is set along with bit 2 when a timeout interrupt is pending. Bits 4 and 5: These two bits of the IIR are always logic 0. Bits 6 and 7: These two bits are set when FCR0 e 1. 8.7 INTERRUPT ENABLE REGISTER This register enables the five types of UART interrupts. Each interrupt can individually activate the interrupt (INTR) output signal. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of the Interrupt Enable Register (IER). Similarly, setting bits of the IER register to a logic 1, enables the selected interrupt(s). Disabling an interrupt prevents it from being indicated as active in the IIR and from activating the INTR output signal. All other system functions operate in their normal manner, including the setting of the Line Status and MODEM Status Registers. Table II shows the contents of the IER. Details on each bit follow. Bit 0: This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic 1. Bit 1: This bit enables the Transmitter Holding Register Empty Interrupt when set to logic 1. Bit 2: This bit enables the Receiver Line Status Interrupt when set to logic 1. Bit 3: This bit enables the MODEM Status Interrupt when set to logic 1. Bits 4 through 7: These four bits are always logic 0. 8.9 MODEM STATUS REGISTER This register provides the current state of the control lines from the MODEM (or peripheral device) to the CPU. In addition to this current-state information, four bits of the MODEM Status Register provide change information. These bits are set to a logic 1 whenever a control input from the MODEM changes state. They are reset to logic 0 whenever the CPU reads the MODEM Status Register. The contents of the MODEM Status Register are indicated in Table II and described below. Bit 0: This bit is the Delta Clear to Send (DCTS) indicator. Bit 0 indicates that the CTS input to the chip has changed state since the last time it was read by the CPU. Bit 1: This bit is the Delta Data Set Ready (DDSR) indicator. Bit 1 indicates that the DSR input to the chip has changed state since the last time it was read by the CPU. Bit 2: This bit is the Trailing Edge of Ring Indicator (TERI) detector. Bit 2 indicates that the RI input to the chip has changed from a low to a high state. Bit 3: This bit is the Delta Data Carrier Detect (DDCD) indicator. Bit 3 indicates that the DCD input to the chip has changed state. 8.8 MODEM CONTROL REGISTER This register controls the interface with the MODEM or data set (or a peripheral device emulating a MODEM). The contents of the MODEM Control Register are indicated in Table II and are described below. Bit 0: This bit controls the Data Terminal Ready (DTR) output. When bit 0 is set to a logic 1, the DTR output is forced to a logic 0. When bit 0 is reset to a logic 0, the DTR output is forced to a logic 1. Note: Whenever bit 0, 1, 2, or 3 is set to logic 1, a MODEM Status Interrupt is generated. Bit 4: This bit is the complement of the Clear to Send (CTS) input. If bit 4 (loop) of the MCR is set to a 1, this bit is equivalent to RTS in the MCR. Bit 5: This bit is the complement of the Data Set Ready (DSR) input. If bit 4 of the MCR is set to a 1, this bit is equivalent to DTR in the MCR. Bit 6: This bit is the complement of the Ring Indicator (RI) input. If bit 4 of the MCR is set to a 1, this bit is equivalent to OUT 1 in the MCR. Note: The DTR output of the UART may be applied to an EIA inverting line driver (such as the DS1488) to obtain the proper polarity input at the succeeding MODEM or data set. Bit 1: This bit controls the Request to Send (RTS) output. Bit 1 affects the RTS output in a manner identical to that described above for bit 0. Bit 2: This bit controls the Output 1 (OUT 1) signal, which is an auxiliary user-designated output. Bit 2 affects the OUT 1 output in a manner identical to that described above for bit 0. 18 8.0 Registers (Continued) B. The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time whenever the following occurs: THRE e 1 and there have not been at least two bytes at the same time in the transmit FIFO, since the last THRE e 1. The first transmitter interrupt after changing FCR0 will be immediate, if it is enabled. Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received data available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty interrupt. Bit 7: This bit is the complement of the Data Carrier Detect (DCD) input. If bit 4 of the MCR is set to a 1, this bit is equivalent to OUT 2 in the MCR. 8.10 SCRATCHPAD REGISTER This 8-bit Read/Write Register does not control the UART in anyway. It is intended as a scratchpad register to be used by the programmer to hold data temporarily. 8.11 FIFO INTERRUPT MODE OPERATION When the RCVR FIFO and receiver interrupts are enabled (FCR0 e 1, IER0 e 1) RCVR interrupts will occur as follows: 8.12 FIFO POLLED MODE OPERATION With FCR0 e 1 resetting IER0, IER1, IER2, IER3 or all to zero puts the UART in the FIFO Polled Mode of operation. Since the RCVR and XMITTER are controlled separately either one or both can be in the polled mode of operation. In this mode the user’s program will check RCVR and XMITTER status via the LSR. As stated previously: LSR0 will be set as long as there is one byte in the RCVR FIFO. LSR1 to LSR4 will specify which error(s) has occurred. Character error status is handled the same way as when in the interrupt mode, the IIR is not affected since IER2 e 0. LSR5 will indicate when the XMIT FIFO is empty. LSR6 will indicate that both the XMIT FIFO and shift register are empty. LSR7 will indicate whether there are any errors in the RCVR FIFO. There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the RCVR and XMIT FIFOs are still fully capable of holding characters. A. The receive data available interrupt will be issued to the CPU when the FIFO has reached its programmed trigger level; it will be cleared as soon as the FIFO drops below its programmed trigger level. B. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the interrupt it is cleared when the FIFO drops below the trigger level. C. The receiver line status interrupt (IIR e 06), as before, has higher priority than the received data available (IIR e 04) interrupt. D. The data ready bit (LSR0) is set as soon as a character is transferred from the shift register to the RCVR FIFO. It is reset when the FIFO is empty. When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO timeout interrupts will occur as follows: A. A FIFO timeout interrupt will occur, if the following conditions exist: Ð at least one character is in the FIFO Ð the most recent serial character received was longer than 4 continuous character times ago (if 2 stop bits are programmed the second one is included in this time delay). Ð the most recent CPU read of the FIFO was longer than 4 continuous character times ago. The maximum time between a received character and a timeout interrupt will be 160 ms at 300 baud with a 12-bit receive character (i.e., 1 Start, 8 Data, 1 Parity and 2 Stop Bits). B. Character times are calculated by using the RCLK input for a clock signal (this makes the delay proportional to the baudrate). C. When a timeout interrupt has occurred it is cleared and the timer reset when the CPU reads one character from the RCVR FIFO. D. When a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after the CPU reads the RCVR FIFO. When the XMIT FIFO and transmitter interrupts are enabled (FCR0 e 1, IER1 e 1), XMIT interrupts will occur as follows: A. The transmitter holding register interrupt (02) occurs when the XMIT FIFO is empty; it is cleared as soon as the transmitter holding register is written to (1 to 16 characters may be written to the XMIT FIFO while servicing this interrupt) or the IIR is read. 9.0 Typical Applications Typical Interface for a High-Capacity Data Bus TL/C/8652 – 23 19 This shows the basic connections of an PC16550D to an 8088 CPU TL/C/8652 – 22 9.0 Typical Applications (Continued) 20 10.0 Physical Dimensions inches (millimeters) Plastic Dual-In-Line Package (N) Order Number PC16550DN NS Package Number N40A 44-Lead Plastic Chip Carrier (V) Order Number PC16550DV NS Package Number V44A 21 PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs 10.0 Physical Dimensions inches (millimeters) (Continued) 44-Lead Package (TQEF) Order Number PC16550DVEF NS Package Number VEF44A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 2900 Semiconductor Drive P.O. Box 58090 Santa Clara, CA 95052-8090 Tel: 1(800) 272-9959 TWX: (910) 339-9240 National Semiconductor GmbH Livry-Gargan-Str. 10 D-82256 F4urstenfeldbruck Germany Tel: (81-41) 35-0 Telex: 527649 Fax: (81-41) 35-1 National Semiconductor Japan Ltd. Sumitomo Chemical Engineering Center Bldg. 7F 1-7-1, Nakase, Mihama-Ku Chiba-City, Ciba Prefecture 261 Tel: (043) 299-2300 Fax: (043) 299-2500 2. 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