N CLC449 1.1GHz Ultra-Wideband Monolithic Op Amp General Description Features The CLC449 is an ultra-high-speed monolithic op amp, with a typical -3dB bandwidth of 1.1GHz at a gain of +2. This wideband op amp supports rise and fall times less than 1ns, settling time of 6ns (to 0.2%) and slew rate of 2500V/µs. The CLC449 achieves 2nd harmonic distortion of -68dBc at 5MHz at a low supply current of only 12mA. These performance advantages have been achieved through improvements in National’s proven current feedback topology combined with a high-speed complementary bipolar process. ■ The DC to 1.2GHz bandwidth of the CLC449 is suitable for many IF and RF applications as a versatile op amp building block for replacement of AC coupled discrete designs. Operational amplifier functions such as active filters, gain blocks, differentiation, addition, subtraction and other signal conditioning functions take full advantage of the CLC449’s unity-gain stable closed-loop performance. The CLC449 performance provides greater headroom for lower frequency applications such as component video, high-resolution workstation graphics, and LCD displays. The amplifier’s 0.1dB gain flatness to beyond 200MHz, plus 0.8ns 2V rise and fall times are ideal for improved time domain performance. In addition, the 0.03%/0.02° differential gain/phase performance allows system flexibility for handling standard NTSC and PAL signals. ■ ■ ■ ■ ■ ■ ■ 1.1GHz small-signal bandwidth (Av = +2) 2500V/µs slew rate 0.03%, 0.02° DG, DΦ 6ns settling time to 0.2% 3rd order intercept, 30dBm @ 70MHz Dual ±5V or single 10V supply High output current: 90mA 2.5dB noise figure Applications ■ ■ ■ ■ ■ ■ ■ High performance RGB video RF/IF amplifier Instrumentation Medical electronics Active filters High-speed A/D driver High-speed D/A buffer CLC449 1.1GHz Ultra-Wideband Monolithic Op Amp June 1999 Frequency Response (Av = +2V/V) In applications using high-speed flash A/D and D/A converters, the CLC449 provides the necessary wide bandwidth (1.1GHz), settling (6ns to 0.2%) and low distortion into 50Ω loads to improve SFDR. Typical Application 120MSPS High-Speed Flash ADC Driver Pinout DIP & SOIC © 1999 National Semiconductor Corporation Printed in the U.S.A. http://www.national.com CLC449 Electrical Characteristics PARAMETERS CONDITIONS TYP CLC449 +25° +25° 1100 500 200 380 380 360 0.5 0.5 0.5 0.05 0.02 0.05 0.05 0.05 0.05 1.1 1.1 1.1 18 2000 18 2000 18 2000 -63 -52 -44 -84 -73 -62 30 16 59 -48 40 77 -66 55 59 -48 40 75 -64 53 59 -48 40 75 -64 53 2.2 15 3 2.9 20.0 5.0 3 25 6 50 2 25 48 47 12 7 9 9 30 45 60 20 25 40 43 44 13.5 41 45 14 41 46 14 200 200 150 0.15 3.1 2.8 2.2 60 0.15 3.1 2.8 2.1 50 0.25 3.1 2.8 1.9 40 FREQUENCY DOMAIN RESPONSE -3dB bandwidth small signal <0.2Vpp large signal <2Vpp ±0.1 dB bandwidth <2Vpp gain flatness peaking DC to 200MHz rolloff DC to 200MHz linear phase deviation <200MHz differential gain 4.43MHz, RL=150Ω differential phase 4.43MHz, RL=150Ω TIME DOMAIN RESPONSE rise and fall time settling time to 0.2% settling time to 0.1% overshoot slew rate 0 0.1 0.8 0.03 0.02 2V step 2V step 2V step 2V step 4V step 0.8 6 11 10 2500 DISTORTION AND NOISE RESPONSE 2nd harmonic distortion 2Vpp, 5MHz 2Vpp, 20MHz 2Vpp, 50MHz 3rd harmonic distortion 2Vpp, 5MHz 2Vpp, 20MHz 2Vpp, 50MHz 3rd order intercept 70MHz 1dB gain compression @ 50MHz equivalent input noise non-inverting voltage 1MHz inverting current 1MHz non-inverting current 1MHz STATIC DC PERFORMANCE input offset voltage average drift input bias current average drift input bias current average drift power supply rejection ratio common-mode rejection ratio supply current Ω, Vcc = ±5V, RL = 100Ω Ω; unless specified) (Av = +2, Rf = 250Ω non-inverting inverting DC DC RL= ∞ MISCELLANEOUS PERFORMANCE input resistance non-inverting input capacitance non-inverting output resistance closed loop output voltage range RL= ∞ RL=100Ω input voltage range common-mode output current 400 1.3 0.1 3.3 2.9 2.4 80 MIN/MAX RATINGS UNITS NOTES 0° to +70° -40° to +85° MHz MHz MHz dB dB deg % deg ns ns ns % V/µs dBc dBc dBc dBc dBc dBc dBm dBm nV/√Hz pA/√Hz pA/√Hz mV µV/°C µA nA/°C µA nA/°C dB dB mA A A A A A kΩ pF Ω V V V mA Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Notes Absolute Maximum Ratings Voc Iout is short circuit protected to ground common-mode input voltage maximum junction temperature operating temperature range AJ storage temperature range lead temperature (soldering 10 sec) ESD (human body model) http://www.national.com ±6V A) J-level: spec is 100% tested at +25°C. ±Vcc +150°C Package Thermal Resistance Package -40°C to +85°C -65°C to +150°C +300°C 500V Plastic (AJP) Surface Mount (AJE) 2 θJC θJA 90°C/W 110°C/W 105°C/W 130°C/W 0.1k Rout (ohms) 0.1M 1k 1M 1M 10k 100k 1M Frequency (Hz) 10M 10M 100M 10M 0.1M Magnitude (0.1dB/div) 100k D.G. (%), D.P. (deg) Distortion (dBc) 10k 1M 10M Time (1ns/div) 3 Phase (1deg/div) -3dB Bandwidth (MHz) Distortion (dBc) 20 log|Z| (dBΩ) Intercept Point (dBm) Distortion (dBc) 180 Magnitude (3dB/div) Magnitude (3dB/div) Magnitude (3dB/div) Phase (deg) 160 Phase (deg) Phase (deg) Noise Voltage (nV/√Hz), Current (pA/√Hz) Phase (deg) PSRR/CMRR (dB) CLC449 Typical Performance Characteristics (TA = 25°C, Vcc = + 5V, Rf = 250Ω, Av = +2, RL = 100Ω) Po = 10dBm 100M 100M PSRR 100M Time (1ns/div) http://www.national.com CLC449 Typical Performance Characteristics (TA = 25°C, Vcc = + 5V, Rf = 250Ω, Av = +2, RL = 100Ω) Input Offset Voltage, VIO (mV) Magnitude (1dB/div) Reverse Isolation (S12) 1.9 2.8 -10 1.8 2.6 -20 1.7 2.4 -30 1.6 2.2 1.5 2.0 1.4 1.3 1.2 -40 |S12| (dB) VSWR VSWR Output VSWR 1.8 1.6 Uncompensated Non-Inverting 1.2 Inverting -50 -60 -70 1.4 1.1 Compensated -80 1.0 1.0 -90 0.9 0.8 -100 0 100M 200M 300M Frequency (Hz) 400M 500M Rs (ohms) Input Bias Current, IBI, IBN (µA) Input VSWR Settling Time (ns) Gain Compression 0 100M 200M 300M Frequency (Hz) 400M 500M 0 100M 200M 300M Frequency (Hz) 400M 500M CLC449 OPERATION The normalized gain plots in the Typical Performance Characteristics section show different feedback resistors, Rf, for different gains. These values of Rf are recommended for obtaining the highest bandwidth with minimal peaking. The resistor Rt in Figure 1 provides DC bias for the non-inverting input. CLC449 Extended Application Information The following design and application topics will supply you with: • A comprehensive set of design parameters and • • • design parameter adjustment techniques. A set of formulas that support design parameter change prediction. A series of common applications that the CLC449 supports. A set of easy to use design guidelines for the CLC449. For Av ≤ 5, calculate the recommended Rf as follows: Rf ≅ 340 - Av • Ri, where Ri = 45Ω. For Av > 5, the minimum recommended feedback resistor is Rf = 100Ω. Select Rg to set the DC gain: R g = Additional design applications are possible with the CLC449. If you have application questions, call 1-800-2729959 in the U.S. to contact a technical staff member. Accuracy of DC gain is usually limited by the tolerance of the external resistors Rf and Rg. DC Gain (Non-Inverting) The non-inverting DC voltage gain for the configuration shown in Figure 1 is: R A V = 1+ f Rg DC Gain (Unity Gain Buffer) Unity gain buffers are easily designed with a currentfeedback amplifier as long as the recommended feedback resistor Rf = 402Ω is used and Rg = ∞, i.e. open. Parasitic capacitance at the inverting node may require a slight increase of the feedback resistor Rf to maintain a flat frequency response. Vcc 3 Rt + 7 CLC449 2 - 4 6 0.1µF Vo + Vin 6.8µF Rf DC Gain (Inverting) The inverting DC voltage gain for the configuration shown in Figure 2 is: Vee Rg + 0.1µF 6.8µF Av = − Figure 1: Non-Inverting Gain http://www.national.com Rf Av − 1 4 Rf Rg Vcc higher than in non-inverting gains. 6.8µF + Rt 3 + 7 0.1µF CLC449 2 Vin Rg - 4 DC Design (Level Shifting) Figure 3 shows a DC level shifting circuit for inverting gain configurations. Vref produces a DC output level shift of 6 Vo Rf Rf Rref which is independent of the DC output produced by Vin. Figure 3: Level Shifting Circuit -Vref ⋅ 0.1µF + 6.8µF Req1 Vee Figure 2: Inverting Gain The normalized gain plots in the Typical Performance Characteristics section show different feedback resistors, Rf, for different gains. These values of Rf are recommended for obtaining the highest bandwidth with minimal peaking. The resistor Rt in Figure 2 provides DC bias for the noninverting input. Vin Req2 Vref Rref + Vo CLC449 Rf DC Design (Single Supply) Figure 4 is a typical single-supply circuit. Resistors R1 and R2 form a voltage divider that sets the non-inverting input DC voltage. This circuit has a DC gain of 1. The coupling capacitor C1 isolates the DC bias point from the previous stage. Both capacitors make a high pass response; the high frequency gain is determined by Rf and Rg. For |Av| ≤ 4, calculate the recommended Rf as follows: Rf ≅ 295 - |Av| • Ri, where Ri = 45Ω. For |Av| > 4, the minimum recommended feedback resistor is Rf = 100 Ω. Select Rg to set the DC gain: Rf Rg = | A At large gains, Rg becomes small and v | will load the previous stage. This situation is resolved by driving Rg with a low impedance buffer like the CLC111, or increasing Rf and Rg (see the Bandwidth (Small Signal) sub-section for the tradeoffs). Vcc Vcc R1 Vin + C1 Accurate DC gain is usually limited by the tolerance of the external resistors Rf and Rg. Vo CLC449 R2 Rf Rg Bandwidth (Small Signal) The CLC449 current-feedback amplifier bandwidth is a function of the feedback resistor (Rf), not of the DC voltage gain (Av). The bandwidth is approximately proportional to 1/Rf. As a rule, if Rf doubles, the bandwidth is cut in half. Other AC specifications will also be degraded. Decreasing Rf from the recommended value increases peaking and for very small values of Rf oscillation will occur. C2 Figure 4: Single Supply Circuit The complete gain equation for the circuit in Figure 4 is: R 1 + sτ 2 ⋅ 1 + f Rg sτ1 Vo = ⋅ Vin 1 + sτ1 1 + sτ 2 With an inverting amplifier design, peaking is sometimes observed. This is often the result of layout parasitics caused by inadequate ground planes or long traces. If this is observed, placing a 50 to 200Ω resistor between the non-inverting pin and ground will usually reduce the peaking. where s = jω, τ1 = (R1|| R2) • C1, and τ2 = RgC2. DC Design (DC Offsets) The DC offset model shown in Figure 5 is used to calculate the output offset voltage. The equation for output offset voltage is: Bandwidth (Minimum Slew Rate) Slew rate influences the bandwidth for large signal sinusoids. To determine an approximate value of slew rate, necessary to support large sinusoids use the following equation: Rf Vo = − Vos + IBN ⋅ Req1 ⋅ 1 + + (IBI ⋅ R f ) Req2 ( ) The current offset terms, IBN and IBI, do not track each other. The specifications are stated in terms of magnitude only. Therefore, the terms Vos, IBN, and IBI may have either positive or negative polarity. Matching the equivalent resistance seen at both input pins does not reduce the output offset voltage. SR ≅ 5 • f • Vpeak Vpeak is the peak output sinusoidal voltage, f is the frequency of the sinusoid. The slew rate of the CLC449 in inverting gains is always 5 http://www.national.com IBN + + Vos - Req1 CLC449 - IBI Matching the output transmission line over greater frequency ranges is accomplished by placing C6 in parallel with R6, reducing the output impedance to compensate for the internal increase of the op-amp’s output impedance with frequency. Vo RL Rf Thermal Design To calculate the power dissipation for the CLC449, follow these steps: Req2 Figure 5: DC Offset Model • Calculate the no-load op amp power: Pamp = Icc • (Vcc – Vee) DC Design (Output Loading) RL, Rf, and Rg load the op amp output. The equivalent closed-loop load impedance seen by the output in Figure 5 is: • Calculate the output stage’s RMS power: Po = (Vcc – Vload) • Iload where Vload and Iload are the RMS voltage and current across the external load. • RL_eq = RL || (Rf + Req2), non-inverting gain • RL_eq = RL || Rf, inverting gain • Calculate the total op amp RMS power: Pt = Pamp + Po RL_eq needs to be kept large enough so that the minimum available output current can produce the required output voltage swing. To calculate the maximum allowable ambient temperature, solve the following equation: Tamb = 175 – Pt • θJA, where θJA is the thermal resistance from junction to ambient in °C/W and Tamb is in °C. Thermal resistance for the various packages are found in the Package Thermal Resistance section. Capacitive Loads Capacitive loads, such as found in A/D converters, require a series resistor (Rs) in the output to improve settling performance. The Rs and Settling Time vs. CL plot in the Typical Performance Characteristics section provides the information for selecting this resistor. Also, use a series resistor to reduce the effects of reactive loads on amplifier loop dynamics. For instance, driving coaxial cables without an output series resistor may cause peaking or oscillation. Dynamic Range (Input /Output Protection) Input ESD diodes are present on all connected pins for protection from static voltage damage. For a signal that may exceed the supply voltages, we recommend using diode clamps at the amplifier’s input to limit the signals to less than the supply voltages. Transmission Line Matching One method for matching the characteristic impedance of a transmission line is to place the appropriate resistor at the input or output of the amplifier. Figure 6 shows the typical circuit configurations for matching transmission lines. Dynamic Range (Input /Output Levels) The Electrical Characteristics section contains the Common-Mode Input Range and Output Voltage Range; these voltage ranges scale with the supplies. Output Current is also specified in the Electrical Characteristics section. R1 Z0 V1 +- R3 R2 R4 Z0 V2 +- Rg Unity gain applications are limited by the Common-Mode Input Range. At greater non-inverting gains, the Output Voltage Range becomes the limiting factor. Inverting gain applications are limited by the Output Voltage Range. C6 + Z0 CLC449 - R6 Vo R7 Rf For transimpedance or inverting gain applications, the current (Iinv) injected at the inverting input pin of the op amp needs to be: V |Iinv | ≤ max Rf R5 Figure 6: Transmission Line Matching In non-inverting gain applications, Rg is connected directly to ground. The resistors R1, R2, R6, and R7 are equal to the characteristic impedance, Zo, of the transmission line or cable. where Vmax is the Output Voltage Range. The voltage ranges discussed above are achieved as long as the equivalent output load is large enough so that the output current can produce the required output voltage swing. See the DC Design (Output Loading) sub-section for details. In inverting gain applications, R3 is connected directly to ground. The resistors R4, R6, and R7 are equal to Zo. The parallel combination of R5 and Rg is also equal to Zo. Dynamic Range (Intermods) For RF applications, the CLC449 specifies a third order intercept of 30dBm at 70MHz and Po = 10dBm. The input and output matching resistors attenuate the signal by a factor of 2, therefore additional gain is needed. http://www.national.com 6 A 2-Tone, 3rd Order IMD Intercept plot is found in the Typical Performance Characteristics section. The output power level is taken at the load. Third-order harmonic distortion is calculated with the formula: The CLC449 noise model in Figure 8 is used to develop the equation below. The equation for Noise Figure (NF) is: ( where: • IP3o = third-order output intercept, dBm at • • • where: the load. Po = output power level, dBm at the load. HD3 rd = third-order distortion from the fundamental, -dBc. dBm is the power in mW, at the load, expressed in dB. • Rs is the source resistance at the noninverting input. • There is no matching resistor from the input to ground. • eni, ibn, ibi are the voltage and current noise density terms (see in the Distortion and Noise Response sub-section of the Electrical Characteristics section). • 4kT = 16 x 10-21J, T = 290°K. • Rf is the feedback resistor and Rg is the gain setting resistor. Realized third-order output distortion is highly dependent upon the external circuit. Some of the common external circuit choices that improve 3rd order distortion are: • short and equal return paths from the load to the supplies. Printed Circuit Board Layout and Measurement High Frequency op amp performance is strongly dependent on proper layout, proper resistive termination and adequate power supply decoupling. The most important layout points to follow are: • de-coupling capacitors of the correct value. • higher load resistance. • a lower ratio of the output swing to the power supply voltage. Noise Figure (dB) Dynamic Range (Noise) In RF applications, noise is frequently specified as Noise Figure (NF). Figure 7 plots NF for the CLC449 at a gain of 10, with a feedback resistor Rf of 100Ω, and with no input matching resistor. The minimum Noise Figure (2.5dB) for these conditions occurs when the source resistance equals 700Ω. • Use a ground plane. • Bypass power supply pins with monolithic • 20 • 15 • 10 • 5 1000 100 capacitors of about 0.1µF value and place the capacitors less than 0.1” (3mm) from the pin. Bypass power supply pins with 6.8µF tantalum capacitors for large signal current swings or improved power supply noise rejection. Minimize trace and lead lengths for components between the inverting and output pins. Remove ground plane underneath the amplifier package and within 0.1” (3mm) of all input/output pads. If parts must be socketed, always use flush-mount socket pins instead of high profile sockets. Evaluation boards are available for proto-typing and measurements. Additional layout information is available in the evaluation board literature. 0 10 ) e + i R 2 + 4kTR + i ⋅ R ||R 2 + 4kT ⋅ R ||R 2 ( bn s ) g s g bi f f NF = 10LOG ni 4kTRs HD3rd = 2 • (IP3o – Po) 10000 Source Resistance (Ω) Figure 7. Noise Figure Plot en Rs Vs + - * * ibn + CLC449 Vo - Rf * ibi Rg Figure 8: CLC449 Noise Model 7 http://www.national.com CLC449 APPLICATIONS achieve high differential bandwidth. For best high frequency performance, maintain low parasitic capacitance from the diodes D1 and D2 to ground, and from the input of the CLC522, to ground. Low Noise Composite Amp With Input Matching The composite circuit shown in Figure 9 eliminates the need for a matching resistor to ground at the input. By connecting two amplifiers in series, the first non-inverting and the second inverting, an overall inverting gain is realized. The feedback resistor (Rf) connected from the output of the second amplifier to the non-inverting input of the first amplifier closes the loop, and generates a set input resistance (Rin) that can be matched to Rs. This resistor generates less noise than a matching resistor to ground at the input. Vin 3 Rin 50Ω + CLC449 6 2 - Vs +- Rf2 + Rs Rg2 CLC449 - - CLC449 Rf1 D1 250Ω D2 Ro 50Ω Vo 6 R2 50Ω Figure 10: Full-Wave Rectifier Flash A/D Application The Typical Application circuit on the front page shows the CLC449 driving a flash A/D. Flash A/D’s require fast settling, low distortion, low noise and wide bandwidth to achieve high Effective Number of Bits and Spurious Free Dynamic Range (SFDR). Input resistance and DC voltage gain of the amplifier are: R R Rf , where G = 1+ f1 ⋅ f2 1+ G R g1 R g2 Rin Vo = − G⋅ Vs Rin + R s This circuit connects a CLC449 to a TDA8716, 8-bit, 120MHz Flash Converter. The input capacitance for this converter is typically 13pF plus layout capacitance. From the Rs and Settling Time vs. CL plot in the Typical Performance Characteristics section, select a series resistor (Rs) of 55Ω. Place Rs in series with the output of the CLC449 to achieve settling to 0.1% in approximately 11ns. Match the source resistance by setting: Rin = R s Noise voltage produced by Rf, referred to the source Vs, is: Rs e 2R = 4kTRs ⋅ f Rin ⋅ (1 + G) The noise of a simple input matching resistor connected to ground can be calculated by setting G to 0 in this equation. Thus, this circuit reduces the thermal noise produced by the matching resistor by a factor of (1+G). Keep the amplifier noise seen at the A/D input at least 3dB lower than the A/D’s noise, to avoid degrading A/D noise performance. Ordering Information Rectifier Circuit Wide bandwidth rectifier circuits have many applications. Figure 10 shows a 200MHz wideband full-wave rectifier circuit using a CLC449 and CLC522 amplifier. Schottky or PIN diodes are used for D1 and D2. They produce an active half-wave rectifier whose signals are taken at the feedback diode connection. The CLC522 takes the difference of the two half-wave rectified signal, producing a full-wave rectifier. The CLC522 is used at a gain of 5 to http://www.national.com 2 + 12 Rg 4 10 CLC522 162Ω 5 9 + Figure 9: Composite Amplifier Rin = R1 50Ω 20Ω 250Ω Vo 20Ω Rg1 Rf 800Ω 3 250Ω Rf Rin Vg 500Ω Model Temperature Range CLC449AJP CLC449AJE CLC449AMC -40°C to +85°C -40°C to +85°C -55°C to +125°C Description 8-pin PDIP 8-pin SOIC dice, MIL-STD-883 Contact factory for other packages and DESC SMD number. Reliability Information Transistor count 8 26 This page intentionally left blank. 9 http://www.national.com This page intentionally left blank. http://www.national.com 10 This page intentionally left blank. 11 http://www.national.com CLC449 1.1GHz Ultra-Wideband Monolithic Op Amp Customer Design Applications Support National Semiconductor is committed to design excellence. For sales, literature and technical support, call the National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018. Life Support Policy National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of National Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. N National Semiconductor Corporation National Semiconductor Europe National Semiconductor Hong Kong Ltd. National Semiconductor Japan Ltd. 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 Fax: (+49) 0-180-530 85 86 E-mail: europe.support.nsc.com Deutsch Tel: (+49) 0-180-530 85 85 English Tel: (+49) 0-180-532 78 32 Francais Tel: (+49) 0-180-532 93 58 Italiano Tel: (+49) 0-180-534 16 80 2501 Miramar Tower 1-23 Kimberley Road Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. http://www.national.com 12