PERICOM PI2EQX5804CNJE

PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™
with Equalization & Emphasis
Features
Description
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Pericom Semiconductor’s PI2EQX5804C is a low power, PCIe®
compliant signal ReDriver™. The device provides programmable
equalization, amplification, and de-emphasis by using 8 select
bits, to optimize performance over a variety of physical mediums
by reducing Inter-symbol interference.
Up to 5.0Gbps PCIe® 2.0 Serial ReDriver™
Supporting 8 differential channels or 4 lanes of PCIe Interface
Pin strapped and I2C configuration controls
Adjustable receiver equalization
Adjustable transmitter amplitude and de-emphasis
Variable input an output termination
1:2 channel broadcast
Channel loop-back
Electrical Idle fully supported
Receiver detect and individual output control
Single supply voltage, 1.2V ± 0.05V
Power down modes
Packaging: 100-contact LBGA, Pb-free & Green
PI2EQX5804C supports eight 100-Ohm Differential CML
data I/O’s between the Protocol ASIC to a switch fabric, across
a backplane, or extends the signals across other distant data
pathways on the user’s platform.
The integrated equalization circuitry provides flexibility with
signal integrity of the PCIe signal before the ReDriver, whereas
the integrated de-emphasis circuitry provides flexibility with
signal integrity of the signal after the ReDriver.
In addition to providing signal re-conditioning, Pericom’s
PI2EQX5804C also provides power management Stand-by mode
operated by a Power Down pin.
Pin Configuration (Top-Side View)
Block Diagram
3
4
5
6
7
8
9
10
B0TX-
B0TX+
VDD
SCL
SDA
VDD
B0RX+
B0RX-
VDD
B A1RX+
GND
GND
A0RX -
DE_A
VDD
A0TX-
GND
GND
A1TX+
C A1RX-
GND
GND
A0RX+
NC
PD#
A0TX+
GND
GND
A1TX -
VDD
D2_A
NC
VDD
D1_A
S0_A
1
+
−
xyRx+
+
xyRx-
−
xyTx+
xyTx-
Output
Controls
Inputleveldetect
tocontrollogic
Equalizer
+
−
Output
Controls
A
+
xyTx+
−
xyTx-
Equalizer
B
Inputleveldetect
tocontrollogic
+
xyRx+
−
xyRx-
+
Sy_x
Dy_x
SDA
SCL
B1TX+ B1TX-
E SEL0_A SEL1_A SEL2_A D0_A
LB#
B1RX- B1RX+ VDD
RXD_A S1_A
SIG_A RX50_A
S1_B
RXD_B S0_B
A1
SEL2_B
LB#
SEL1_B SEL0_B
VDD
A2TX+
A2TX -
VDD
B3RX -
GND
GND
B2RX+
B3RX+
GND
GND B2RX-
RXD_x
RES_x
Power
Management
I2CControl
F RX50_B SIG_B
G
VDD
A2RX-
A2RX+
VDD
H
B2TX+
GND
GND
B3TX-
J B2TX-
GND
GND
B3TX+ RESET# D1_B
MODE D0_B
DE_B
A0
Ax
K
09-0001
VDD
Mode
Controlregisters
&logic
DE_x
PD#
D
VDD
−
DataLaneRepeats4Times
SELy_x
A
2
1
VDD
A3RX+ A3RX-
VDD
D2_B
A4
VDD
A3TX-
PS8926B
A3TX+
VDD
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
Pin #
Data Signals
C4
B4
C7
B7
B1
C1
B10
C10
G3
G2
G8
G9
K2
K3
K9
K8
A8
A9
A3
A2
D9
D8
D2
D3
H10
J10
H1
J1
J7
H7
J4
H4
Pin Name
Type
Description
A0RX+,
A0RXA0TX+,
A0TXA1RX+,
A1RXA1TX+,
A1TXA2RX+,
A2RXA2TX+,
A2TXA3RX+,
A3RXA3TX+,
A3TXB0RX+,
B0RXB0TX+,
B0TXB1RX+,
B1RXB1TX+,
B1TXB2RX+,
B2RXB2TX+,
B2TXB3RX+,
B3RXB3TX+,
B3TX-
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
CML inputs for Channel A0, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel A0, with internal 50-Ohm pull up during normal operation and 2K-Ohm pull up otherwise.
CML inputs for Channel A1, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel A1, with internal 50-Ohm pull up during normal operation and 2K-Ohm pull up otherwise.
CML inputs for Channel A2, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel A2, with internal 50-Ohm pull up during normal operation and 2K-Ohm pull up otherwise.
CML inputs for Channel A3 with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel A3, with internal 50-Ohm pull up during normal operation and 2K-Ohm pull up otherwise.
CML inputs for Channel B0, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel B0, with internal 50-Ohm pull up during normal operation and 2K-Ohm pull up otherwise.
CML inputs for Channel B1, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel B1, with internal 50-Ohm pull up during normal operation and 2K-Ohm pull up otherwise.
CML inputs for Channel B2, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel B2, with internal 50-Ohm pull up during normal operation and 2K-Ohm pull up otherwise.
CML inputs for Channel B3, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel B3, with internal 50-Ohm pull up during normal operation and 2K-Ohm pull up otherwise.
H6, F6, K6
A0, A1, A4
I
I2C programmable address bit A0, A1 and A4.
E4, E5, D5
D[0:2]_A
I
Selection pins for Channel Ax emphasis (See emphasis Configuration Table) w/
100K-Ohm internal pull up
G6, J6, K5
D[0:2]_B
I
B5
DE_A
I
Control Signals
09-0001
Selection pins for Channel Bx emphasis (See emphasis Configuration Table) w/
100K-Ohm internal pull up
De-emphasis enable input for Channel A0, A1, A2 and A3 with internal 100KOhm pull-up resistor. Set high selects output de-emphasis and set low selects
output pre-emphasis.
2
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
Pin #
Pin Name
Type
H5
DE_B
I
F8
LB#
I
G5
MODE
I
C6
PD#
I
D6
C5
NC
NC
J5
RESET#
I
E10
RX50_A
O
F1
RX50_B
O
E7
RXD_A
I
F4
RXD_B
I
E6, E8
S[0:1]_A
I
F5, F3
S[0:1]_B
I
A5
A6
SCL
SDA
I/O
I/O
E1, E2, E3
SEL[0:2]_A
I
09-0001
Description
De-emphasis enable input for Channel B0, B1, B2 and B3 with internal 100KOhm pull-up resistor. Set high selects output de-emphasis and set low selects
output pre-emphasis.
Input with internal 100K-Ohm pull-up resistor. LB# = High or open for normal
operation. LB# = Low for loopback connection of A_RX to A_TX and B_TX.
Input switch between pin control and I2C control with internal 100k-ohm pull-up
resistor. A LVCMOS high level selects input pin control, and disables I2C operation. Note, during startup, input status of the control pin (LB#, RESET#, PD#,
RXD_A/B, SEL0-2_A/B, D0-2_A/B, S0-1_A/B, DE_A/B) will be latched to the
initial state of some I2C control pins only once.
Input with internal 100K-Ohm pull-up resistor, PD# =High or open is normal
operation, PD# =Low disable the IC, and set IC to power down mode, both input
and output go Hi-Z.
No Connect
No Connect
RESET# is an active low channel reset input for Channel A0, B0, A1, B1, A2,
B2, A3 and B3 with internal 100K-Ohm pull-up resistor. When low, the receiver
detection cycle is reset, and normal detection cycle is started after the pin goes
high.
Receiver detect output pin for Channel A0. RX50_A=High
indicates that a 50-Ohm termination was sensed at the A0TX+/- outputs.
Receiver detect output pin for Channel B0. RX50_B=High
indicates that a 50-Ohm termination was sensed at the B0TX+/- outputs.
Receiver detect enable input for Channel A0, A1, A2 and A3 with internal 100KOhm pull-up resistor.
Receiver detect enable input for Channel B0, B1, B2 and B3 with internal 100KOhm pull-up resistor.
Selection pins for Channel Ax output level (see Output Swing Configuration
Table) w/ 100K-Ohm internal pull up
Selection pins for Channel Bx output level (see Output Swing Configuration
Table) w/ 100K-Ohm internal pull up
I2C SCL clock input.
I2C SDA data input.
Selection pins for Channel Ax equalization (see Equalizer Configuration Table)
w/ 100K-Ohm internal pull up
3
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
Pin #
Pin Name
Type
Description
F10, F9, F7
SEL[0:2]_B
I
Selection pins for Channel Bx Equalization (see Equalizer Configuration Table)
w/ 100K-Ohm internal pull up
E9
SIG_A
O
F2
SIG_B
O
Signal detect output pin for Channel A0. SIG_A=High represents a input signal >
threshold at the differential inputs.
Signal detect output pin for Channel B0. SIG_B=High represents a input signal >
threshold at the differential inputs.
Power Pins
B2, B3, B8, B9, C2,
C3, C8, C9, H2,
GND
H3, H8, H9, J2, J3,
J8, J9
PWR
Supply Ground
A1, A4, A7, A10,
B6, D1, D4, D7,
D10, G1, G4, G7,
G10, K1, K4, K7,
K10
PWR
1.2V Supply Voltage
VDD
DESCRIPTION of OPERATION
Configuration Modes
Device configuration can be performed in two ways depending on the state of the MODE input. MODE determines whether IC configuration status is from the input pins or via I2C control. When MODE is set high,
the configuration input pins set the configuration operating state as stored in configuration registers. While
MODE is set high, changes to these control registers are disabled and the initial condition is protected from
any changes to insuring a known operating state. When the MODE pin is low, reprogramming of these control
registers via I2C is allowed. Note that the MODE pin is not latched, and is always active to enable or disable
I2C access.
During initial power-on, the value at the configuration input pins: LB#, RESET#, PD#, RXD_A and RXD_B,
DE_A, DE_B, SEL0_A, SEL1_A, SEL2_A, D0_A, D1_A, D2_A, S0_A, S1_A, SEL0_B, SEL1_B, SEL2_B,
D0_B, D1_B, D2_B, S0_B, S1_B, will be latched to the configuration registers as initial startup states.
09-0001
4
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
Equalizer Configuration
The PI2EQX5804C input equalizer compensates for signal attenuation and Inter-Symbol Interference (ISI) resulting from long signal traces or cables, vias, signal crosstalk and other factors, by boosting the gain of highfrequency signal components. Because either too little, or too much, signal compensation may be non-optimal
eight levels are provided to adjust for any application.
Equalizer configuration is performed in two ways determined by the state of the MODE pin. When the device
first powers up, the SELx_[A:B] input pins are read into the appropriate control registers to set the equalization
characteristic. If the MODE pin is low, reprogramming of these control registers via I2C is allowed.
Each group of four channels, A and B, has separate equalization control, and all four channels within the group
are assigned the same configuration state. The Equalizer Selection table below describes pin strapping options
and associated operation of the equalizer. Refer to the section on I2C programming for information on software configuration of the equalizer.
Equalizer Selection
SEL2_[A:B]
0
0
0
0
1
1
SEL1_[A:B]
0
0
1
1
0
0
SEL0_[A:B]
0
1
0
1
0
1
@1.25GHz
0.5dB
0.6dB
1.0dB
1.9dB
2.8dB
3.6dB
@2.5GHz
1.2dB
1.5dB
2.6dB
4.3dB
5.8dB
7.1dB
1
1
1
1
0
1
5.0dB
7.7dB
9.0dB
12.3dB
Output Configuration
The PI2EQX5804C provides flexible output strength and emphasis controls to provide the optimum signal to
pre-compensate for losses across long trace or noisy environments so that the receiver gets a clean eye opening. Control of output configuration is grouped for the A and B channels, so that each channel within the
group has the same setting.
Output configuration is performed in two ways depending on the state of the MODE pin. When the device
first powers up, the Sx_[A:B], and Dx_[A:B] input pins are read into the appropriate control registers to set the
power-on state. If the MODE pin is low, reprogramming of these control registers via I2C is allowed.
The Output Swing Control table shows available configuration settings for output level control, as specified
using the Sx_y pins and registers.
09-0001
5
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
Output Swing Control
S1_[A:B]
0
0
1
1
S0_[A:B]
0
1
0
1
Swing (Diff. VPP)
1V
0.5V
0.7V
0.9V
Emphasis settings are determined by the state of the DEx_y input pins and configuration registers, as shown in
the Output De-emphasis table below. De-Emphasis is selected as the default power-on mode in following the
PCI Express specification, but can be changed to Pre-emphasis via reprogramming the Loopback and Emphasis Control register using the I2C interface.
Output De-emphasis Adjustment
D2_[A:B]
D1_[A:B]
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
D0_[A:B]
0
1
0
1
0
1
0
1
De-emphasis
0dB
-2.5dB
-3.5dB
-4.5dB
-5.5dB
-6.5dB
-7.5dB
-8.5dB
Input Level Detect
An input level detect and output squelch function is provided on each channel to eliminate re-transmission of
input noise. A continuous signal level below the Vth- threshold causes the output driver to go to a high-impredance state, so that both the positive and negative output signal are pulled to VDD by the internal pull-up resistors. This feature supports the L0s PCI Express Electrical Idle state.
Receiver Detect
Automatic Receiver Detection is a feature that can set the number of active channels. By sensing the presence of a load
device on the output, the channel can be automatically enabled for operation. This allows the PI2EQX5804C to configure itself properly depending on the devices it is communicating with, whether it is a 4-lane, 3-lane, 2-lane or just 1-lane
device or adapter card.
Receiver Detect is enabled by the RXD_A, or RXD_B pins, or alternatively via I2C programming. When RXD_A or
RXD_B is set to low, then the Receiver Detect operation for that group of channel is disabled, and those channels go
directly to 50-Ohm input termination to ground and 50-Ohm output termination to VDD (for a valid differential channel
input level) or to 2K-Ohm (if the signal level is less than the threshold level).
(Continued)
09-0001
6
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
The RESET# input is used to reset the receiver detect state machine to its initial state. The start of the receiver detect
cycle starts when RESET# transitions from low to high.
When a Receiver Detect cycle is begins the differential channel pins are enabled with a 2K-Ohm pullup to VDD. A 50Ohm Receiver termination will change the pin level. This pin level is evaluated after a fixed time-out, and the channel
is then set into the proper operating state. The output signals RX50_A and RX50_B represent the receiver detect result
for their specific channels.
The I/O Operation table summaries the relationships and operation of receiver detect and other signals involved with
I/O control.
Table 4 - I/O Operation Control
Control Inputs
PD# RXD_x RESET#
Detection
States
RX50 SIG_x
0
X
X
X
X
1
0
0
X
X
1
0
1
X
0
1
0
1
X
1
1
1
0
X
X
1
1
1
0
X
1
1
1
1
0
1
1
1
1
1
09-0001
Data Channel I/O
Input Termination Output Termination Mode
Full IC power down, all channels disHi-Z
Hi-Z
abled
Channel disabled, output pulls to VDD.
Hi-Z
2K-Ohm pull-up
Receiver detect reset
50-Ohm pullChannel enabled, no input signal, output
2K-Ohm pull-up
down
pulls to VDD. Receiver detect disabled
Channel enabled, valid input signal
50-Ohm pull50-Ohm pull-up
detected, output driving. Receiver detect
down
disabled.
Hi-Z
2K-Ohm pull-up Channel disabled. Receiver detect reset.
Channel disabled, output pulls to VDD.
Hi-Z
2K-Ohm pull-up Receiver detect enabled, no receiver
detected.
Channel inactive, output pulls to VDD.
50-Ohm pull2K-Ohm pull-up Receiver detect enabled, receiver dedown
tected. No input signal
Channel active, valid input signal de50-Ohm pull50-Ohm pull-up
tected, output driving. Receiver detect
down
enabled, load detected.
7
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
Loopback Operation
Each lane of the PI2EQX5804C provides a loopback mode for test purposes which is controlled by a strapping
pin and I2C register bit. The LB# pin controls all lanes together. When this pin is high normal data mode is enabled. When LB# is low the loopback mode is enabled. The figure below diagrams this operation. Loopback
is not intended to be dynamically switched, and the normal system application is to initialize to one configuration or the other.
The Loopback mode can also support mux/demux operation. Using I2C configuration, unused inputs and outputs can be disabled to minimize power and unnecessary noise.
A0
B0
A0
A0
B0
B0
Normal Operation
LB#=1
A0
B0
B0
Loopback Mode
LB#=0
A0
A0
B0
B0
Mux Function
ODIS_AO = 1
Solid: LB_A0B0#=1
Dashed: LB_A0B0#=0
A0
A0
B0
Demux Function
INDIS_BO = 1
Solid: LB=1
Dashed: LB=0
Loopback Modes
09-0001
8
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
I2C Operation
The integrated I2C interface operates as a slave device, supporting standard rate operation of 100Kbps, with
7-bit addressing mode. The data byte format is 8 bit bytes. The bytes must be accessed in sequential order
from the lowest to the highest byte with the ability to stop after any complete byte has been transferred. Address bits A4, A1 and A0 are programmable to support multiple chips environment. The data is loaded until a
Stop sequence is issued.
Configuration Register Summary
Byte
0
1
2
Mnemonic
SIG
RX50
LBEC
3
4
5
6
7
8
INDIS
OUTDIS
RESET
PWR
RXDE
AEOC
Function
Signal Detect, indicates valid input signal level
Receiver Detect Output, indicates whether a receiver load was detected
Loopback and Emphasis Control, provides for control of the loopback function and emphasis mode (preemphasis or de-emphasis)
Channel Input Disable, controls whether s channels input buffer is enabled or disabled
Channel Output Disable: Controls whether a channels output buffer is enabled or disabled
Channel Reset
Power Down Control, enables power down for each channel individually
Receiver Detect Enable, controls the receiver detect operation
A-Channels Equalizer and Output Control
9
10
11
AEOC
RSVD
RSVD
B-Channels Equalizer and Output Control
Reserved
Reserved
3.3V to 1.2V Bi-directional Level Shifter
If the I2C controller is 3.3V bus, the bi-directional level shifter is used to interconnect two sections of an I2Cbus system, each section with a different supply voltage and different logic levels. In the bus system of Figure
2 the left section has pull-up resistors and devices connected to a 1.2 Volt supply voltage, the right section has
pull-up resistors and devices connected to a 3.3 Volt supply voltage. The devices of each section have I/O’s
with supply voltage related logic input levels and an open drain output configuration.
The level shifter for each bus line is identical and consists of one discrete N-channel enhancement MOS-FET,
T1 for the serial data line SDA and T2 for the serial clock line SCL. The gates (g) has to be connected to the
lowest supply voltage VDD1 (1.2V), the sources (s) to the bus lines of the “Lower voltage” section, and the
drains (d) to the bus lines of the “Higher voltage” section. The diode between the drain (d) and substrate is
inside the MOS-FET present as n-p junction of drain and substrate.
09-0001
9
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
THE MOS-FET’S.
The requirements for the most important characteristics of the MOS-FET’s, used as bi-directional level shifter.
Type : N-channel enhancement mode MOS-FET.
Gate threshold voltage : VGS(th) min. 0.8V max. 1.5V
On resistance : RDS(on) max. 30 Ohm @ ID= 3mA, VGS= 2.5V
Input capacitance : Ciss max. 50 pF @ VDS= 1V, VGS = 0V
Switching times : ton toff max. 50 ns.
Allowed drain current : ID 30 mA or higher.
27k
10k
VDD2= 3.3 V
Vbias = 2.4V
100nf
VDD1= 1.2V
4.7k
4.7k
g
VDD2= 3.3 V
T1
s
10k
2SK3018
d
g
10k
SDA2
T2
s
d
SCL2
2SK3018
to I2C controller
PI2EQX5804C
PI2EQX5804C
“Lower voltage” section
“Higher voltage” section
Figure 2. Bi-directional Level Shifter Circuit
MOS-FET’s in table 1 are suitable to be used as level shifter. The 2SK3018 are low cost devices and have
good properties for 1.2V/3.3V level shifting, isolation and protection.
Manufacturer ManufacPart Number turer
Drain to
Current - Con- Input Capac- Gate
Source Volt- tinuous Drain itance (Ciss) threshold
age (Vds)
(Id) @ 25° C
@ Vds
voltage
2SK3018T106
30V
09-0001
Rohm
100mA
10
13pF @ 5V
0.8~1.5V
@100μA
Package /
Case
SOT-23
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
Transferring Data
Every byte put on the SDA line must be 8-bits long. Each byte has to be followed by an acknowledge
bit. Data is transferred with the most significant bit (MSB) first (see the I2C Data Transfer diagram). The
PI2EQX5804C will never hold the clock line SCL LOW to force the master into a wait state.
Note: Byte-write and byte-read transfers have a fixed offset of 0x00, because of the very small number of configuration bytes. An offset byte presented by a host to the PI2EQX5804C is not used.
Addressing
Up to eight PI2EQX5804C devices can be connected to a single I2C bus. The PI2EQX5804C supports 7-bit
addressing, with the LSB indicating either a read or write operation. The address for a specific device is determined by the A0, A1 and A4 input pins.
Address Assignment
A6
1
A5
1
A4
Program
A3
0
A2
0
A1
A0
Programmable
R/W
1=R, 0=W
Acknowledge
Data transfer with acknowledge is required from the master. When the master releases the SDA line (HIGH)
during the acknowledge clock pulse, the PI2EQX5804C will pull down the SDA line during the acknowledge
clock pulse so that it remains stable LOW during the HIGH period of this clock pulse as indicated in the I2C
Data Transfer diagram. The PI2EQX5804C will generate an acknowledge after each byte has been received.
Data Transfer
A data transfer cycle begins with the master issuing a start bit. After recognizing a start bit, the PI2EQX5804C
will watch the next byte of information for a match with its address setting. When a match is found it will
respond with a read or write of data on the following clocks. Each byte must be followed by an acknowledge
bit, except for the last byte of a read cycle which ends with a stop bit. For a write cycle, the first data byte following the address byte is a dummy or fill byte that is not used by the PI2EQX5804C. This byte is provided
to provided compatibility with systems implementing 10-bit addressing. Data is transferred with the most
significant bit (MSB) first. After each block write, address pointer will reset to byte 0.
09-0001
11
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
Register Description
Byte 0 - Signal Detect (SIG)
SIG_xy=0=low input signal, SIG_xy=1=valid input signal
Bit
Name
7
SIG_A0
6
SIG_B0
5
SIG_A1
4
SIG_B1
3
SIG_A2
2
SIG_B2
1
SIG_A3
0
SIG_B3
Type
Power-on
State
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Signal Detect register provides information on the instantaneous status of the channel input from the Input Level
Threshold Detect circuit. If the input level falls below the Vth- level the relevant SIG_xy bit will be 0, indicating a lowlevel noise or electrical idle input, resulting in the outputs going to the high-impedance off state or squelch mode. If the
input level is above Vth-, then SIG_xy is 1, indicating a valid input signal, and active signal recovery operation.
Byte 1 - Receiver Detect Output Register (RX50)
LB_xyxy#=0=loopback mode, LB_xyxy#=1=normal mode, DE_x=0=pre-emphasis, DE_x=1=de-emphasis
Bit
7
6
5
4
3
2
1
0
Name
RX50_A0
RX50_B0
RX50_A1
RX50_B1
RX50_A2
RX50_B2
RX50_A3
RX50_B3
Type
Power-on
State
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The RX50_xy bits report the result of a receiver detection cycle. One bit is assigned for each channel of the device.
RX50_xy is at a logic 1 level indicating a load and receiver was detected. When RX50_xy is 0 then a load device was
not detected. The RX50 register is read-only, and is undefined after power-up until a Receiver Detection cycle completes.
Byte 2 - Loopback and Emphasis Control Register (LBEC)
LB_xyxy#=0=loopback mode, LB_xyxy#=1=normal mode, DE_x=0=pre-emphasis, DE_x=1=de-emphasis
Bit
7
6
5
4
3
2
1
0
Name
LB_A0B0#
LB_A1B1#
LB_A2B2#
LB_A3B3#
DE_A
DE_B
rsvd
rsvd
Type
Power-on
State
R/W
LB#
R/W
LB#
R/W
LB#
R/W
LB#
R/W
DE_A
R/W
DE_B
R
X
R
X
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
Individual control for each lane is provided for the loopback function via this register.
09-0001
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PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
BYTE 3 - Channel Input Disable (INDIS)
INDIS_xy=0=enable input, INDIS_xy=1=disable input
Bit
7
6
5
4
3
2
1
0
Name
INDIS_A0
INDIS_B0
INDIS_A1
INDIS_B1
INDIS_A2
INDIS_B2
INDIS_A3
INDIS_B3
Type
Power-on
State
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Channel Input Disable register, provides control over the input buffer of each channel independently.
When and INDIS_xy bit is logic 1, then the input buffer is switched off and the input termination is high impedance. This feature can be used for PCB testing, and when only one input is used during Loopback as a demux function. When INDIS_xy is at a logic 0 state then the input buffer is enabled (normal operating mode).
BYTE 4 - Channel Output Disable (OUTDIS)
ODIS_xy=0=enable output, ODIS_xy=1=disable output
Bit
7
6
5
4
3
2
1
0
Name
ODIS_A0
ODIS_B0
ODIS_A1
ODIS_B1
ODIS_A2
ODIS_B2
ODIS_A3
ODIS_B3
Type
Power-on
State
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Channel Output Disable register, allows control over the output buffer of each channel independently.
When and OUTDIS_xy bit is logic 1, then the output buffer is switched off and the termination is high impedance. This feature can be used for PCB testing, and when only one output is used during Loopback as a mux
function. When INDIS_xy is at a logic 0 state then the input buffer is enabled (normal operating mode).
BYTE 5 - Channel Reset (RESET)
RES_xy# =0=reset, RES_xy# =1=normal operation. Latch from RESET# input at startup
Bit
7
6
5
4
3
2
1
0
Name
RES_A0#
RES_B0#
RES_A1#
RES_B1#
RES_A2#
RES_B2#
RES_A3#
RES_B3#
Type
Power-on
State
R/W
RESET#
R/W
RESET#
R/W
RESET#
R/W
RESET#
R/W
RESET#
R/W
RESET#
R/W
RESET#
R/W
RESET#
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Channel Reset register allows for restart of an individual channels Receiver Detect function. A transition
from 0 to 1 initiates a new Receiver Detect cycle (if the channel is enabled and receiver detect is enabled).
While static at 0 or 1, the RES_zy# bit will have no effect on operation. The Channel Reset bits are read/write
allowing the current state to be checked.
09-0001
13
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
BYTE 6 - Power Down Control (PWR)
PD_xy# =0=channel off/power down, PD_xy# =1=normal operation, Latch from PD# input at startup
Bit
7
6
5
4
3
2
1
0
Name
PD_A0#
PD_B0#
PD_A1#
PD_B1#
PD_A2#
PD_B2#
PD_A3#
PD_B3#
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
State
PD#
PD#
PD#
PD#
PD#
PD#
PD#
PD#
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Power Down Control register allows for individual control over each channel for power savings. When
PD_xy# is logic 0 the channel is turned off. When PD_xy# is 1 then the channel is enabled for normal
operation.
BYTE 7 - Receiver Detect Enable (RXD)
RXD_xy =0=channel off/power down, RXD_xy =1=normal operation, Latch from PD# input at startup
Bit
7
6
5
4
3
2
1
0
Name
RXD_A0
RXD_B0
RXD_A1
RXD_B1
RXD_A2
RXD_B2
RXD_A3
RXD_B3
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
State
RXD_A
RXD_B
RXD_A
RXD_B
RXD_A
RXD_B
RXD_A
RXD_B
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Receiver Detect Enable register allows for control of the receiver detect state machine for each individual
channel. When RXD_xy is set to 0, then the receiver detect function is disabled. When RXD_xy is logic 1,
then the receiver detect state machine is enabled for operation. The initial state of the register bits are determined by the RXD_A and RXD_B input pins during power-up.
BYTE 8 - A-Channels Equalizer and Output Control (AEOC)
SELx_A: Equalizer configuration, Dx_A: Emphasis control, Sx_A: Output level control (see Configuration Table)
Bit
7
6
5
4
3
2
1
0
Name
SEL0_A
SEL1_A
SEL2_A
D0_A
D1_A
D2_A
S0_A
S1_A
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
State
SEL0_A
SEL1_A
SEL2_A
D0_A
D1_A
D2_A
S0_A
S1_A
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The A-Channels Equalizer and Output Control register is used to control the configuration of the input equalizer and output emphasis and levels of the four A channels. These register bits are loaded from the input configuration pins of the same name at power-on. These bits may be changed if the MODE# input is set to allow
I2C configuration. Please refer to the tables (1) Equalizer Configuration, (2) Output Swing Configuration and
09-0001
14
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
(3) Output Emphasis Configuration earlier in this document for setting information. All four A channels get
the same configuration settings.
BYTE 9 - B-Channels Equalizer and Output Control (BEOC)
SELx_B: Equalizer configuration,
Dx_B: Emphasis control,
Sx_B: Output level control (see Configuration Table)
Bit
7
6
5
4
3
2
1
0
Name
SEL0_B
SEL1_B
SEL2_B
D0_B
D1_B
D2_B
S0_B
S1_B
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
State
SEL0_B
SEL1_B
SEL2_B
D0_B
D1_B
D2_B
S0_B
S1_B
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The B-Channels Equalizer and Output Control register is used to control the configuration of the input equalizer and output emphasis and levels of the four B channels. These register bits are loaded from the input configuration pins of the same name at power-on. These bits may be changed if the MODE# input is set to allow
I2C configuration. Please refer to the tables (1) Equalizer Configuration, (2) Output Swing Configuration and
(3) Output Emphasis Configuration earlier in this document for setting information. All four B channels get
the same configuration settings.
BYTE 10 - Reserved
BYTE 11 - Reserved
Reserved Bytes 10 and 11 are also visible via the I2C interface. These bytes are R/W, are initialized to 0 at
power up, are used for IC manufacturing test purposes and should not be changed for normal operation.
Start & Stop Conditions
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. A LOW to
HIGH transition on the SDA line while SCL is HIGH defines a STOP condition, as shown in the figure below.
I2C
09-0001
15
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
I2C Data Transfer
1.Readsequence
ACK
PI2EQX5804C
DATAOUT ACK
ACK
ACK
ACK
DATAOUTN
NOACK
PI2EQX5804C
DEVSEL
stop
start
I2C Master
R/W
2.Writesequence
ACK
ACK
ACK
PI2EQX5804C
DEVSEL
R/W
DATAINN
DATAIN1
DUMMY BYTE
stop
start
I2C Master
3.Combinedsequence
ACK DUMMYBYTE ACK
ACK DATAOUT1 ACK
ACK DATAOUTN NO
PI2EQX5804C
DEVSEL R/W
start
start
I2C Master
DEVSEL R/W
Notes:
1. only block read and block write from the lowest byte
are supported for this application.
2. for some I2C application, an offset address byte will be
presented at the second byte in write command, which
is called dummy byte here and will be simply ignored in
this application for correct interoperation.
09-0001
16
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Storage Temperature...................................... –65°C to +150°C
Supply Voltage to Ground Potential........ –0.5V to +2.5V
DC SIG Voltage....................................... –0.5V to VDD +0.5V
Current Output ........................................ –25mA to +25mA
Power Dissipation Continuous ............... 1W
Operating Temperature............................ 0 to +70°C
ESD, HBM: I2C pins............................... –1kV to +1kV
ESD, HBM: All other pins....................... –2kV to +2kV
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and function al
operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
AC/DC Electrical Characteristics
Power Supply Characteristics (VDD = 1.2 ±0.05V, TA = 0 TO 70°C)
Symbol
IDDactive
Parameter
Power supply current - active
Conditions
All channels switching
IDDstandby
IDD-channel
Power supply current - standby
Power supply current - per channel, Active
PD# = 0
Min.
Typ.
Max.
800
Units
mA
5
50
10
mA
mA
Typ.
750
Max.
Units
ps
Min.
Typ.
Max.
Units
AC Performance Characteristics (VDD = 1.2 ±0.05V, TA = 0 TO 70°C)
Symbol
Tpd
Parameter
Channel latency from input to output
Conditions
Min.
CML Receiver Input (VDD = 1.2 ±0.05V, TA = 0 TO 70°C)
Symbol
Parameter
ZRX-DIFF-DC
DC Differential Input Impedance
80
100
120
Ohms
ZRX-DC
DC Input Impedance
40
50
60
Ohms
VRX-DIFFP-P
Differential Input Peak-to-peak Voltage
1.200
V
VRX-CM-ACP
AC Peak Common Mode Input Voltage
150
mV
Vth-
Signal detect threshold voltage
150
mV
09-0001
Conditions
0.120
100
17
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
Equalizer
Symbol
JRS-T
Parameter
Residual jitter
Conditions
Total
JRS-D
JRM
Residual jitter
Random jitter
Deterministic
Note 2
Min.
Typ.
Max.
0.3
Units
Ulp-p
0.2
Ulp-p
psrms
1.5
Notes
1. K28.7 pattern is applied differentially at point A as shown in AC test circuit (see figure).
2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 × RJ + DJ) where RJ is random RMS jitter and DJ is maximum
deterministic jitter. Signal source is a K28.5 ± pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or
equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or its
equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. Jitter is measured at 0V
at point C of the AC test circuit (see figure).
CML Transmitter Output (VDD = 1.2V ± 0.05V, TA = 0 to 70°C)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
ZOUT
Output resistance
Single ended
40
50
60
Ohms
ZTX-DIFF-DC
DC Differential TX Impedance
80
100
120
Ohms
VDIFFP
Output Voltage Swing, Differential
|VTX-D+ - VTX-D-|
200
800
mVp-p
VTX-DIFFP-P
Differential Peak-to-peak
Ouput Voltage
VTX-DIFFP-P = 2 * | VTX-D+ VTX-D- |
0.4
1.6
V
VTX-C
Common-Mode Voltage
| VTX-D+ + VTX-D- | / 2
tF, tR
Transition Time
20% to 80% (3)
(1)
VDD- 0.3
AC Coupling Capacitor
CTX
75
V
150
ps
200
nF
Note:
1. Recommended external blocking capacitor.
Digital I/O DC Specifications (VDD = 1.2V ± 0.05V, TA = 0 to 70°C)
Symbol
Parameter
Conditions
VIH
DC input logic high
VIL
DC input logic low
VOH
DC output logic high
IOH = 4mA
VOL
DC output logic low
IOL = 4mA
Vhys
Hysteresis of Schmitt trigger input
IIH(1)
Input high current
Min.
Typ.
Max.
Units
VDD/2 +0.2
VDD+0.3
V
-0.3
VDD/2 -0.2
V
VDD-0.4
V
0.4
V
0.2
V
100
μA
(2)
Input low current
-20
μA
(3)
Input low current
-20
μA
IIL1
IIL2
Notes:
1. Includes input signals A1, A2, A4, Dx_[A:B], DE_[A:B], LB#, MODE#, PD#, RESET#, RXD_[A:B], Sx_[A:B], SCL, SDA, SEL_x[A:B]
2. For control inputs without pullups: A1, A2, A4, SCL, SDA
3. Control inputs with pull-ups include: Dx_[A:B], DE_[A:B], LB#, MODE#, PD#, RESET#, RXD_[A:B], Sx_[A:B], SEL_x[A:B]
09-0001
18
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
SDA and SCL I/O for I2C-bus (VDD = 1.2 ± 0.05v, TA = 0 to 70°C)
Symbol
VIH
VIL
Parameter
DC input logic high
DC input logic low
Conditions
VOL
Vhys
DC output logic low
Hysteresis of Schmitt trigger input
IOL = 3mA
Min.
1.1
-0.3
Typ.
Max.
VDD+0.3
0.7
Units
V
V
0.4
V
V
Max.
100
–
Unit
kHz
μs
4.7
–
μs
4.0
4.7
5.0
250
–
4.0
4.7
–
–
–
–
100
300
–
–
μs
μs
μs
ns
ns
ns
μs
μs
–
400
pF
0.2
Characteristics of the SDA and SCL bus lines for F/S-mode I2C-bus devices(1)
Symbol
fSCL
tHD;STA
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
tf
tSU;STO
tBUF
Cb
Parameter
SCL clock frequency
Hold time (repeated) START condition. After
this period, the first clock pulse is generated
LOW period of the SCL clock
Conditions
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Buss free time between a STOP and STOP
condition
Capacitive load for each bus line
Min.
0
4.0
Typ.
Notes:
1. All values referred to VIHmin and VILmax levels.
2. A device must initially provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.
09-0001
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PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
STOP
START
START
SDA
tf
tf
tSU;DAT
tLOW
tr
t HD;STA
tBUF
SCL
S
tHD;STA
tHD;DAT
HIGH
t SU;STA
Sr
t SU;STO
P
S
I2C Timing
Channel Latency, 5.0 Gbps
09-0001
20
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
Output Level Settings (1V left, and 0.5V right at 5.0 Gbps)
–3.5 dB (Dx = 010)
0.0 dB (Dx = 000)
–8.5 dB (Dx = 111)
–6.5 dB (Dx = 101)
Output De-emphasis Characteristics
09-0001
21
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
Eye Diagrams 5.0Gbps (input left, output right)
Data Waveforms, 2.5Gbps (left) & 5.0Gbps (right)
FR4
Signal
Source
A
B
C
D.U.T.
SmA
Connector
SmA
Connector
In
Out
≤30IN
AC Test Circuit Referenced in the Electrical Characteristic Table
09-0001
22
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
Packaging Mechanical: 100-Ball LBGA (NJ)
1
DATE: 04/28/08
DESCRIPTION: 100-Ball Low Profile Ball Grid Array (LBGA)
PACKAGE CODE:
NJ100
REVISION: B
DOCUMENT CONTROL #: PD-2055
08-0178
Ordering Information
Ordering Number
PI2EQX5804CNJE
Package Code
NJ
Package Description
Pb-free & Green 100-Contact LBGA
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free and Green
• X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
09-0001
ReDriver is a trademark of Pericom Semiconductor.
PCIe® , and the PCI EXPRESS design mark® are trademarks of PCI-SIG® (www.pcisig.com)
23
PS8926B
06/08/09