SN74SSQEA32882 www.ti.com...................................................................................................................................................................................................... SCAS879 – JUNE 2009 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS PARITY TEST ONE PAIR TO FOUR PAIR DIFFERENTIAL CLOCK PLL DRIVER FEATURES 1 • • • • • • • • JEDEC SSTE32882 Compliant 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 DIMMs CKE Powerdown mode for optimized system power consumption 1.5V/1.35V Phase Lock Loop Clock Driver Buffers One Differential Clock Pair (CK and CK) and Distributes to Four Differential Outputs 1.5V/1.35V CMOS Inputs Checks Parity on Command and Address (CS-gated) Data Inputs Supports Four Chip Selects Configurable Driver Strength APPLICATIONS • • • DDR3 Registered DIMMs up to DDR3-1600 DDR3L Registered DIMMs up to DDR3L-1333 Single-, Dual- and Quad-Rank RDIMM DESCRIPTION/ORDERING INFORMATION This JEDEC SSTE32882-compliant, 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3 registered DIMMs with with VDD of 1.5 V and on DDR3L registered DIMMs with VDD of 1.35 V. The SN74SSQEA32882 implements different power-saving mechanisms to reduce thermal power dissipation and to support system power-down states. Power consumption is further reduced by disabling unused outputs. All inputs are 1.5V and 1.35V CMOS-compatible. All outputs are optimized to drive DRAM signals on terminated traces in DDR3 RDIMM applications. Clock outputs Yn and Yn and control net outputs DxCKEn, DxCSn, and DxODTn can each be driven with a different strength and skew to optimize signal integrity, compensate for different loading, and balance signal travel speed. The SN74SSQEA32882 has two basic modes of operation associated with the Quad Chip Select Enable (QCSEN) input. First, when the QCSEN input pin is open or pulled high, the component has two chip select inputs, DCS0 and DCS1, and two copies of each chip select output, QACS0, QACS1, QBCS0 and QBCS1. This mode is the QuadCS disabled mode. Alternatively, when the QCSEN input pin is pulled low, the component has four chip select inputs DCS[3:0], and four chip select outputs, QCS[3:0]. This mode is the QuadCS enabled mode. When QCSEN is high or floating, the device also supports an operating mode that allows a single device to be mounted on the back side of a DIMM array. This device can then be configured to keep the input bus termination (IBT) feature enabled for all input signals independent of MIRROR. The SN74SSQEA32882. operates from a differential clock (CK and CK). Data are registered at the crossing of CK going high and CK going low. This data can either be re-driven to the outputs or used to access internal control registers. Details are covered in the Function Tables (each flip-flop) with QCSEN = low. Input bus data integrity is protected by a parity function. All address and command input signals are summed; the last bit of the sum is then compared to the parity signal delivered by the system at the PAR_IN input one clock cycle later. If these two values do not match, the device pulls the open drain output ERROUT low. The control signals (DCKE0, DCKE1, DODT0, DODT1, and DCS[n:0]) are not part of this computation. The package design is optimal for high-density DIMMs. By aligning input and output positions towards DIMM finger-signal ordering and SDRAM ballout, the device de-scrambles the DIMM traces and allows low crosstalk designs with low interconnect latency. Edge-controlled outputs reduce ringing and improve signal eye opening at the SDRAM inputs. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated SN74SSQEA32882 SCAS879 – JUNE 2009...................................................................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) 0°C - Tcase (see Table 1) (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING SN74SSQEA32882ZALR EA32882B PACKAGE (2) TCASE 176ZAL Tape and Reel For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range (unless otherwise noted). (1) PARAMETER VDD Supply voltage VI Receiver input voltage VREF Reference voltage VO Driver output voltage See IIK Input clamp current IOK IO ICCC Continuous current through each VDD or GND pin Tstg Storage temperature (1) (2) (3) See (2) (2) and and (3) (3) VALUE UNIT –0.4 to +1.975 V –0.4 to VDD + 0.5 V –0.4 to VDD + 0.5 V –0.4 to VDD + 0.5 V VI < 0 or VI > VDD –50 mA Output clamp current VO < 0 or VO > VDD ±50 mA Continuous output current 0 < VO < VDD ±50 mA ±100 mA –65 to +150 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 2.2 V maximum. Table 1. Case Temperature vs Speed Node PARAMETER Tcase (1) 2 Maximum case temperature (1) DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 UNIT +109 +108 +106 +103 °C The temperature values fit to JEDEC RAW cards A, B, and C. The user must keep Tcase below the specified values in order to keep the junction temperature below +125°C. Other combinations of features and termination resistors can require lower case temperature and extra cooling. These combinations depend on the specific application. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated SN74SSQEA32882 www.ti.com...................................................................................................................................................................................................... SCAS879 – JUNE 2009 PACKAGE INFORMATION ZAL Package The package is an 8-mm × 13.5-mm, 176-pin ball grid array (BGA) with 0.65-mm ball pitch in an 11 × 20 grid. The device pinout supports outputs on the outer two left and right columns to support easy DIMM signal routing. Corresponding inputs are placed in such a way that two devices can be placed back-to-back for four rank modules while the data inputs share the same vias. Each input and output is located close to an associated no-ball position or on the outer two rows to allow for low-cost via technology combined with the small, 0.65-mm ball pitch. 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R T U V W Y NOTE: To request more information on SN74SSQEA32882 DDR3 Register/PLL please contact [email protected] . Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 3 PACKAGE OPTION ADDENDUM www.ti.com 30-Jul-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing SN74SSQEA32882ZALR ACTIVE BGA ZAL Pins Package Eco Plan (2) Qty 176 1000 Green (RoHS & no Sb/Br) Lead/Ball Finish SNAGCU MSL Peak Temp (3) Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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