R7731A Burst Triple Mode PWM Flyback Controller General Description Features The R7731A is a high-performance, low cost, low start-up current and current mode PWM controller with burst triple mode to support green mode power saving operation. The R7731A integrates functions of soft start, Under Voltage LockOut (UVLO), Leading Edge Blanking (LEB), Over Temperature Protection (OTP) and internal slope compensation. It provides the users a superior AC/DC power application of higher efficiency, low external component counts and lower cost solution. z To protect the external power MOSFET from being damaged by supply over voltage, the R7731A output driver is clamped at 12V. Furthermore, R7731A features fruitful protections like Over Load Protection (OLP) and Over Voltage Protection (OVP) to eliminate the external protection circuits and provide reliable operation. R7731A is available in SOT-23-6 and DIP-8 packages. z z z z z z z z z z z z z z z z Ordering Information z μA) Very Low Start-up Current (<30μ 10/14V UVLO Soft Start Function Current Mode Control Jittering Switching Frequency Internal Leading Edge Blanking Built-in Slope Compensation Burst Triple Mode PWM for Green-Mode Cycle-by-Cycle Current Limit Feedback Open Protection Over Voltage Protection Over Temperature Protection Over Load Protection Soft Driving for Reducing EMI Driver Capability ±200mA High Noise Immunity Opto-Coupler Short Protection RoHS Compliant and Halogen Free R7731A Package Type E : SOT-23-6 N : DIP-8 Lead Plating System G : Green (Halogen Free and Pb Free) Applications z z z Note : z Richtek products are : z ` RoHS compliant and compatible with the current require- z Adaptor and Battery Charger ATX Standby Power Set-Top Box (STB) DVD and CD(R) TV/Monitor Standby Power PC Peripherals ments of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. Marking Information R7731AGE IDP=W IDP= : Product Code W : Date Code R7731AGE RichTek R7731A GNYMDNN R7731A-10 August 2011 R7731AGN : Product Number YMDNN : Date Code www.richtek.com 1 R7731A Pin Configurations (TOP VIEW) GND COMP NC 8 GATE VDD CS 6 5 4 2 3 GND COMP RT 7 6 5 2 3 4 NC CS GATE VDD SOT-23-6 RT DIP-8 Typical Application Circuit VO+ AC Mains (90V to 265V) VO- RT VDD * R7731A COMP GATE GND CS * : See Application Information Functional Pin Description Pin No. Pin Name Pin Function SOT-23-6 DIP8 1 8 GND Ground. 2 7 COMP Comparator Input. By connecting an opto-coupler to this pin, the peak current set point is adjusted accordingly to the output power requirement. 3 5 RT Set the switching frequency by connecting a resistor to GND. 4 4 CS Primary Current Sense. 5 2 VDD IC Power Supply. 6 1 GATE Gate Driver Output to drive the external MOSFET. -- 3, 6 NC No Internal Connection. www.richtek.com 2 R7731A-10 August 2011 R7731A Function Block Diagram OVP - OTP Shutdown Logic + UVLO Counter OLP - 14V/10V Bias & Bandgap Jittering Oscillator SS Constant Power RT Dmax Soft Driver S COMP Slope Ramp CS + PWM comparator X3 GATE Q R COMP Burst Triple Mode LEB 27V POR Brown out sensing COMP open sensing VDD + VBURL VBURH VDD GND R7731A-10 August 2011 www.richtek.com 3 R7731A Absolute Maximum Ratings z z z z z z z z z z (Note 1) Supply Input Voltage, VDD ------------------------------------------------------------------------------------------------- −0.3V to 30V GATE Pin ---------------------------------------------------------------------------------------------------------------------- −0.3V to 20V RT, COMP, CS Pin ---------------------------------------------------------------------------------------------------------- −0.3V to 6.5V IDD ------------------------------------------------------------------------------------------------------------------------------- 10mA Power Dissipation, PD @ TA = 25°C SOT-23-6 ---------------------------------------------------------------------------------------------------------------------- 0.4W DIP-8 --------------------------------------------------------------------------------------------------------------------------- 0.714W Package Thermal Resistance (Note 2) SOT-23-6, θJA ----------------------------------------------------------------------------------------------------------------- 250°C/W DIP-8, θJA ---------------------------------------------------------------------------------------------------------------------- 140°C/W Junction Temperature ------------------------------------------------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------------- 260°C Storage Temperature Range ---------------------------------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility (Note 3) HBM (Human Body Mode) ------------------------------------------------------------------------------------------------ 4kV MM (Machine Mode) -------------------------------------------------------------------------------------------------------- 250V Recommended Operating Conditions z z z z (Note 4) Supply Input Voltage, VDD ------------------------------------------------------------------------------------------------- 12V to 25V Operating Frequency ------------------------------------------------------------------------------------------------------- 50k to 130kHz Junction Temperature Range ---------------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ---------------------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VDD = 15V, VDD bypass capacitor=0.1μF, RT = 100kΩ, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit 25.5 27 28.5 V VDD Section VDD Over Voltage Protection Level VOVP On Threshold Voltage VTH_ON 13 14 15 V VDD On/Off Hysteresis VDD_HYS 3 4 5 V Start-up Current IDD_ST VDD = VTH_ON – 0.1V -- 20 30 μA Operating Current IDD_OP VDD = 15V, RT = 100kΩ, GATE = Open, VCOMP = 2.5V -- 1.1 2.2 mA VDD Holdup Mode Hysteresis Ending Level VDD_HYS VCOMP < 1.6V -- 11.5 -- V VDD Holdup Mode Entry Level VDD_LOW VCOMP < 1.6V -- 11 -- V VDD Clamp Voltage VDD_CLAMP -- 29 -- V 60 65 70 kHz Oscillator Section (RT pin) Normal PWM Frequency fOSC RT = 100kΩ To be continued www.richtek.com 4 R7731A-10 August 2011 R7731A Parameter Symbol Test Conditions Frequency Jittering Range Typ Max Unit -- ±6 -- % -- 4 -- ms 70 75 80 % PWM Frequency Jitter Period TJIT Maximum Duty Cycle DMAX Frequency Variation Versus VDD Deviation f DV VDD = 12V to 25V -- -- 2 % f DT TA = −30°C to 105°C (Note 5) -- -- 5 % 5.2 5.6 6 V Frequency Variation Versus Temperature Deviation For 65 kHz Min COMP Input Section Open Loop Voltage VCOMP_OP COMP pin open COMP Open-loop Protection Delay TOLP Cycles RT = 100kΩ -- 60 -- ms Short Circuit Current VCOMP = 0V -- 1.2 2.2 mA 0.8 0.85 0.9 V I ZERO Current-Sense Section Initial Peak Current Limit Offset VCSTH Leading Edge Blanking Time TLEB -- 420 520 ns Propagation Delay Time TPD -- 100 -- ns GATE Section Rising Time TR VDD = 15V, CL = 1nF -- 250 350 ns Falling Time TF VDD = 15V, CL = 1nF -- 150 250 ns Gate Output Clamping Voltage VCLAMP VDD = 22V -- 12 -- V Over Temperature Protection TOTP 140 -- -- °C OTP Hysteresis TOTP_HYS -- 30 -- °C Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at TA = 25°C on a low effective single layer thermal conductivity test board of JEDEC 51-3 thermal measurement standard. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guaranteed by design. R7731A-10 August 2011 www.richtek.com 5 R7731A Typical Operating Characteristics IDD_ST vs. Temperature VTH vs. Temperature 15 28 VDD = 13V 26 14 V TH_ON 24 I DD_ST (µA) VDD (V) 13 12 11 22 20 18 16 VTH_OFF 14 10 12 9 10 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -15 10 35 60 85 110 135 110 135 Temperature (°C) Temperature (°C) IDD_OP vs. Temperature fOSC vs. Temperature 63 1.55 VCOMP = 2V, CL = 1nF VDD = 11V 62 1.50 VDD = 15V f OSC (kHz) I DD_OP (mA) VDD = 27V 1.45 VDD = 11V 1.40 61 VDD = 27V 60 VDD = 15V 1.35 59 1.30 58 57 1.25 -40 -15 10 35 60 85 110 -40 135 -15 10 35 60 85 Temperature (°C) Temperature (°C) VCOMP vs. Temperature DMAX vs. Temperature 5.60 80 COMP Open Voltage 79 5.56 78 76 VCOMP DMAX (%) 77 75 74 5.52 5.48 73 5.44 72 71 5.40 70 -40 -20 0 20 40 60 Temperature (°C) www.richtek.com 6 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature (°C) R7731A-10 August 2011 R7731A VCLAMP vs. Temperature 13.0 GATE vs. Temperature 350 VDD = 20V, CL = 1nF VDD = 20V, CL = 1nF 300 12.5 GATE (ns) VCLAMP (V) 250 12.0 11.5 11.0 Rising 200 150 Falling 100 10.5 50 0 10.0 -40 -15 10 35 60 85 110 -40 -25 -10 135 5 50 65 80 95 110 125 Temperature (°C) Temperature (°C) ISUPPLY vs. VDD ISUPPLY vs. Temperature 0.50 20 35 0.426 COMP Pin Open No Gate Output ISUPPLY = IDD_OP − ICOMP 0.424 0.422 COMP Pin Open No Gate Output ISUPPLY = IDD_OP − ICOMP I SUPPLY (mA) I SUPPLY (mA) 0.45 0.40 0.420 0.418 0.416 0.414 0.412 0.35 0.410 0.408 0.30 -40 -20 0 20 40 60 80 100 11 120 12 13 14 15 17 18 19 20 21 22 19 20 21 22 VDD (V) Temperature (°C) VCLAMP vs. VDD VGATE_OFF vs. VDD 13 600 ISOURCE = 20mA ISINK = 20mA 575 12 550 VCLAMP (V) VGATE_OFF (mV) 16 525 500 475 11 10 9 450 8 425 7 400 11 12 13 14 15 16 17 VDD (V) R7731A-10 August 2011 18 19 20 21 22 11 12 13 14 15 16 17 18 VDD (V) www.richtek.com 7 R7731A VCSTH vs. Temperature 0.890 0.875 VCSTH (V) 0.860 0.845 0.830 0.815 0.800 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) www.richtek.com 8 R7731A-10 August 2011 R7731A Application Information UVLO Leading Edge Blanking (LEB) Under Voltage LockOut (UVLO) block is to ensure VDD has reached proper operation voltage before we enable the whole IC blocks. To provide better temperature coefficient and precise UVLO threshold voltage, the reference voltage of hysteresis voltage (10V / 14V) is from band-gap block directly. By this way, R7731A can operate more reliable in different environments. MOSFET COSS, secondary rectifier reverse recovery current and gate driver sourcing current comprise initial current spike. The spike will seriously disturb current mode operation especially at light load and high line. R7731A provides built-in 420ns LEB to guarantee proper operation in diverse design. Noise Immunity The maximum start-up current (30μA) is only for leakage current of IC at UVLO(on)-0.1V. The external al-capacitor on VDD may have 5 to 6μA extra leakage current. So designed start-up current of the system should exceed 36μA or more and IC can start up normally. In addition, designed start-up current of system should be less than 380μA, and IC can work normally at hiccup mode. Jittering Oscillator For better EMI performance, R7731A will operate the system with ±6% frequency deviation around setting frequency. To guarantee precise frequency, it is trimmed to 5% tolerance. It also generates slope compensation saw-tooth, 75% maximum duty cycle pulse and overload protection slope. By adjusting resistor of RT pin according to the following formula : 6500 fOSC (kHz) = R T (k Ω ) It can typically operate between 50kHz to 130kHz. Note that RT pin can't be short or open otherwise oscillator will not operate. Current mode controller is very sensitive to noise. R7731A takes the advantages of Richtek long term experience in designing high noise immunity current mode circuit and layout. Also, we amplify current sense signal to compare with feedback signal instead of dividing feedback signal. All the effort is to provide clean and reliable current mode operation. Soft-Start During initial power on, especially at high line, current spike is kind of unlimited by current limit. Therefore, besides cycle-by-cycle current limiting, R7731A still provides soft-start function. It effectively suppresses the start-up current spike. As shown in the Figure 1 and Figure 2, the start-up VCS is about 0.3V lower than competitor. The typical soft-start duration is 4ms (RT = 100kΩ). Again, this will provide more reliable operation and possibility to use smaller current rating power MOSFET. V CS V OUT Built-in Slope Compensation To reduce component counts, slope compensation is implemented by internal built-in saw-tooth. Since it's builtin, it's compromised between loop gain and sub-harmonic reduction. In general design, it can cancel sub-harmonic to 90Vac. VOUT (2V/Div) VCS (500mV/Div) Figure 1. Competitor R7731A-10 August 2011 www.richtek.com 9 R7731A ` V CS During light load, switching loss will dominate the power efficiency calculation. This mode is to cut switching loss. As shown in Figure 3, when the output load gets light, feedback signal drops and touches VBURL (Typical value is 1.75V). Clock signal will be blanked and system ceases to switching. After VOUT drops and feedback signal goes back to VBURH (1.8V, typically), switching will be resumed. Burst mode so far is widely used in low power application because it's simple, reliable and will not have any patent infringement issue. VOUT (2V/Div) VCS (500mV/Div) ` Figure 2. R7731A Gate Driver A totem pole gate driver is fine tuned to meet both EMI and efficiency requirement in low power application. An internal pull low circuit is activated after pretty low VDD to prevent external MOSFET from accidentally turning on during UVLO. Burst Triple Mode To fulfill green mode requirement, there are 3 operation modes in R7731A. Please also refer to Figure 3 for details. ` PWM Mode For most of load condition, the circuit will run at traditional PWM current mode. Normal Operation Burst Mode V OUT Light Load VDD Holdup Mode When the VDD drops down to VDD turn off threshold voltage, the system will be shut down. During shut down period, controller does nothing to any load change and might cause VOUT down. To avoid this, when VDD drops to a setting threshold, 11V, the hysteresis comparator will bypass PWM and burst mode loop and force switching at a very low level to supply energy to VDD pin. The designed value is 11.25V with 0.5V hysteresis band. Furthermore, VDD holdup mode is only designed to prevent VDD from touching turn off threshold voltage under light load or load transient moment. Relative to burst mode, switching loss will increase on the system at VDD holdup mode, so it is highly recommended that the system should avoid operating at this mode during light load or no load condition, normally. No Load (VDD Holdup Mode) Load VDD VDD_High VDD_Low VCOMP VBURH VBURL VGATE Figure 3. Burst Triple Mode www.richtek.com 10 R7731A-10 August 2011 R7731A Protection Negative Voltage Spike on Each Pin R7731A provides fruitful protection functions that intend to protect system from being damaged. All the protection functions can be listed as below : Negative voltage (< −0.3V) on each pin will cause substrate injection. It leads to controller damage or circuit false trigger. Generally, it happens at CS pin due to negative spike because of improper layout or inductive current sense resistor. Therefore, it is highly recommended to add a R-C filter to avoid CS pin damage, as shown in Figure 4. Proper layout and careful circuit design should be done to guarantee yield rate in mass production. ` Cycle-by-Cycle Current Limit This is a basic but very useful function and it can be implemented easily in current mode controller. ` Over Load Protection Long time cycle-by-cycle current limit will lead to system thermal stress. To further protect system, system will be shut down after about 4096 clock cycles. it's about 60ms delay in 67kHz operation. After shutdown, system will resume and behave as hiccup. By proper start-up resistor design, thermal will be averaged to an acceptable level over the ON/OFF cycle of IC. This will last until fault is removed. #It's highly recommended to add a resistor in parallel with the opto-coupler. To provide sufficient bias current to make TL-431 regulate properly, 1.2kΩ resistor is suggested. AC Mains (90V to 265V) VDD R7731A GATE CS R-C Filter ` Brownout Protection During heavy load, this will trigger 60ms protection and shut down the system. If it's in light load condition, system will be shut down after VDD is running low and triggers UVLO. ` Figure 4. R-C Filter on CS Pin OVP Output voltage can be roughly sensed by VDD pin.If the sensed voltage reaches 27V threshold, system will be shut down after 20μs deglitch delay. ` Feedback Open and Opto-Coupler Short This will trigger OVP or 60ms delay protection. It depends on which one occurs first. ` OTP Internal OTP function will protect the controller itself from suffering thermal stress and permanent damage. It stops the system from switching until the temperature is under threshold level. Meanwhile, if VDD reaches VDD turn off threshold voltage, system will hiccup till over temperature condition is gone. R7731A-10 August 2011 www.richtek.com 11 R7731A Layout Consideration It is good for reducing noise, output ripple and EMI issue to separate ground traces of bulk capacitor (a), MOSFET (b), auxiliary winding (c) and IC control circuit (d). Finally, connect them together on bulk capacitor ground (a). The areas of these ground traces should be kept large. A proper PCB layout can abate unknown noise interference and EMI issue in the switching power supply. Please refer to the guidelines when you want to design PCB layout for switching power supply: Placing bypass capacitor for abating noise on IC is highly recommended. The bypass capacitor should be placed as close to controller as possible. The current path (1) from bulk capacitor, transformer, MOSFET, Rcs return to bulk capacitor is a huge high frequency current loop. It must be as short as possible to decrease noise coupling and kept a space to other low voltage traces, such as IC control circuit paths, especially. Besides, the path (2) from RCD snubber circuit to MOSFET is also a high switching loop, too. So keep it as small as possible. AC Mains (90V to 265V) CBULK To minimize reflected trace inductance and EMI minimize the area of the loop connecting the secondary winding, the output diode, and the output filter capacitor. In addition, provide sufficient copper area at the anode and cathode terminal of the diode for heatsinking. Provide a larger area at the quiet cathode terminal. A large anode area can increase high-frequency radiated EMI. (2) (a) CBULK Ground (a) + Trace RT COMP VDD (c) GATE R7731A GND (d) IC Ground (d) Trace Auxiliary Ground (c) Trace MOSFET Ground (b) (1) CS (b) Figure 5. PCB Layout Guide www.richtek.com 12 R7731A-10 August 2011 R7731A Outline Dimension H D L C B b A A1 e Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.889 1.295 0.031 0.051 A1 0.000 0.152 0.000 0.006 B 1.397 1.803 0.055 0.071 b 0.250 0.560 0.010 0.022 C 2.591 2.997 0.102 0.118 D 2.692 3.099 0.106 0.122 e 0.838 1.041 0.033 0.041 H 0.080 0.254 0.003 0.010 L 0.300 0.610 0.012 0.024 SOT-23-6 Surface Mount Package R7731A-10 August 2011 www.richtek.com 13 R7731A A B E J C L I D F Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 9.068 9.627 0.357 0.379 B 6.198 6.604 0.244 0.260 C 3.556 4.318 0.140 0.170 D 0.356 0.559 0.014 0.022 E 1.397 1.651 0.055 0.065 F 2.337 2.743 0.092 0.108 I 3.048 3.556 0.120 0.140 J 7.366 8.255 0.290 0.325 L 0.381 0.015 8-Lead DIP Plastic Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. www.richtek.com 14 R7731A-10 August 2011