® RT8055 3A, 2MHz, Synchronous Step-Down Converter General Description Features The RT8055 is a high efficiency synchronous, step-down DC/DC converter. Its input voltage range is from 2.6V to 5.5V and provides an adjustable regulated output voltage from 0.8V to 5V while delivering up to 3A of output current. z set by an external resistor. The 100% duty cycle provides low dropout operation extending battery life in portable systems. Current mode operation with external compensation allows the transient response to be optimized over a wide range of loads and output capacitors. z z z z z z z Applications z The RT8055 is operated in forced continuous PWM Mode which minimizes ripple voltage and reduces the noise and RF interference. The RT8055 is available in the WDFN-10L 3x3 and SOP-8 (Exposed Pad) packages. z z z z z z Ordering Information RT8055 Package Type QW : WDFN-10L 3x3 (W-Type) SP : SOP-8 (Exposed Pad-Option 2) Lead Plating System G : Green (Halogen Free and Pb Free) Z : ECO (Ecological Element with Halogen Free and Pb free) Low RDS(ON) Internal Switches : 100mΩ Ω Programmable Frequency : 300kHz to 2MHz No Schottky Diode Required 0.8V Reference Voltage Allows for Low Output Voltage Forced Continuous Mode Operation 100% Duty Cycle Operation Input Over Voltage Protection RoHS Compliant and Halogen Free Portable Instruments Battery-Powered Equipment Notebook Computers Distributed Power Systems IP Phones Digital Cameras 3G/3.5G Data Card Pin Configurations (TOP VIEW) SHDN/RT GND LX LX PGND 1 2 3 10 9 GND The internal synchronous low on-resistance power switches increase efficiency and eliminate the need for an external Schottky diode. The switching frequency is z High Efficiency : Up to 95% 4 5 8 7 6 11 COMP FB VDD PVDD PVDD WDFN-10L 3x3 Note : Richtek products are : ` RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. SHDN/RT GND 2 LX 3 PGND 4 GND 8 COMP 7 FB 6 VDD 5 PVDD 9 SOP-8 (Exposed Pad) Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8055-05 November 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT8055 Marking Information RT8055GQW RT8055GSP JN= : Product Code RT8055GSP : Product Number RT8055 GSPYMDNN YMDNN : Date Code JN=YM DNN YMDNN : Date Code RT8055ZQW JN : Product Code YMDNN : Date Code JN YM DNN Typical Application Circuit VIN 5V L1 2µH CIN 22µF PVDD RT8055 VDD C1 0.1µF ROSC 180k VOUT 3.3V/3A LX R1 75k COUT 22µF x 2 FB SHDN/RT R2 24k COMP RCOMP 30k GND PGND CCOMP 470pF Table 1. Recommended Component Selection VOUT R1 (kΩ) R2 (kΩ) R COMP (kΩ) CCOMP (nF) L1 (μH) COUT (μF) 3.3 75 24 30 0.47 2.2 22 x 2 2.5 51 24 27 0.47 2.2 22 x 2 1.8 30 24 22 0.47 2.2 22 x 2 1.5 21 24 18 0.47 2.2 22 x 2 1.2 12 24 15 0.47 1.0 22 x 2 1.0 6 24 13 0.47 1.0 22 x 2 Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS8055-05 November 2012 RT8055 Functional Pin Description Pin No. WDFN-10L 3x3 SOP-8 1 1 Pin Name Pin Function Shutdown Control or Frequency Setting Input. Connect a SHDN/RT resistor to ground from this pin sets the switching frequency. Force this pin to VDD or GND causes the device to be shut down. Signal Ground. All small-signal components and compensation 2, components should be connected to this ground, which in turn 2, GND 11 (Exposed Pad) 9 (Exposed Pad) connects to PGND at one point. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. Internal Power MOSFET Switches Output. Connect this pin to 3, 4 3 LX 5 4 PGND 6, 7 5 PVDD 8 6 VDD 9 7 FB 10 8 COMP the inductor. Power Ground. Connect this pin close to the negative terminal of CIN and COUT . Power Supply Input. Decouple this pin to PGND with a capacitor. Signal Supply Input. Decouple this pin to GND with a capacitor. Generally, VDD is equal to PVDD. Feedback Pin. This pin receives the feedback voltage from a resistive divider connected across the output. Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Connect external compensation elements to this pin to stabilize the control loop. Function Block Diagram SHDN/RT PVDD ISEN SD OSC Slope Comp. COMP 0.8V FB EA Output Clamp OC Limit Internal Soft Star Driver LX Control Logic 0.7V NISEN OTP POR PGND N-MOSFET ILIM 0.4V VREF GND VDD Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8055-05 November 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT8055 Absolute Maximum Ratings z z z z z z z z z z (Note 1) Supply Input Voltage, VDD, PVDD ---------------------------------------------------------------------------- −0.3V to 6.5V LX Pin Switch Voltage -------------------------------------------------------------------------------------------- −0.3V to (PVDD + 0.3V) <10ns ---------------------------------------------------------------------------------------------------------------- −5V to 8.5V Other I/O Pin Voltages ------------------------------------------------------------------------------------------- −0.3V to 6.5V LX Pin Switch Current -------------------------------------------------------------------------------------------- 4A Power Dissipation, PD @ TA = 25°C WDFN-10L 3x3 ----------------------------------------------------------------------------------------------------- 1.667W SOP-8 (Exposed Pad) ------------------------------------------------------------------------------------------- 1.333W Package Thermal Resistance (Note 2) WDFN-10L 3x3, θJA ----------------------------------------------------------------------------------------------- 60°C/W WDFN-10L 3x3, θJC ----------------------------------------------------------------------------------------------- 7.8°C/W SOP-8 (Exposed Pad), θJA ------------------------------------------------------------------------------------- 75°C/W SOP-8 (Exposed Pad), θJC ------------------------------------------------------------------------------------- 15°C/W Junction Temperature --------------------------------------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------------------- 260°C Storage Temperature Range ------------------------------------------------------------------------------------ −65°C to 150°C ESD Susceptibility (Note 3) HBM (Human Body Model) -------------------------------------------------------------------------------------- 2kV Recommended Operating Conditions z z z (Note 4) Supply Input Voltage ---------------------------------------------------------------------------------------------- 2.6V to 5.5V Junction Temperature Range ------------------------------------------------------------------------------------ −40°C to 125°C Ambient Temperature Range ------------------------------------------------------------------------------------ −40°C to 85°C Electrical Characteristics (VDD = 3.3V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Input Voltage Range VDD 2.6 -- 5.5 V Feedback Reference Voltage VREF 0.784 0.8 0.816 V Feedback Leakage Current IFB VFB = 3.3V -- -- 0.1 μA Active , VFB = 0.7V, Not Switching -- 500 -- μA Shutdown -- -- 1 μA DC Bias Current Output Voltage Line Regulation ΔVLINE VIN = 2.6V to 5.5V -- 0.1 -- %/V Output Voltage Load Regulation ΔVLOAD VIN = 5V, VOUT = 3.3V, IOUT = 0A to 3A -- 0.4 -- % Error Amplifier Transconductance gm -- 400 -- μA/V Current Sense Transresistance RS -- 0.4 -- Ω -- -- 1 μA RT Leakage Current SHDN/RT = VIN = 5.5V Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS8055-05 November 2012 RT8055 Parameter Symbol Switching Frequency Test Conditions Min Typ Max R OSC = 180kΩ 1.44 1.8 2.16 Adjustable Switching Frequency Range 0.3 -- 2 Unit MHz Switch On Resistance, High RDS(ON)_P ISW = 0.3A -- 100 160 mΩ Switch On Resistance, Low RDS(ON)_N ISW = 0.3A -- 100 170 mΩ Peak Current Limit ILIM 3.5 -- -- A VDD Rising @Full Temperature 2.33 2.4 2.57 VDD Falling @Full Temperature 1.98 2.2 2.37 Under Voltage Lockout Threshold (Note 5) Shutdown Threshold VSHDN VSHDN Rising -- VIN − 0.85 VIN − 0.4 V V Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guaranteed by design. Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8055-05 November 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT8055 Typical Operating Characteristics Output Voltage vs. Input Voltage Efficiency vs. Output Current 3.36 100 90 3.35 Output Voltage (V) Efficiency (%) 80 70 60 50 40 30 20 3.34 3.33 3.32 3.31 10 VIN = 5V, VOUT = 3.3V IOUT = 0A, VOUT = 3.3V 3.30 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.5 3.0 3.7 3.9 4.1 Output Current (A) 4.7 4.9 5.1 5.3 5.5 VIN UVLO vs. Temperature 3.38 2.50 3.37 2.45 3.36 2.40 3.35 3.34 VIN UVLO (V) Output Voltage (V) 4.5 Input Voltage (V) Output Voltage vs. Output Current 3.33 3.32 3.31 3.30 3.29 Rising 2.35 2.30 2.25 2.20 Falling 2.15 2.10 3.28 3.27 VIN = 5V, VOUT = 3.3V 2.05 VOUT = 3.3V 2.00 3.26 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 -50 3.0 -25 0 25 50 75 100 125 Temperature (°C) Output Current (A) Switching Frequency vs. Temperature Switching Frequency vs. Input Voltage 2.1 2.1 2.0 1.9 1.8 1.7 1.6 VIN = 5V, VOUT = 3.3V IOUT = 0.3A, fSW = 1.8MHz 1.5 Switching Frequency (MHz)1 Switching Frequency (MHz)1 4.3 2.0 1.9 1.8 1.7 1.6 VIN = 5V, VOUT = 3.3V IOUT = 0.3A, fSW = 1.8MHz 1.5 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 Input Voltage (V) Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 5.5 -50 -25 0 25 50 75 100 125 Temperature (°C) is a registered trademark of Richtek Technology Corporation. DS8055-05 November 2012 RT8055 Output Current Limit vs. Temperature 6.0 5.5 5.5 Output Current Limit (A) Output Current Limit (A) Output Current Limit vs. Input Voltage 6.0 5.0 4.5 4.0 3.5 3.0 2.5 5.0 4.5 4.0 3.5 3.0 2.5 VIN = 5V, VOUT = 3.3V VOUT = 3.3V 2.0 2.0 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 -50 -25 0 3.38 0.832 3.36 0.824 3.34 3.32 3.30 3.28 3.26 3.24 VIN = 5V, VOUT = 3.3V IOUT = 0A 75 100 125 0.816 0.808 0.800 0.792 0.784 0.776 0.768 0.760 3.20 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 Temperature (°C) Temperature (°C) Output Ripple Output Ripple VLX (5V/Div) VLX (5V/Div) VOUT (5mV/Div) VOUT (5mV/Div) VIN = 5V, VOUT = 3.3V IOUT = 3A Time (500ns/Div) Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8055-05 50 Reference Voltage vs. Temperature 0.840 Reference Voltage (V) Output Voltage (V) Output Voltage vs. Temperature 3.40 3.22 25 Temperature (°C) Input Voltage (V) November 2012 100 125 VIN = 5V, VOUT = 3.3V IOUT = 0A Time (500ns/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT8055 Load Transient Response Load Transient Response VOUT (200mV/Div) VOUT (200mV/Div) IOUT (1A/Div) IOUT (1A/Div) VIN = 5V, VOUT = 3.3V IOUT = 0A to 3A VIN = 5V, VOUT = 3.3V IOUT = 0A to 2A Time (100μs/Div) Time (100μs/Div) Power On from VIN UVP Shutdown VLX (5V/Div) VLX (5V/Div) VIN (2V/Div) VOUT (1V/Div) VIN = 5V, VOUT = 3.3V IOUT = 0A Time (1ms/Div) Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 VOUT (1V/Div) VIN = 5V, VOUT = 3.3V Time (10μs/Div) is a registered trademark of Richtek Technology Corporation. DS8055-05 November 2012 RT8055 Application Information Output Voltage Setting The output voltage is set by an external resistive divider according to the following equation : VOUT = VREF × ⎛⎜1 + R1 ⎞⎟ ⎝ R2 ⎠ where VREF equals to 0.8V typical. The resistive divider allows the FB pin to sense a fraction of the output voltage as shown in Figure 1. VOUT R1 FB RT8055 R2 GND Figure 1. Setting the Output Voltage Soft-Start The RT8055 contains an internal soft-start clamp that gradually raises the clamp on the COMP pin. Operating Frequency Selection of the operating frequency is a tradeoff between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Operation at lower frequency improves efficiency by reducing internal gate charge and switching losses but requires larger inductance and/or capacitance to maintain low output ripple voltage. The operating frequency of the RT8055 is determined by an external resistor that is connected between the SHDN/ RT pin and GND. The value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator. The RT resistor value can be determined by examining the frequency vs. RRT curve. Although frequencies as high as 2MHz are possible, the minimum on-time of the RT8055 imposes a minimum limit on the operating duty cycle. The minimum on-time is typically 110ns. Therefore, the minimum duty cycle is equal to 100 x 110ns x f (Hz). Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8055-05 November 2012 3.0 Switching Frequency (MHz)1 The basic RT8055 application circuit is shown in Typical Application Circuit. External component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by CIN and COUT. 2.5 RRT = 180k for 1.8MHz 2.0 1.5 1.0 0.5 0.0 0 200 400 600 800 1000 ROSC (K (kΩ)) Figure 2 100% Duty Cycle Operation When the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle eventually reaching 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the internal P-MOSFET and the inductor. Low Supply Operation The RT8055 is designed to operate down to an input supply voltage of 2.6V. One important consideration at low input supply voltages is that the RDS(ON) of the P-Channel and N-Channel power switches increases. The user should calculate the power dissipation when the RT8055 is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant frequency architectures by preventing sub-harmonic oscillations at duty cycles greater than 50%. It is accomplished internally by adding a compensating ramp to the inductor current signal. Normally, the maximum inductor peak current is reduced when slope compensation is added. In the RT8055, however, separated inductor current signals are used to monitor over current condition. is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT8055 This keeps the maximum output current relatively constant regardless of duty cycle. Short Circuit Protection When the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. A current runaway detector is used to monitor inductor current. As current increasing beyond the control of current loop, switching cycles will be skipped to prevent current runaway from occurring. Inductor Selection The inductor value and operating frequency determine the ripple current according to a specific input and output voltage. The ripple current ΔIL increases with higher VIN and decreases with higher inductance. V V ΔIL = ⎡⎢ OUT ⎤⎥ × ⎡⎢1− OUT ⎤⎥ VIN ⎦ ⎣ f ×L ⎦ ⎣ This formula has a maximum at VIN = 2VOUT, where I RMS = I OUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. The selection of COUT is determined by the effective series resistance (ESR) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, ΔVOUT, is determined by : ⎡ 1 ⎤ ΔVOUT ≤ ΔIL ⎢ESR + ⎥ 8fC OUT ⎦ ⎣ The inductor's current rating (caused a 40°C temperature rising from 25°C ambient) should be greater than the maximum load current and its saturation current should be greater than the short circuit peak current limit. The output ripple is highest at maximum input voltage since ΔIL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. CIN and COUT Selection Using Ceramic Input and Output Capacitors The input capacitance, C IN, is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent large ripple voltage, a low ESR input capacitor sized for the maximum RMS current should be used. RMS current is given by : Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input Having a lower ripple current reduces not only the ESR losses in the output capacitors but also the output voltage ripple. However, it requires a large inductor to achieve this goal. For the ripple current selection, the value of ΔIL = 0.4(IMAX) will be a reasonable starting point. The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation : ⎡ VOUT ⎤ ⎡ VOUT ⎤ L =⎢ × ⎢1 − ⎥ ⎥ ⎣ f × ΔIL(MAX) ⎦ ⎣ VIN(MAX) ⎦ IRMS = IOUT(MAX) VOUT VIN VIN −1 VOUT Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 is a registered trademark of Richtek Technology Corporation. DS8055-05 November 2012 RT8055 Maximum Power Dissipation (W) and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VDD. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 125°C. The junction to ambient thermal resistance, θJA, is layout dependent. For SOP-8 (Exposed Pad) packages, the thermal resistance, θJA, is 75°C/W on a standard JEDEC 51-7 four-layer thermal test board. For WDFN-10L 3x3 packages, the thermal resistance, θJA, is 70°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formulas : The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. The derating curves in Figure 3 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8055-05 November 2012 Four-Layer PCB WDFN-10L 3x3 SOP-8 (Exposed Pad) 0 25 50 75 100 125 Ambient Temperature (°C) Figure 3. Derating Curve of Maximum Power Dissipation Layout Considerations Follow the PCB layout guidelines for optimal performance of RT8055. ` A ground plane is recommended. If a ground plane layer is not used, the signal and power grounds should be segregated with all small-signal components returning to the GND pin at one point that is then connected to the PGND pin close to the IC. The exposed pad should be connected to GND. ` Connect the terminal of the input capacitor(s), CIN, as close as possible to the PVDD pin. This capacitor provides the AC current into the internal power MOSFETs. ` LX node is with high frequency voltage swing and should be kept within small area. Keep all sensitive small-signal nodes away from the LX node to prevent stray capacitive noise pick-up. ` Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of powercomponents. PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W for SOP-8 (Exposed Pad) package PD(MAX) = (125°C − 25°C) / (70°C/W) = 1.429W for WDFN-10L 3x3 package 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 You can connect the copper areas to any DC net (PVDD, VDD, VOUT, PGND, GND, or any other DC rail in your system). ` Connect the FB pin directly to the feedback resistors. The resistor divider must be connected between VOUT and GND. is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT8055 Connect the FB pin directly to feedback resistors. The resistor divider must be connected between VOUT and GND. VOUT GND CCOMP ROSC RCOMP SHDN/RT GND LX LX PGND L1 VOUT 1 2 3 4 5 10 9 GND LX should be connected to Inductor by wide and short trace, keep sensitive compontents away from this trace COUT Output capacitor must be near RT8055 8 11 7 6 COMP FB VDD PVDD PVDD R2 R1 CIN CF VIN CIN must be placed between VDD and GND as closer as possible Figure 4. PCB Layout Guide Recommended component selection for Typical Application Table 2. Inductors Component Supplier Series TAIYO YUDEN NR 8040 Inductance (μH) DCR (mΩ) Current Rating (mA) Dimensions (mm) 2 9 7800 8x8x4 Table 3. Capacitors for CIN and COUT Component Supplier Part No. Capacitance (μF) Case Size TDK C3225X5R0J226M 22 1210 TDK C2012X5R0J106M 10 0805 Panasonic ECJ4YB0J226M 22 1210 Panasonic ECJ4YB1A106M 10 1210 TAIYO YUDEN LMK325BJ226ML 22 1210 TAIYO YUDEN JMK316BJ226ML 22 1206 TAIYO YUDEN JMK212BJ106ML 10 0805 Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 is a registered trademark of Richtek Technology Corporation. DS8055-05 November 2012 RT8055 Outline Dimension D2 D L E E2 1 e SEE DETAIL A b 2 1 2 1 A A1 A3 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 2.300 2.650 0.091 0.104 E 2.950 3.050 0.116 0.120 E2 1.500 1.750 0.059 0.069 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 10L DFN 3x3 Package Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8055-05 November 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT8055 H A M EXPOSED THERMAL PAD (Bottom of Package) Y J X B F C I D Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 4.000 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.510 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.000 0.152 0.000 0.006 J 5.791 6.200 0.228 0.244 M 0.406 1.270 0.016 0.050 X 2.000 2.300 0.079 0.091 Y 2.000 2.300 0.079 0.091 X 2.100 2.500 0.083 0.098 Y 3.000 3.500 0.118 0.138 Option 1 Option 2 8-Lead SOP (Exposed Pad) Plastic Package Richtek Technology Corporation 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. www.richtek.com 14 DS8055-05 November 2012