® RT8061A 3A, 1MHz, Synchronous Step-Down Converter General Description Features The RT8061A is a high efficiency synchronous, step-down DC/DC converter. Its input voltage range from 2.7V to 5.5V that provides an adjustable regulated output voltage from 0.6V to VIN while delivering up to 3A of output current. z The internal synchronous low on resistance power switches increase efficiency and eliminate the need for an external Schottky diode. The switching frequency is fixed internally at 1MHz. The 100% duty cycle provides low dropout operation, hence extending battery life in portable systems. Current mode operation with internal compensation allows the transient response to be optimized over a wide range of loads and output capacitors. The RT8061A is operated in PWM/PSM mode to achieve high efficiency for a wide load range. The RT8061A is available in a WDFN-10L 3x3 package. z z z z z z z z z z z Ordering Information z RT8061A z Note : Richtek products are : ` RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Portable Instruments Battery-Powered Equipment Notebook Computers Distributed Power Systems IP Phones Digital Cameras Pin Configurations (TOP VIEW) NC LX LX PGOOD EN 1 2 3 4 5 GND Lead Plating System Z : ECO (Ecological Element with Halogen Free and Pb free) Ω/49mΩ Ω at VIN Low RDS(ON) Internal Switches : 69mΩ = 5V Fixed Frequency : 1MHz No Schottky Diode Required 0.6V Reference Allows Low Output Voltage PWM/PSM Mode Operation Low Dropout Operation : 100% Duty Cycle OCP, UVP, OVP, OTP RoHS Compliant and Halogen Free Applications z Package Type QW : WDFN-10L 3x3 (W-Type) High Efficiency : Up to 95% 11 10 9 8 7 6 PVIN PVIN SVIN NC FB WDFN-10L 3x3 Suitable for use in SnPb or Pb-free soldering processes. Marking Information 11 : Product Code 11 YM DNN YMDNN : Date Code Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8061A-04 September 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT8061A Typical Application Circuit RT8061A 4 PGOOD PGOOD LX 2, 3 LOUT VOUT R1 9, 10 VIN CIN 8 RFB1 PVIN FB 5 SVIN RFB2 GND EN COUT 6 C1 Chip Enable CFF 11 (Exposed Pad) Functional Pin Description Pin No. Pin Name Pin Function 1, 7 NC No Internal Connection. 2, 3 LX Switch Node. Connection this pin to the inductor. 4 PGOOD Power Good Indicator. This pin is an open drain logic output that is pulled to ground when the output voltage is less than 90% of the target output voltage. 5 EN Enable Control. Pull high to turn on. Do not float. 6 FB Feedback. This pin receives the feedback voltage from a resistive voltage divider connected across the output. 8 SVIN Signal Input. Decouple this pin to GND with at least 1μF ceramic cap. 9, 10 PVIN Power Input. Decouple this pin to GND with at least 4.7μF ceramic cap. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. 11 (Exposed Pad) GND Function Block Diagram EN Slope Com OSC PGOOD PGOOD 0.6V FB EN PVIN ISEN EN Output Clamp OC Limit Int-SS Driver LX 0.72V OV Control Logic 0.54V NISEN PGOOD 0.4V POR Zero Current UV VREF OTP SVIN Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS8061A-04 September 2012 RT8061A Absolute Maximum Ratings z z z z z z z z z (Note 1) Supply Input Voltage, PVIN, SVIN -------------------------------------------------------------------------------LX Pin Voltage --------------------------------------------------------------------------------------------------------Other I/O Pin Voltage -----------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C WDNF-10L 3x3 -------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) WDFN-10L 3x3, θJA -------------------------------------------------------------------------------------------------WDFN-10L 3x3 θJC -------------------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Model) ----------------------------------------------------------------------------------------- Recommended Operating Conditions z z z −0.3V to 6.5V (VIN + 0.3V) to 6.8V −0.3V to 6.5V 1.429W 70°C/W 8.2°C/W 150°C 260°C −65°C to 150°C 2kV (Note 4) Supply Input Voltage, PVIN, SVIN -------------------------------------------------------------------------------- 2.7V to 5.5V Junction Temperature Range --------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range --------------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VIN = 3.3V, TA = 25°C, unless otherwise specified) Parameter Symbol Min Typ Max Unit 0.594 0.6 0.606 V -- 0.1 0.4 μA Active , VFB = 0.7V, Not Switching -- 110 140 Shutdown -- -- 1 Output Voltage Line Regulation VIN = 2.7V to 5.5V IOUT = 0A -- 0.3 -- %/V Output Voltage Load Regulation IOUT = 0A to 3A −1 -- 1 % Switch Leakage Current VEN = 0A -- -- 1 μA 0.8 1 1.2 MHz Feedback Reference Voltage VREF Feedback Leakage Current IFB DC Bias Current Test Conditions Switching Frequency μA Switch On Resistance, High R DS(ON)_P VIN = 5V -- 69 -- mΩ Switch On Resistance, Low RDS(ON)_N VIN = 5V -- 49 -- mΩ PMOS Current Limit (latch-off) ILIM 4 -- -- A Under Voltage Lockout Threshold VUVLO VIN Rising 2.2 2.4 2.6 VIN Falling 2 2.2 2.4 EN Threshold Voltage Logic-High VIH 1.6 -- -- Logic-Low VIL -- -- 0.4 -- 500 -- EN Pull Low Resistance Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8061A-04 September 2012 V V kΩ is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT8061A Parameter Symbol Test Conditions Min Typ Max Unit Over Temperature Protection (latch-off) TSD -- 150 -- °C Soft-Start Time tSS 500 -- -- μs -- 100 -- Ω 115 120 130 % 57 66 75 % 85 90 -- % -- 5 -- % VOUT Discharge Resistance VOUT Over Voltage Protection (latch-off, delay time = 10μs) VOUT Under Voltage Lockout Threshold (latch-off) Power Good Measured FB, With Respect to VREF Power Good Hysteresis Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS8061A-04 September 2012 RT8061A Typical Operating Characteristics Efficiency vs. Load Current Efficiency vs. Load Current 100 100 98 98 Efficiency (%) Efficiency (%) 96 96 VIN = 5V 94 92 VIN = 4.2V 94 92 VIN = 5V 90 88 86 90 VIN = 3.3V 84 88 82 VOUT = 3.3V 86 VOUT = 1.8V 80 0 0.5 1 1.5 2 2.5 3 0 0.5 1 Load Current (A) Efficiency vs. Load Current 2 2.5 3 Output Voltage vs. Output Current 100 1.820 Output Voltage (V) 95 Efficiency (%) 1.5 Load Current (A) 90 85 VIN = 5V 80 VIN = 3.3V 1.812 1.804 VIN = 3.3V 1.796 VIN = 5V 1.788 75 VOUT = 1.8V VOUT = 1.05V 70 1.780 0 0.5 1 1.5 2 2.5 3 0 0.6 1.2 Load Current (A) 1.8 2.4 3 Output Current (A) Current Limit vs. Input Voltage Current Limit vs. Temperature 7.0 7.0 6.5 VIN = 5V Current Limit (A) Current Limit (A) 6.2 6.0 5.5 5.0 4.5 VIN = 3.3V 5.4 4.6 4.0 3.8 3.5 VOUT = 1.05V 3.0 VOUT = 1.05V 3.0 2.5 3 3.5 4 4.5 5 Input Voltage (V) Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8061A-04 September 2012 5.5 -50 -25 0 25 50 75 100 125 Temperature (°C) is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT8061A RDS(ON) vs. Temperature Load Transient Response 90 VOUT (50mV/Div) RDS(ON) (m Ω ) 79 P-MOSFET 68 57 IOUT (2A/Div) N-MOSFET 46 VIN = 5V VIN = 5V, VOUT = 1.8V, IOUT = 0.5A to 3A 35 -50 -25 0 25 50 75 100 125 Time (50μs/Div) Temperature (°C) Load Transient Response VOUT (50mV/Div) Switching VOUT (5mV/Div) VLX (500mV/Div) IOUT (2A/Div) ILX (1A/Div) VIN = 5V, VOUT = 1.8V, IOUT = 1.5A to 3A VIN = 5V, VOUT = 1.8V, IOUT = 1.5A Time (50μs/Div) Time (500ns/Div) Switching Over Voltage Protection VOUT (5mV/Div) VOUT (1V/Div) VLX (500mV/Div) VLX (2V/Div) ILX (2A/Div) VIN = 5V, VOUT = 1.8V, IOUT = 3A Time (500ns/Div) Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 VIN = 5V, VOUT = 1.8V, IOUT = 1A Time (10μs/Div) is a registered trademark of Richtek Technology Corporation. DS8061A-04 September 2012 RT8061A Under Voltage Protection Over Current Protection ILX (5A/Div) VOUT (1V/Div) VOUT (1V/Div) VLX (2V/Div) VLX (5V/Div) VIN = 5V, VOUT = 1.8V VIN = 5V, VOUT = 1.8V Time (5μs/Div) Time (2.5μs/Div) Power On from VIN Power Off from VIN VIN (2V/Div) VIN (2V/Div) VOUT (1V/Div) VOUT (1V/Div) ILX (2A/Div) ILX (2A/Div) VOUT = 1.8V, IOUT = 3A VOUT = 1.8V, IOUT = 3A Time (2.5ms/Div) Time (2.5ms/Div) Power On from EN Power Off from EN VEN (5V/Div) VEN (5V/Div) VOUT (1V/Div) VOUT (1V/Div) ILX (2A/Div) ILX (2A/Div) VIN = 5V, VOUT = 1.8V, IOUT = 3A Time (200μs/Div) Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8061A-04 September 2012 VIN = 5V, VOUT = 1.8V, IOUT = 3A Time (40μs/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT8061A Application Information The RT8061A is a single-phase buck PWM converter. It provides single feedback loop, current mode control with fast transient response. An internal 0.6V reference allows the output voltage to be precisely regulated for low output voltage applications. A fixed switching frequency (1MHz) oscillator and internal compensation are integrated to minimize external component count. Protection features include over current protection, under voltage protection, over voltage protection and over temperature protection. PWM Operation The RT8061A utilizes DEM control to improve light load efficiency. Depending on the load current, the controller automatically operates in Diode-Emulation Mode (DEM) or in Continuous Conduction Mode (CCM) with fixedfrequency PWM. At light load condition, the RT8061A automatically operates in diode-emulation mode to reduce switching frequency and improve efficiency. As the output current decreases from heavy load condition, the inductor current is also reduced and eventually comes to the point where its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. By emulating the behavior of diodes, the low side MOSFET allows only partial negative current to flow when the inductor freewheeling current reaches negative. As the load current further decreases, it takes longer and longer to discharge the output capacitor to the level that that requires the next UGATE “ON” cycle. In contrast, when the output current increases from light load to heavy load, the switching frequency increases to the preset value as the inductor current reaches the continuous conduction. The controller will then operate in continuous conduction mode with 1MHz fixed PWM switching frequency. Output Voltage Setting Connect a resistive voltage divider at the FB between VOUT and GND to adjust the output voltage. The output voltage is set according to the following equation : VOUT = VFB × ⎛⎜ 1+ R1 ⎞⎟ ⎝ R2 ⎠ where VFB is 0.6V (typ.). Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 VOUT R1 FB R2 GND Figure 1. Setting VOUT with a Voltage Divider Chip Enable and Disable The EN pin allows for power sequencing between the controller bias voltage and another voltage rail. The RT8061A remains in shutdown if the EN pin is lower than 400mV. When the EN pin rises above the VEN trip point, the RT8061A begins a new initialization and soft-start cycle. Internal Soft-Start The RT8061A provides an internal soft-start function to prevent large inrush current and output voltage overshoot when the converter starts up. The Soft-Start (SS) automatically begins once the chip is enabled. During softstart, the internal soft-start capacitor becomes charged and generates a linear ramping up voltage across the capacitor. This voltage clamps the voltage at the FB pin, causing PWM pulse width to increase slowly and in turn reduce the output surge current. The internal 0.6V reference takes over the loop control once the internal ramping-up voltage becomes higher than 0.6V. UVLO Protection The RT8061A has input Under Voltage Lockout protection (UVLO). If the input voltage exceeds the UVLO rising threshold voltage (2.4V typ.), the converter resets and prepares the PWM for operation. If the input voltage falls below the UVLO falling threshold voltage during normal operation, the device will stop switching. The UVLO rising and falling threshold voltage has a hysteresis to prevent noise-caused reset. Inductor Selection The switching frequency (on-time) and operating point (% ripple or LIR) determine the inductor value as shown below : L= VOUT × ( VIN − VOUT ) fSW × LIR × ILOAD(MAX) × VIN is a registered trademark of Richtek Technology Corporation. DS8061A-04 September 2012 RT8061A where LIR is the ratio of the peak-to-peak ripple current to the average inductor current. Find a low loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK) : IPEAK = ILOAD(MAX) + ⎛⎜ LIR × ILOAD(MAX) ⎞⎟ ⎝ 2 ⎠ The calculation above serves as a general reference. To further improve transient response, the output inductor can be further reduced. This relation should be considered along with the selection of the output capacitor. Input Capacitor Selection High quality ceramic input decoupling capacitor, such as X5R or X7R, with values greater than 20μF are recommended for the input capacitor. The X5R and X7R ceramic capacitors are usually selected for power regulator capacitors because the dielectric material has less capacitance variation and more temperature stability. Voltage rating and current rating are the key parameters when selecting an input capacitor. Generally, selecting an input capacitor with voltage rating 1.5 times greater than the maximum input voltage is a conservatively safe design. The input capacitor is used to supply the input RMS current, which can be approximately calculated using the following equation : VOUT ⎛ VOUT ⎞ × ⎜ 1− VIN VIN ⎟⎠ ⎝ The next step is selecting a proper capacitor for RMS current rating. One good design is using more than one capacitor with low Equivalent Series Resistance (ESR) in parallel to form a capacitor bank. IIN_RMS = ILOAD × The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be approximately calculated using the following equation : IOUT(MAX) × 0.25 ΔVIN = CIN × fSW For example, if IOUT(MAX) = 3A, CIN = 20μF, fSW = 1MHz, the input voltage ripple will be 37.5mV. Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8061A-04 September 2012 Output Capacitor Selection The output capacitor and the inductor form a low pass filter in the buck topology. In steady state condition, the ripple current flowing into/out of the capacitor results in ripple voltage. The output voltage ripple (VP-P) can be calculated by the following equation : 1 ⎞ VP-P = LIR × ILOAD(MAX) × ⎛⎜ ESR + 8 × COUT × fSW ⎟⎠ ⎝ When load transient occurs, the output capacitor supplies the load current before the controller can respond. Therefore, the ESR will dominate the output voltage sag during load transient. The output voltage undershoot (VSAG) can be calculated by the following equation : VSAG = ΔILOAD × ESR For a given output voltage sag specification, the ESR value can be determined. Another parameter that has influence on the output voltage sag is the equivalent series inductance (ESL). The rapid change in load current results in di/dt during transient. Therefore, the ESL contributes to part of the voltage sag. Using a capacitor with low ESL can obtain better transient performance. Generally, using several capacitors connected in parallel can have better transient performance than using a single capacitor for the same total ESR. Unlike the electrolytic capacitor, the ceramic capacitor has relatively low ESR and can reduce the voltage deviation during load transient. However, the ceramic capacitor can only provide low capacitance value. Therefore, use a mixed combination of electrolytic capacitor and ceramic capacitor to obtain better transient performance. Power Good Output (PGOOD) PGOOD is an open-drain type output and requires a pullup resistor. PGOOD is actively held low in soft-start, standby, and shutdown. It is released when the output voltage rises above 90% of nominal regulation point. The PGOOD signal goes low if the output is turned off or is 10% below its nominal regulation point. is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT8061A The output voltage can be continuously monitored for under voltage. When under voltage protection is enabled, both UGATE and LGATE gate drivers will be forced low if the output is less than 66% of its set voltage threshold. The UVP will be ignored for at least 3ms (typ.) after start up or a rising edge on the EN threshold. Toggle EN threshold or cycle VIN to reset the UVP fault latch and restart the controller. Over Voltage Protection (OVP) The RT8061A is latched once OVP is triggered and can only be released by toggling EN threshold or cycling VIN. There is a 10μs delay built into the over voltage protection circuit to prevent false transition. Over Current Protection (OCP) The RT8061A provides over current protection by detecting high side MOSFET peak inductor current. If the sensed peak inductor current remains over 4A (typ) for 5 clock cycles, OCP will be triggered. When OCP trips, the RT8061A will shut down and enter Latch-Off Mode to stop the energy transfer to the load. In Latch-Off Mode, the RT8061A can only be reset by EN or VIN. Thermal Shutdown (OTP) The device implements internal thermal shutdown when the junction temperature exceeds 150°C. When the OTP function is triggered, the RT8061A shuts down and enters Latch-Off Mode. In Latch-Off Mode, the RT8061A can be reset by EN or VIN. Thermal Considerations where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 125°C. The junction to ambient thermal resistance, θJA, is layout dependent. For WDFN-10L 3x3 packages, the thermal resistance, θJA, is 70°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula : PD(MAX) = (125°C − 25°C) / (70°C/W) = 1.429W for WDFN-10L 3x3 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. The derating curve in Figure 2 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. 1.6 Maximum Power Dissipation (W)1 Under Voltage Protection (UVP) Four-Layer PCB 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 2. Derating Curve of Maximum Power Dissipation For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) − TA) / θJA Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 is a registered trademark of Richtek Technology Corporation. DS8061A-04 September 2012 RT8061A ` ` Make the traces of the main current paths as short and wide as possible. Put the input capacitor as close as possible to the device pins (VIN and GND). ` LX node encounters high frequency voltage swings so it should be kept in a small area. Keep sensitive components away from the LX node to prevent stray capacitive noise pick-up. ` Ensure all feedback network connections are short and direct. Place the feedback network as close to the chip as possible. ` The GND pin and Exposed Pad should be connected to a strong ground plane for heat sinking and noise protection. ` An example of PCB layout guide is shown in Figure 3. for reference. Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS8061A-04 September 2012 COUT CIN1 NC VOUT LX LX RPGOOD PGOOD VIN EN REN 1 2 3 4 5 11 LX should be connected to inductor by wide and short trace. Keep sensitive components away from this trace. 10 9 8 7 6 PVIN PVIN SVIN NC FB CIN2 R2 R1 VOUT Layout is very important in high frequency switching converter design. The PCB can radiate excessive noise and contribute to converter instability with improper layout. Certain points must be considered before starting a layout using the RT8061A. Input capacitor must be placed as close to the IC as possible. GND The output capacitor must be placed near the IC. GND Layout Considerations The voltage divider must be connected as close to the device as possible. Figure 3. PCB Layout Guide is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT8061A Outline Dimension D2 D L E E2 1 e SEE DETAIL A b 2 1 2 1 A A1 A3 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 2.300 2.650 0.091 0.104 E 2.950 3.050 0.116 0.120 E2 1.500 1.750 0.059 0.069 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 10L DFN 3x3 Package Richtek Technology Corporation 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. www.richtek.com 12 DS8061A-04 September 2012