RICHTEK RT8868A

®
RT8868A
4/3/2/1-Phase PWM Controller for AMD AM2/AM2+/AM3 CPUs
General Description
Features
The RT8868A is a 4/3/2/1-phase synchronous buck
controller with two integrated MOSFET drivers for CPU
power application and a single-phase buck with integrated
MOSFET driver for North-Bridge (NB) chipset. The
RT8868A uses differential inductor DCR current sense to
achieve phase current balance and active voltage
positioning. Other features include adjustable operating
frequency, power good indication, external error-amp
compensation, over voltage protection, over current
protection and enable/shutdown for various applications.
The RT8868A comes in a small footprint with WQFN-48L
7x7 package.
z
12V Power Supply Voltage
z
4/3/2/1-Phase Power Conversion for VCORE Power
3 Embedded MOSFET Drivers (2 for CPU and 1 for
NB)
Internal Regulated 5V Output
Support AMD AM2 6-bit Parallel and AM2+ 7-bit
Serial VID Tables
Support 3.4MHz High Speed I2C
Continuous Differential Inductor DCR Current Sense
Adjustable Frequency (Typically at 300kHz)
Selectable 1 or 2 Phase in Power-Saving (PS) Mode
Phase-Interleaving for VCORE Controller
Power Good Indication
Adjustable Over Current Protection
Over Voltage Protection
Small 48-Lead WQFN Package
RoHS Compliant and Halogen Free
z
z
z
z
z
z
z
z
z
z
Applications
z
z
Desktop CPU Core Power
Low Voltage, High Current DC/DC Converter
Ordering Information
z
z
z
Pin Configurations
RT8868A
(TOP VIEW)
EN
PGOOD
VID5
VID4
VID3/SVC
VID2/SVD
VID1/PVI
VID0/VFIXEN
VCC12_NB
LGATE_NB
PHASE_NB
UGATE_NB
Package Type
QW : WQFN-48L 7x7 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
48 47 46 45 44 43 42 41 40 39 38 37
Note :
Richtek products are :
`
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
`
Suitable for use in SnPb or Pb-free soldering processes.
Marking Information
RT8868AGQW : Product Number
YMDNN : Date Code
1
36
2
35
3
34
4
33
5
32
6
7
31
GND
30
8
29
9
28
10
27
49
26
11
25
12
BOOT_NB
BOOT1
UGATE1
PHASE1
LGATE1
VCC12
LGATE2
PHASE2
UGATE2
BOOT2
PWM3
PWM4
13 14 15 16 17 18 19 20 21 22 23 24
IMAX_NB
IMAX
ISN1
ISP1
ISN2
ISP2
ISN3
ISP3
ISN4
ISP4
PS
VCC5
RT8868A
GQW
YMDNN
PWROK
RT
FBRTN
FBRTN_NB
FB_NB
COMP_NB
ISP_NB
ISN_NB
ADJ
OFS
COMP
FB
WQFN-48L 7x7
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8868A-00 May 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
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Copyright © 2012 Richtek Technology Corporation. All rights reserved.
VCCP_CORE
VCCP_CORE
L2
L2
12V
12V
BOOT
VCC
12V
GND
PWM
PWM
GND
VCC
ROFS
LGATE
RT9619
PHASE
UGATE
BOOT
LGATE
RT9619
PHASE
UGATE
ISP4
PWM4
EN
4
ISP_NB 7
8
ISN_NB
FB_NB 5
COMP_NB 6
PHASE_NB 38
LGATE_NB 39
BOOT_NB 36
UGATE_NB 37
13 IMAX_NB FBRTN_NB
PWROK
47 PGOOD
2 RT
14 IMAX
1
48
VID[5:0]
21 ISN4
10 OFS
22
25
3
ISP2 18
17
ISN2
FB 12
COMP 11
20 ISP3
19 ISN3
FBRTN
PHASE2 29
LGATE2 30
46 to 41
12V
23
BOOT2 27
UGATE2 28
PS
ISP1 16
15
ISN1
PHASE1 33
LGATE1 32
26 PWM3
VCC5
40 VCC12_NB
12V
24
31 VCC12
BOOT1 35
UGATE1 34
RT8868A
12V
9 ADJ
12V
12V
12V
L2
L2
L1
NTC
LOAD
VCCP_NB
LOAD
VCCP_CORE
VCCP_CORE
RT8868A
Typical Application Circuit
is a registered trademark of Richtek Technology Corporation.
DS8868A-00 May 2012
RT8868A
Table 1. 7-bit VID Code Table for AM2+/AM3 CPU (Serial)
SVID[6:0]
Voltage
SVID[6:0]
Voltage
SVID[6:0]
Voltage
SVID[6:0]
Voltage
0000000
1.5500
0100000
1.1500
1000000
0.7500
1100000
0.3500
0000001
1.5375
0100001
1.1375
1000001
0.7375
1100001
0.3375
0000010
1.5250
0100010
1.1250
1000010
0.7250
1100010
0.3250
0000011
1.5125
0100011
1.1125
1000011
0.7125
1100011
0.3125
0000100
1.5000
0100100
1.1000
1000100
0.7000
1100100
0.3000
0000101
1.4875
0100101
1.0875
1000101
0.6875
1100101
0.2875
0000110
1.4750
0100110
1.0750
1000110
0.6750
1100110
0.2750
0000111
1.4625
0100111
1.0625
1000111
0.6625
1100111
0.2625
0001000
1.4500
0101000
1.0500
1001000
0.6500
1101000
0.2500
0001001
1.4375
0101001
1.0375
1001001
0.6375
1101001
0.2375
0001010
1.4250
0101010
1.0250
1001010
0.6250
1101010
0.2250
0001011
1.4125
0101011
1.0125
1001011
0.6125
1101011
0.2125
0001100
1.4000
0101100
1.0000
1001100
0.6000
1101100
0.2000
0001101
1.3875
0101101
0.9875
1001101
0.5875
1101101
0.1875
0001110
1.3750
0101110
0.9750
1001110
0.5750
1101110
0.1750
0001111
1.3625
0101111
0.9625
1001111
0.5625
1101111
0.1625
0010000
1.3500
0110000
0.9500
1010000
0.5500
1110000
0.1500
0010001
1.3375
0110001
0.9375
1010001
0.5375
1110001
0.1375
0010010
1.3250
0110010
0.9250
1010010
0.5250
1110010
0.1250
0010011
1.3125
0110011
0.9125
1010011
0.5125
1110011
0.1125
0010100
1.3000
0110100
0.9000
1010100
0.5000
1110100
0.1000
0010101
1.2875
0110101
0.8875
1010101
0.4875
1110101
0.0875
0010110
1.2750
0110110
0.8750
1010110
0.4750
1110110
0.0750
0010111
1.2625
0110111
0.8625
1010111
0.4625
1110111
0.0675
0011000
1.2500
0111000
0.8500
1011000
0.4500
1111000
0.0500
0011001
1.2375
0111001
0.8375
1011001
0.4375
1111001
0.0375
0011010
1.2250
0111010
0.8250
1011010
0.4250
1111010
0.0250
0011011
1.2125
0111011
0.8125
1011011
0.4125
1111011
0.0125
0011100
1.2000
0111100
0.8000
1011100
0.4000
1111100
OFF
0011101
1.1875
0111101
0.7875
1011101
0.3875
1111101
OFF
0011110
1.1750
0111110
0.7750
1011110
0.3750
1111110
OFF
0011111
1.1625
0111111
0.7625
1011111
0.3625
1111111
OFF
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8868A-00 May 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
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RT8868A
Table 2. 6-bit VID Code Table for AM2 CPU (Parallel)
VID[5:0]
Voltage
VID[5:0]
Voltage
VID[5:0]
Voltage
VID[5:0]
Voltage
000000
1.5500
010000
1.1500
100000
0.7625
110000
0.5625
000001
1.5250
010001
1.1250
100001
0.7500
110001
0.5500
000010
1.5000
010010
1.1000
100010
0.7375
110010
0.5375
000011
1.4750
010011
1.0750
100011
0.7250
110011
0.5250
000100
1.4500
010100
1.0500
100100
0.7125
110100
0.5125
000101
1.4250
010101
1.0250
100101
0.7000
110101
0.5000
000110
1.4000
010110
1.0000
100110
0.6875
110110
0.4875
000111
1.3750
010111
0.9750
100111
0.6750
110111
0.4750
001000
1.3500
011000
0.9500
101000
0.6625
111000
0.4625
001001
1.3250
011001
0.9250
101001
0.6500
111001
0.4500
001010
1.3000
011010
0.9000
101010
0.6375
111010
0.4375
001011
1.2750
011011
0.8750
101011
0.6250
111011
0.4250
001100
1.2500
011100
0.8500
101100
0.6125
111100
0.4125
001101
1.2250
011101
0.8250
101101
0.6000
111101
0.4000
001110
1.2000
011110
0.8000
101110
0.5875
111110
0.3875
001111
1.1750
011111
0.7750
101111
0.5750
111111
0.3750
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8868A-00 May 2012
RT8868A
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
PWROK
PWROK Input Signal.
2
RT
Connect this Pin to GND by a Resistor to Adjust Frequency.
3
FBRTN
Remote Sense Ground for CORE.
4
FBRTN_NB
Remote Sense Ground for NB.
5
FB_NB
Inverting Input of Error-Amp for NB.
6
COMP_NB
Output of Error-Amp and Input of PWM Comparator for NB.
7
ISP_NB
Positive Current Sense Pin of NB.
8
ISN_NB
Negative Current Sense Pin of NB.
9
ADJ
10
OFS
11
12
COMP
FB
Connect this Pin to GND by a Resistor to set Load Line of
VCORE.
Connect this Pin to 5VCC by a Resistor to set No-Load Offset
Voltage of VCORE.
Output of Error-Amp and Input of PWM Comparator of VCORE .
Inverting Input of Error-Amp of VCORE.
13
IMAX_NB
14
IMAX
15, 17, 19, 21 ISN1, ISN2, ISN3, ISN4
Connect this Pin to GND by a Resistor to set OCP of NB.
Connect this Pin to GND by a Resistor to set OCP of VCORE.
Negative Current Sense Pin of Channel 1, 2, 3 and 4.
16, 18, 20, 22 ISP1, ISP2, ISP3, ISP4
Positive Current Sense Pin of Channel 1, 2, 3 and 4.
23
PS
PWM4, PWM3
Power Saving Mode Selection Pin.
Output of Internal 5V Regulator for Control Circuits Power
Supply. Connect this Pin to GND by a Ceramic Capacitor Larger
than 1μF.
PWM Output for Channel 4 and Channel 3.
24
VCC5
27, 35, 36
BOOT2, BOOT1, BOOT_NB
Bootstrap Supply for Channel 2 and Channel 1 and NB.
28, 34, 37
UGATE2, UGATE1, UGATE_NB Upper Gate Driver for Channel 2 and Channel 1 and NB.
29, 33, 38
PHASE2, PHASE1, PHASE_NB Switching Node of Channel 2 and Channel 1 and NB.
30, 32, 39
LGATE2, LGATE1, LGATE_NB
Lower Gate Driver for Channel 2 and Channel 1 and NB.
VCC12, VCC12_NB
25,26
31, 40
41
VID0/VFIXEN
42
VID1/PVI
43
VID2/SVD
44
VID3/SVC
45, 46
VID4, VID5
IC Power Supply. Connect this pin to 12V.
PVI Mode : Used as Voltage Identification Input for DAC.
SVI Mode : Functions as VFIXEN Selection Input.
This Pin Selects PVI/SVI Mode Based on the State of this Pin
Prior to EN Signal.
PVI Mode : Used as Voltage Identification Input for DAC.
PVI Mode : Used as Voltage Identification Input for DAC.
SVI Mode : Serial Data Input.
PVI Mode : Used as Voltage Identification Input for DAC.
SVI Mode : Serial Clock Input.
PVI Mode : Used as Voltage Identification Input for DAC.
47
PGOOD
Power Good Indicator (open drain).
48
EN
Enable Input Signal.
Reference Ground for the IC. The exposed pad must be
soldered to a large PCB and connected to GND for maximum
power dissipation.
49
GND
(Exposed pad)
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8868A-00 May 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
5
RT8868A
Function Block Diagram
RAMP_NB
Modulator
Waveform
Generator
RT
VCC12
Power-On
Reset
POR
COMP
FB
5V
Regulator
VCC5
EA
+
BOOT1
Offset
OFS
UGATE1
MOSFET
Driver
+
PHASE1
+
-
LGATE1
OV
+
1.8V
BOOT2
+
MOSFET
Driver
-
Transient
Response
Enhancement
PWM3
-
PGOOD
PWROK
EN
Soft Start
and
Fault
Logic
CH3_EN
Detector
+
PWM4
-
CH4_EN
Detector
PS
+
-
I_SEN1
+
+
-
1.25V
FBRTN_NB
+
VID
Table
Generator
-
-
-
I_SEN3
+
OC
Detection
OC
+
-
OC_NB
Detection
IMAX_NB
CH1
Current
SENSE
CH2
Current
SENSE
ISP1
ISN1
ISP2
ISN2
AVG
ADJ
IMAX
I_SEN2
+
VID5 to VID0
FBRTN
PHASE2
LGATE2
+
OV
OC
VIDOFF
POR
UGATE2
I_SEN4
OC_NB
I_SENNB
Transient
Response
Enhancement
CH3
Current
SENSE
ISP3
ISN3
CH4
Current
SENSE
ISP4
NB
Current
SENSE
ISP_NB
ISN4
ISN_NB
VCC12_NB
COMP_NB
BOOT_NB
FB_NB
+
+
-
EA
+
OV_NB
+
RAMP_NB
-
MOSFET
Driver
UGATE_NB
PHASE_NB
LGATE_NB
1.8V
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8868A-00 May 2012
RT8868A
Absolute Maximum Ratings
z
z
z
z
z
z
z
z
z
z
z
z
(Note 1)
Supply Input Voltage --------------------------------------------------------------------------------- −0.3V to 15V
BOOTx to PHASEx ---------------------------------------------------------------------------------- −0.3V to 15V
PHASEx to GND
DC -------------------------------------------------------------------------------------------------------- −2V to 15V
<20ns --------------------------------------------------------------------------------------------------- −5V to 30V
UGATEx to GND
DC -------------------------------------------------------------------------------------------------------- (VPHASE − 0.3V) to (VBOOT + 0.3V)
<20ns --------------------------------------------------------------------------------------------------- (VPHASE − 5V) to (VBOOT + 5V)
LGATEx to GND
DC -------------------------------------------------------------------------------------------------------- (GND − 0.3V) to (VCC + 0.3V)
<20ns --------------------------------------------------------------------------------------------------- (GND − 5V) to (VCC + 5V)
Input/Output Voltage or I/O Voltage -------------------------------------------------------------- −0.3V to 7V
Power Dissipation, PD @ TA = 25°C
WQFN−48L 7x7 --------------------------------------------------------------------------------------- 3.226W
Package Thermal Resistance (Note 2)
WQFN-48L 7x7, θJA ---------------------------------------------------------------------------------- 31°C/W
WQFN-48L 7x7, θJC --------------------------------------------------------------------------------- 6°C/W
Junction Temperature -------------------------------------------------------------------------------- 150°C
Lead Temperature (Soldering, 10 sec.) ---------------------------------------------------------- 260°C
Storage Temperature Range ----------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Model) ------------------------------------------------------------------------- 2kV
Recommended Operating Conditions
z
z
z
(Note 4)
Supply Voltage, VCC12 ----------------------------------------------------------------------------- 12V ± 10%
Junction Temperature Range ----------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ----------------------------------------------------------------------- − 40°C to 85°C
Electrical Characteristics
(VVCC12 = 12V, GND = 0V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VCC Supply Input
VCC12 Supply Voltage
VVCC12
10.8
12
13.2
V
VCC12 Supply Current
IVCC12
--
10
--
mA
VCC12_NB Supply Voltage
VVCC12_NB
10.8
12
13.2
V
VCC12_NB Supply Current
IVCC12_NB
--
5
--
mA
4.9
5
5.1
V
10
--
--
mA
VCC5 Power
VCC5 Supply Voltage
VVCC5
VCC5 Output Sourcing
IVCC5
ILOAD = 10mA
Power On Reset
VCC12 Rising Threshold
VVCC12TH
VCC12 Rising
9.4
9.8
10.2
V
VCC12 Hysteresis
VVCC12HY
VCC12 Falling
--
0.9
--
V
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8868A-00 May 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
7
RT8868A
Parameter
Input Threshold
Symbol
Test Conditions
Min
Typ
Max
2
-2
--
-----
-0.8
-0.8
Unit
Logic-High
Enable Input
Threshold Voltage Logic-Low
Logic-High
PWROK Input
Threshold Voltage Logic-Low
VENHI
VENLO
VPOKHI
VPOKLO
EN Rising
EN Falling
PWROK Rising
PWROK Falling
VID5 to VID0 Rising Threshold
VVID5 to 0
VID5 to VID0 Rising
0.75
0.8
0.85
V
VID5 to VID0 Hysteresis
VID5 to VID0 Pull-Down
Current
Reference Voltage Accuracy
V VID5 to 0 HYS
VID5 to VID0 Falling
--
25
--
mV
IVID5 to 0
VVID5 to 0 = 1.5V
--
16
30
μA
1V to 1.55V
−0.5
--
0.5
%
0.8V to 1V
−8
--
8
mV
0.5V to 0.8V
−10
--
10
mV
DAC Accuracy
V
V
Error Amplifier
DC Gain
ADC
No Load
--
80
--
dB
Gain-Bandwidth
GBW
CLOAD = 10pF
--
10
--
MHz
Slew Rate
SR
CLOAD = 10pF
10
--
--
V/μs
Output Voltage Range
VCOMP
RLOAD = 47kΩ
0.5
--
3.6
V
Over Voltage Threshold
VPGOOD-OV
FB Rising
VDAC
V DAC
V DAC
+210mV +240mV +270mV
V
Under Voltage Threshold
VPGOOD-UV
FB Falling
V DAC
V DAC
VDAC
−330mV −300mV −270mV
V
Over Voltage Threshold_NB
VPGOOD-OV_NB FB_NB Rising
Under Voltage Threshold_NB
VPGOOD-UV_NB FB_NB Falling
Power Good Low Voltage
VPGOOD
Power Good
VDAC
V DAC
V DAC
V
+210mV +240mV +270mV
IPGOOD = 4mA
VDAC
V DAC
V DAC
V
−330mV −300mV −270mV
--
--
0.4
V
100
--
--
μA
−2
0
2
mV
270
300
330
kHz
--
1.6
--
V
Current Sense Amplifier
Max Current
IGMMAX
Input Offset Voltage
VOSCS
VCSP = 1.3V
Sink Current from CSN
Oscillator
Running Frequency
fOSC
Ramp Amplitude
VRAMP
RRT = 40kΩ
Soft-Start
Soft-Start Slew Rate
SRSS
Slew Rate
2.5
3.25
4
mV/μs
VID change Slew Rate
SRVID
Slew Rate
2.5
3.25
4
mV/μs
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8868A-00 May 2012
RT8868A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Protection
VOVP
Sweep FB Voltage
1.7
1.8
1.9
V
VOVP_NB
Sweep FB_NB Voltage
1.7
1.8
1.9
V
IOCP
RIMAX = 40kΩ
64.5
83
101.5
μA
VIMAX
RIMAX = 40kΩ
1.44
1.6
1.76
V
IOCP_NB
RIMAX_NB = 40kΩ
64.5
83
101.5
μA
VIMAX_NB
RIMAX_NB = 40kΩ
1.44
1.6
1.76
V
UGATE Drive Source
RUGATEsr
VBOOT − VPHASE = 8V
250mA Source Current
--
1
--
Ω
UGATE Drive Sink
RUGATEsk
VBOOT − VPHASE = 8V
250mA Sink Current
--
1
--
Ω
LGATE Drive Source
RLGATEsr
VLGATE = 8V
--
1
--
Ω
LGATE Drive Sink
RLGATEsk
250mA Sink Current
--
0.9
--
Ω
Over Voltage Threshold
Over-Current Threshold
Gate Driver
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8868A-00 May 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
9
RT8868A
Typical Operating Characteristics
Power Off from EN_CORE
Power On from EN_CORE
VCCP_CORE
(1V/Div)
VCCP_CORE
(1V/Div)
EN
(2V/Div)
PGOOD
(2V/Div)
EN
(2V/Div)
PGOOD
(2V/Div)
UGATE1
(20V/Div)
UGATE1
(20V/Div)
VID = 1.1V, ILOAD = 6A
Time (200μs/Div)
Time (200μs/Div)
Power On from EN_NB
Power Off from EN_NB
V CCP_NB
(1V/Div)
V CCP_NB
(1V/Div)
EN
(2V/Div)
PGOOD
(1V/Div)
EN
(2V/Div)
PGOOD
(1V/Div)
UGATE_NB
(20V/Div)
UGATE_NB
(20V/Div)
VID = 1.1V, ILOAD = 6A
VID = 1.1V, ILOAD = 6A
Time (200μs/Div)
Time (200μs/Div)
Power On from EN_SVI Mode
Power Off from EN_SVI Mode
VCCP_CORE
(1V/Div)
VCCP_CORE
(1V/Div)
V CCP_NB
(1V/Div)
V CCP_NB
(1V/Div)
EN
(2V/Div)
PGOOD
(2V/Div)
EN
(2V/Div)
VID = 1.1V, ILOAD = 6A
Time (200μs/Div)
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10
VID = 1.1V, ILOAD = 6A
PGOOD
(2V/Div)
VID = 1.1V, ILOAD = 6A
Time (200μs/Div)
is a registered trademark of Richtek Technology Corporation.
DS8868A-00 May 2012
RT8868A
Dynamic VID Down
Dynamic VID Up
VCCP_NB
(1V/Div)
V CCP_NB
(1V/Div)
VCCP_CORE
(1V/Div)
V CCP_CORE
(1V/Div)
SVC
(2V/Div)
SVC
(2V/Div)
SVD
(2V/Div)
SVD
(2V/Div)
Time (40μs/Div)
Time (40μs/Div)
Over Voltage Protection_CORE
Over Voltage Protection_NB
VID = 0.8V, Increase COMP
Voltage to Trigger OVP
VID = 0.8V, Increase COMP_NB
Voltage to Trigger OVP
FB
(1V/Div)
FB_NB
(1V/Div)
LGATE1
(10V/Div)
LGATE_NB
(10V/Div)
UGATE1
(20V/Div)
UGATE_NB
(20V/Div)
Time (40μs/Div)
Time (40μs/Div)
Over Current Protection_CORE
Over Current Protection_NB
VCCP_CORE
(1V/Div)
V CCP_NB
(1V/Div)
PGOOD
(1V/Div)
PGOOD
(1V/Div)
UGATE1
(20V/Div)
UGATE_NB
(20V/Div)
I LOAD
(50A/Div)
I LOAD
(20A/Div)
Time (100μs/Div)
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8868A-00 May 2012
Time (100μs/Div)
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
11
RT8868A
Load Transient Response_CORE
V CCP_CORE
(100mV/Div)
V CCP_CORE
(100mV/Div)
Load Transient Response_CORE
1.1V ->
1.1V ->
90A
90A
I LOAD
I LOAD
30A
30A
ILOAD = 30A to 90A
Time (20μs/Div)
Load Transient Response_NB
Load Transient Response_NB
V CCP_NB
(100mV/Div)
V CCP_NB
(100mV/Div)
Time (20μs/Div)
1.1V ->
I LOAD
20A
5A
1.1V ->
20A
I LOAD 5A
ILOAD = 5A to 20A
Time (20μs/Div)
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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12
ILOAD = 90A to 30A
ILOAD = 20A to 5A
Time (20μs/Div)
is a registered trademark of Richtek Technology Corporation.
DS8868A-00 May 2012
RT8868A
Application Information
The RT8868A is a dual output PWM controller that supports
hybrid power control of AMD processors which operate
from either a 6-bit Parallel VID Interface (PVI) or a Serial
VID Interface (SVI). One of the outputs is a 4/3/2/1-phase
PWM controller with two integrated MOSFET drivers to
support CPU core voltage (VDD) and another is a singlephase buck controller with an integrated MOSFET driver
to power North-Bridge (NB) chipset (VDDNB) in SVI mode.
In PVI mode, only multiphase PWM controller is active
for single plane VDD only processor.
TM
Richtek's proprietary Burst Transient Response(BTR )
provides fast initial response to high di/dt load transients
and requires less bulk and ceramic output capacitance to
meet transient regulation specifications. The RT8868A
incorporates differential voltage sensing, continuous
inductor DCR phase current sensing, programmable loadline voltage positioning and offset voltage to provide high
accuracy regulated power for both VDD and VDDNB. While
VDDNB is enabled in SVI mode, it will be automatically
phase-shifted with respect to the CPU Core phases in
order to reduce the total input RMS current amount.
CPU_TYPE Detection and System Start-Up
At system start-up, on the rising-edge of EN signal, the
RT8868A monitors the status of VID1 and latches the PVI
mode (VID1 = 1) or SVI mode (VID1 = 0).
PVI Mode
PVI is a 6-bit-wide parallel interface used to address the
CPU Core section reference. According to the selected
code, the device sets the Core section reference and
regulates its output voltage according to Table 2. In this
mode, NB section is kept in high impedance. Furthermore,
PWROK information is ignored as well since the signal
only applies to the SVI protocol.
SVI Mode
SVI wire protocol is based on fast-mode I2C as shown in
Figure 1. SVI interface also considers two additional
signals needed to manage the system start-up. These
signals are EN and PWROK. The device asserts a PGOOD
signal if the output voltages are in regulation.
Start
Slave Addressing + W
6
SVC
5
4
3
ACK
0
Data Phase
7
6
ACK
SVD
ACK
Stop
0
ACK
110b
Start
Slave Addressing
(7 Clocks)
BUS Driven by
RT8868A
Write ACK
(1Ck) (1Ck)
Data Phase
(8 Clocks)
ACK
(1Ck)
Stop
BUS Driven by Master (CPU)
Figure 1. SVI Communication-Send Byte
Set VID Command
The Set VID Command is defined as the command
sequence that the CPU issues on the SVI bus to modify
the voltage level of the Core section and NB section, as
shown is Figure 1. During a Set VID Command, the
processor sends the start (Start) sequence followed by
the address of the Section which the Set VID Command
applies. The processor then sends the write (WRITE) bit.
After the write bit, the Voltage Regulator (VR) sends the
acknowledge (ACK) bit. The processor then sends the
VID bits code during the data phase. The VR sends the
acknowledge (ACK) bit after the data phase. Finally, the
processor sends the stop (Stop) sequence. After the VR
has detected the stop, it performs an On-the-Fly VID
transition for the addressed section(s). Refer to Table 3
for the details of SVI send byte.
The RT8868A is able to manage individual power off for
both VCORE and NB sections. The CPU may issue a
serial VID command to power off or power on one section
while the other one remains powered. In this case, the
PGOOD signal remains asserted.
SVI is a two wire, Clock and Data, bus that connects a
single master (CPU) to one slave (RT8868A). The master
initiates and terminates SVI transactions and drives the
clock, SVC, and the data, SVD, during a transaction. The
slave receives the SVI transactions and acts accordingly.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8868A-00 May 2012
is a registered trademark of Richtek Technology Corporation.
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13
RT8868A
Table 3. SVI Send Byte-Address and Data Phase
Description / Example
bits
Description
Address Phase
6 : 4 Always 110b
3
Not Applicable, ignored.
2
Not Applicable, ignored.
CORE Section. (Note)
If set then the following data byte contains the
VID code for CORE Section.
NB Section. (Note)
If set then the following data byte contains the
VID code for NB Section.
Data Phase
PSI_L Flag (Active Low). When asserted, the
VR is allowed to enter Power-Saving Mode.
VID Code.
1
0
7
6:0
Note : Assertion in both bit 1 and 0 will address the VID
code to both CORE and NB simultaneously.
Example :
SVI Address
Bits [6 : 0]
1100_000
Should be ignored.
1100_001
Set VID on VDDNB.
1100_110
Set VID on VDD0 and VDD1.
1100_100
Set VID on VDD1.
1100_010
Set VID on VDD0 or VDD (Uniplane).
Set VID on VDDNB, VDD0 and
VDD1.
1100_111
Description
PWROK De-assertion
PWROK stays low after EN signal is asserted, and the
controller regulates all the planes according to the PrePWROK Metal VID.
PGOOD is de-asserted as long as Pre-PWROK Metal VID
voltage is out of the initial voltage specifications.
V_FIX Mode Function
Anytime the pin VID0/VFIXEN is pulled high, the controller
enters V-FIX mode. When in V_FIX mode, both VCORE
and NB section voltages are governed by the information
shown in Table 4. Regardless of the state of PWROK, the
device will work in SVI mode. SVC and SVD are considered
as static VID and the output voltage will be changed
according to their status. Dynamic SVC/SVD-change
management is provided in this condition. V_FIX mode is
intended for system debug only.
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14
Table 4. V_FIX Mode and Pre-PWROK Metal VID
SVC
SVD
0
0
1
1
0
1
0
1
Output Voltage (V)
Pre-PWROK
V_FIX Mode
Metal VID
1.1V
1.4V
1.0V
1.2V
0.9V
1.0V
0.8V
0.8V
Power Ready Detection
During start-up, the RT8868A will detect VCC12, VCC5
and EN signal. Figure 2 shows the power ready detection
circuit. When VCC12 > 9.6V and VCC5 > 4.6V, POR
(Power On Reset) will go high. POR is the internal signal
to indicate all input powers are ready to allow the RT8868A
and the companioned MOSFET drivers to work properly.
When POR = L, the RT8868A will turn off both high side
and low side MOSFETs.
VCC12
+
9.6V
VCC5
+
4.6V
CMP
CMP
-
EN
POR
Chip Enable
Figure 2. Circuit for Power Ready Detection
Power-Up Sequencing
Figure 3 and 4 are the power-up sequencing diagram of
the RT8868A. Once power_on_reset is valid (POR = H),
on the rising edge of the EN signal, the RT8868A detects
the VID1 pin and determines whether to operate in SVI or
PVI mode. Figure3 shows the PVI-mode power sequence,
the controller stays in T1 state waiting for valid parallel
VID code sent by CPU. After receiving valid parallel VID
code, VCORE continues ramping up to the specified
voltage according to the VID code in T2 state. Figure 4
shows the SVI-mode power sequence, the controller
samples the two serial VID pins, SVC and SVD. Then,
the controller stores this value as the boot VID that is the
so-called “Pre-PWROK Metal VID” in T1 state. After the
processor starts with boot VID voltages, PWROK is
asserted and the processor initializes the serial VID
interface in T2 state. The processor uses the serial VID
interface to issue VID commands to move the power planes
from the boot VID values to the dual power planes in T3
state.
is a registered trademark of Richtek Technology Corporation.
DS8868A-00 May 2012
RT8868A
VCC12 9.6V
VCC5 4.6V
8.7V
L
DCR
RS
CS
4.2V
POR
CSA: Current Sense Amplifier
EN
VID(1)/PVI xx
PVI mode
(6-bits)
xx
+
235nA
Valid
VOFS_CSA
IX
+
-
235nA
ISP
RCSP
ISN
RCSN
VDD
PGOOD
PWROK
Figure 5. Current Sensing Circuit
T2
T1
CORE Section Phase Detection
Figure 3. PVI-Mode Power-sequencing Diagram
VCC12 9.6V
VCC5 4.6V
8.7V
4.2V
POR
EN
VID(1)/PVI xx
SVC
SVD
xx
xx
Valid
Valid
Vboot
VDD or
VDDNB
PGOOD
PWROK
T1
T2
T3
Figure 4. SVI-Mode Power-sequencing Diagram
The number of the operational phases is determined by
the internal circuitry that monitors the ISNx voltages during
start up. Normally, the RT8868A operates as a 4-phase
PWM controller. Pull ISN4 and ISP4 to 5VCC programs
3-phase operation, pull ISN3 and ISP3 to 5VCC programs
2-phase operation, and pull ISN2 and ISP2 to 5VCC
programs 1-phase operation. The RT8868A detects the
voltage of ISN4, ISN3 and ISN2 at rising edge of POR. At
the rising edge, the RT8868A detects whether the voltage
of ISN4, ISN3 and ISN2 are higher than “VCC5-1V”
respectively to decide how many phases should be active.
Phase detection is only active during start up. Once POR
= high, the number of operational phases is determined
and latched.
CORE Section Output Current Sensing
Amplifier (CSA) to monitor the continuous output current
of each phase for VCORE. Output current of CSA (IX[n]) is
used for current balance and active voltage position as
shown in Figure 5. In this inductor current sensing topology,
RS and CS must be set according to the equation below :
L = R ×C
S
S
DCR
Then the output current of CSA will follow the equation
below :
[I × DCR − VOFS-CSA + 235nA × (RCSP − RCSN )]
IX = L
RCSN
235nA is the typical value of the CSA input offset current.
VOFS-CSA is the input offset. Usually, “VOFS-CSA + 235nA x
(RCSP − RCSN)” is negligible except at very light load and
the equation can be simplified as the equation below :
I × DCR
IX = L
RCSN
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8868A-00 May 2012
CORE Section Switching Frequency
Connecting a resistor (RRT) from the RT pin to GND
programs the switching frequency of each phase. Figure
6 shows the relationship between the resistance and
switching frequency.
1200
1000
Frequency (kHz)
The RT8868A provides a low input offset Current Sense
800
600
400
200
0
0
40
80
120
160
200
240
280
RRT (k
ohm)
(kΩ)
Figure 6. RRT vs. Phase switching Frequency
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15
RT8868A
CORE Section Differential Output Voltage Sensing
The RT8868A uses differential voltage sensing by a high
gain low offset error-amp as shown in Figure 7. Connect
the negative on-die CPU remote sense pin to FBRTN.
Connect the positive on-die remote sense pin to FB with
a resistor (R FB ) The error-amp compares EAP
( = VDAC − VADJ) with VFB to regulate the output voltage.
C2
CFB
RFB
VCCP
(Positive remote
sense pin of CPU)
(Negative remote
sense pin of CPU)
VCCN
RADJ
R1
FB
-
IOFSP
+
VDAC
+-
+
EA
C1
COMP
EAP
-
FBRTN
ADJ
Figure 7. Circuit for VCORE Differential Sensing and No
Load Offest
CORE Section No-Load Offset
In Figure 7, IOFSP is used to generate no-load offset.
Connect a resistor from OFS pin to 5VCC to activate IOFSP.
IOFSP flows through RFB from the VCCP to FB pin. In this
case, positive no-load offset voltage (VOFSP) is generated.
Besides IOFSP, the RT8868A generates another DC current
for initial no-load negative offset. A DC current source will
continuously inject typical 9μA current into the resistors
connected to ADJ pin, Therefore, the effect of this 9μA
current source and ADJ resistors should be included in
the calculation of no-load offset :
VOFSP = IOFSP × RFB − 9μ × R ADJ
R
= 0.4 × FB − 9μ × R ADJ
ROFS
CORE Section Programmable Load-line
Output current of CSA is summed and averaged in the
RT8868A. Then 0.5Σ (IX[n]) is sent to ADJ pin. Because
Σ IX[n] is a PTC (Positive Temperature Coefficient) current,
an NTC (Negative Temperature Coefficient) resistor is
needed to connect ADJ pin to GND. If the NTC resistor is
properly selected to compensate the temperature
coefficient of I X[n], the voltage on ADJ pin will be
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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16
proportional to IOUT without temperature effect. In the
RT8868A, the positive input of error-amp is “VDAC − VADJ”.
VOUT will follow “VDAC − VADJ” , too. Thus, the output
voltage which decreases linearly with IOUT is obtained. The
loadline is defined as :
R
ΔVOUT ΔVADJ 1
LL(loadline) =
=
= × DCR × ADJ
ΔIOUT
ΔIOUT 2
RCSN
Briefly, the resistance of RADJ sets the resistance of
loadline. The temperature coefficient of RADJ compensates
the temperature effect of loadline.
CORE Section Load Transient Quick Response
In steady state, the value of VFB is controlled to be very
close to VEAP. However, a load step transient from light
load to heavy load can still cause VFB to become lower
than VEAP by several tens of mV. In prior design, owing to
limited control bandwidth, it is difficult for the controller to
prevent VOUT undershoot during quick load transient from
light load to heavy load. The RT8868A has a built-in
proprietary Burst Transient Response (BTRTM ) technology
that detects load transient by comparing VFB and VEAP. If
VFB suddenly drops below “VEAP − V QR” (VQR is a
predetermined voltage), the quick response indicator QR
rises up. When QR = high, the RT8868A turns on all high
side MOSFETs and turns off all low side MOSFETs. The
sensitivity of quick response can be adjusted by the values
of CFB and RFB. Smaller RFB and/or larger CFB will make
QR easier to be triggered. Figure 8 illustrates the circuit
and typical waveforms.
VOUT
CFB
C2
RFB
R1 C1
FB
EAP = VDAC - VADJ
IOUT
VOUT
FB
COMP
-
-
+
+
FB
QR
= VEAP
= VEAP - VQR
EAP - VQR
QR
Figure 8. Load Transient Quick Response
CORE Section Current Balance
In Figure 9, IX[n] is the current signal which is proportional
to the current flowing through channel n. The current error
signals IERR[n] ( = I X [n] − AVG(I X [n])) are used to raise or
lower the valley of internal sawtooth waveforms (EAMP[1]
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DS8868A-00 May 2012
RT8868A
to RAMP[n]) which is compared with error-amp output
(COMP) to generate PWM signal. Raising the valley of
sawtooth waveform will decrease the PWM duty of the
corresponding channel, while lowering the sawtooth
waveform valley will increase the PWM duty. Eventually,
the current flowing through each channel will be balanced.
CORE Section Over Current Protection (OCP)
VIN
ILX
PWM
Controller
LS
RAMP[n]
+
CMP
-
-
BUF
1.6V
+
CMP
-
-
CX
BUF
1/8IX
1/4IIMAX
PWM[1]
IERR [1] x R CB
+
RX
+
-
Interleaved
+
DCRX
OCP Comparator
COMP
RAMP[1]
HS L
X
+
-
PWM[n]
4
+
GM
-
RCSNX
IIMAX
VIMAX
IERR [n] x R CB
8
RIMAX
IX
RT8868A CORE section
Figure 9. Circuit Channel Current Balance
CORE Section Phase Current Adjustment
If phase current is not balanced due to asymmetric PCB
layout of power stage, external resistors can be adjusted
to correct current imbalance. Figure10 shows two types
of current imbalance, constant ratio type and constant
difference type. If the initial current distribution is constant
ratio type, according to Equation (3), reducing RCSN[1]
can reduce IL[1] and improve current balance. If the initial
current distribution is constant difference type, according
to Equation (2), increasing RCSP[1] can reduce IL[1] and
improve current balance.
I1
I2
IOUT , total
Constant ratio
I1
I2
IOUT , total
Constant difference
Figure 10. Category of Phase Current Imbalance
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8868A-00 May 2012
Figure 11. Over Current Protection for CORE Section
CORE section uses an external resistor RIMAX connected
to IMAX pin to generate a reference current IMAX for over
current protection as depicted in Figure 11.
IIMAX =
VIMAX
RIMAX
where VIMAX is typically 1.6V. The RT8868A senses each
phase current IX and the OCP comparator compares
sensed average current with the reference current.
Equivalently, the maximum phase average current ILX(MAX)
is calculated as below :
1 ×I
1
IMAX = × IX(MAX)
4
8
V
IX(MAX) = 2 × IIMAX = 2 × IMAX
RIMAX
R
R
V
ILX(MAX) = IX(MAX) × CSNX = 2 × IMAX × CSNX
DCR X
RIMAX DCR X
Once IX is larger than 2 x IIMAX, the OCP of CORE section
is triggered and latched. Then, the RT8868A will turn off
both high side MOSFET and low side MOSFET of all
channels. A 100μs delay is used in OCP detection circuit
to prevent false trigger.
Except the normal OCP function described above, there
is another short circuit OCP function especially designed
for short circuit protection. Since short circuit may cause
catastrophic damage over a very short period, the short
circuit OCP should have a very short delay for triggering
OCP latch. Also to prevent false trigger, the trigger level
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RT8868A
of the short circuit OCP is designed 1.5 times of normal
OCP level. Hence, the equation of short circuit OCP
threshold is :
R
V
ILX(MAX), short = 1.5 x ILX(MAX) = 3 × IMAX × CSNX ,
RIMAX DCR X
and the delay of short circuit OCP is 20μs. When short
circuit OCP is triggered, the RT8868A will turn off both
high side MOSFET and low side MOSFET of all channels.
CORE Section Over Voltage Protection (OVP)
The over voltage protection monitors the output voltage
via the FB pin. Once VFB exceeds 1.8V, OVP is triggered
and latched for VCORE section. RT8868A will try to turn
on each low side MOSFET and turn off each high side
MOSFET to protect CPU.
The RT8868A provides low input offset Current Sense
Amplifier (CSA) to monitor the continuous output current
of NB section. Output current of CSA (IX_NB) is used for
over current detection as shown in Figure 12. In this
inductor current sensing topology, RS_NB and CS_NB must
be set according to the equation below :
LNB
= RS_NB × CS_NB
DCRNB
Then the output current of CSA will follow the equation
below :
IL_NB × DCRNB
IX_NB =
RCSN_NB
R S_NB
DCR NB
C S_NB
CSA: Current Sense Amplifier
IX_NB
+
R CSN_NB
-
Figure 12. Current Sensing Circuit for NB Section
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18
NB section uses an external resistor RIMAX_NB connected
to IMAX_NB pin to generate a reference current IMAX_NB
for over current protection as depicted in Figure 13.
VIMAX_NB
IIMAX_NB =
RIMAX_NB
where VIMAX_NB is typically 1.6V. The OCP comparator
compares the sensed phase current IX_NB with the reference
current. Equivalently, the maximum phase NB current
ILX_NB(MAX) is calculated as below :
1 ×I
1
IMAX_NB = × IX_NB
4
8
IX_NB = 2 × IIMAX_NB = 2 ×
VIMAX_NB
RIMAX_NB
RCSN_NB
DCRNB
VIMAX_NB RCSN_NB
= 2×
×
RIMAX_NB DCRNB
ILX_NB(MAX) = IX_NB ×
NB Section Output Current Sensing
L NB
NB Section Over Current Protection (OCP)
Once IX_NB is larger than 2 x IIMAX_NB, OCP of NB section
is triggered and latched. Then, the RT8868A will turn off
both high side MOSFET and low side MOSFET of NB
section. A 100μs delay is used in OCP detection circuit
to prevent false trigger.
Except the normal OCP function described above, there
is another short circuit OCP function especially designed
for short circuit protection. Since short circuit may cause
catastrophic damage over a very short period, the short
circuit OCP should have a very short delay for triggering
OCP latch. Also to prevent false trigger, the trigger level
of the short circuit OCP is designed 1.5 times of normal
OCP level of NB section. Hence, the equation of NB
section short circuit OCP threshold is :
ILX_NB(MAX), short = 1.5 x ILX_NB(MAX)
= 3×
VIMAX_NB RCSN_NB
×
,
RIMAX_NB DCRNB
and the delay of short circuit OCP of NB section is 20μs.
When short circuit OCP is triggered at NB section, the
RT8868A will turn off both high side MOSFET and low
side MOSFET of NB section.
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RT8868A
VIN
5VCC
HS
ILX
PSOC2P
LX_NB DCR
NB
PWM
Controller
(1) 5VCC for (4 phase to 2 phase)
(2) 3.3V for (4 phase to 1 phase)
Latch
VDDIO
EN
LS
OCP Comparator
RX_NB CX_NB
1.6V
+
-
4
PS
Control
+
-
1/8IX_NB
1/4IIMAX_NB
PSIA
+
GM
-
8
IIMAX_NB
RCSN_NB
IX_NB
Figure 14. Power-Saving-Mode Circuit
VIMAX_NB
Table 5. PSI Strategy
RT8868A NB section
RIMAX_NB
Figure 13. Over Current Protection for NB Section
NB Section Over Voltage Protection (OVP)
The over voltage protection monitors the output voltage
via the FB_NB pin. Once VFB_NB exceeds 1.8V, OVP is
triggered and latched for NB section. The RT8868A will
try to turn on low side MOSFET and turn off high side
MOSFET to protect NB.
Power Saving Indicator (PSI)
This is an active low flag that can be set by the CPU to
allow the regulator to enter Power-Saving mode to
maximize the system efficiency when in light-load
conditions. The status of the flag is communicated to the
controller through either the SVI bus or PS pin. The
RT8868A monitors the PS pin to define the action
performed by the controller when PSI is asserted.
According to Figure 14, by programming different voltage
on PS pin, this configures the controller to operate in one
or two-phase condition when PSI is asserted. By pulling
up PS pin to 3.3V through a resistor, the controller
operates in only one-phase configuration. If the 3.3V is
changed to 5V, the RT8868A operates in two-phase
configuration. When PSI is de-asserted, the controller will
return to the original configuration. The PSI strategy is
summarized as shown in Table 5.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8868A-00 May 2012
PSI
(Active Low)
PSI
(From I2C)
PS pin
Pull-Up to 3.3V
Pull-Up to 5V
PSI Strategy
Phase number is set to 1 while
PSI is asserted.
Phase number is set to 2 while
PSI is asserted.
Non-overlap Control of MOSFET Driver
To prevent the overlap of the gate drives during the UGATE
pull low and the LGATE pull high, the non-overlap circuit
monitors the voltages at the PHASE node and high side
gate drive (UGATE-PHASE). When the PWM input signal
goes low, UGATE begins to pull low (after propagation
delay). Before LGATE can pull high, the non-overlap
protection circuit ensures that the monitored voltages have
gone below 1.1V. Once the monitored voltages fall below
1.1V, LGATE begins to turn high. By waiting for the
voltages of the PHASE pin and high side gate drive to fall
below 1.1V, the non-overlap protection circuit ensures that
UGATE is low before LGATE pulls high.
Also to prevent the overlap of the gate drives during LGATE
pull low and UGATE pull high, the non-overlap circuit
monitors the LGATE voltage. When LGATE go below 1.1V,
UGATE goes high after propagation delay.
Layout Considerations
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. The high power
switching power stage requires particular attention. Follow
these guidelines for optimum PCB layout.
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RT8868A
When placing the MOSFETs, try to keep the source of
the upper MOSFETs and the drain of the lower MOSFETs
as close to each other as possible. Input bulk capacitors
should be placed close to the drain of the upper MOSFETs
and the source of the lower MOSFETs.
Locate the output inductors and output capacitors between
the MOSFETs and the load. Route high-speed switching
nodes away from sensitive analog areas (ISP, ISN, FB,
FBRTN, COMP, ADJ, OFS, IMAX.....)
Keep the routing of the bootstrap capacitor short between
BOOT and PHASE.
Place the snubber R&C as close as possible to the lower
MOSFETs of each phase.
Thermal Considerations
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WQFN-48L 7x7 package, the thermal resistance, θJA, is
31°C/W on a standard JEDEC 51-7 four-layer thermal test
board. The maximum power dissipation at TA = 25°C can
be calculated by the following formula :
PD(MAX) = (125°C − 25°C) / (31°C/W) = 3.226W for
WQFN-48L 7x7 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 15 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Maximum Power Dissipation (W)1
Place the power components first, including power
MOSFETs, input and output capacitors, and inductors. It
is important to have a symmetrical layout for each power
train, preferably with the controller located equidistant from
each. Symmetrical layout allows heat to be dissipated
equally across all power trains. Great attention should be
paid for routing the UGATE, LGATE, and PHASE traces
since they drive the power train MOSFETs with short,
high current pulses. It is important to size them as large
and short as possible to reduce their overall impedance
and inductance. Extra care should be given to the LGATE
traces in particular since keeping their impedance and
inductance low helps to significantly reduce the possibility
of shoot through.
3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
Four-Layer PCB
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 15. Derating Curve of Maximum Power
Dissipation
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA ) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
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20
is a registered trademark of Richtek Technology Corporation.
DS8868A-00 May 2012
RT8868A
Outline Dimension
2
1
2
1
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.200
0.300
0.008
0.012
D
6.950
7.050
0.274
0.278
D2
5.050
5.250
0.199
0.207
E
6.950
7.050
0.274
0.278
E2
5.050
5.250
0.199
0.207
e
L
0.500
0.350
0.020
0.450
0.014
0.018
W-Type 48L QFN 7x7 Package
Richtek Technology Corporation
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
DS8868A-00 May 2012
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