RT9607/A Dual Channel Synchronous-Rectified Buck MOSFET Driver General Description Features The RT9607/A is a dual power channel MOSFET driver specifically designed to drive four power N-MOSFETs in a synchronous-rectified buck converter topology. These drivers combined with RichTek’ s series of Multi-Phase Buck PWM controllers provide a complete core voltage regulator solution for advanced microprocessors. z Drives Four N-MOSFETs z Adaptive Shoot-Through Protection Propagation Delay 40ns Support High Switching Frequency Fast Output Rise Time 5V to 12V Gate-Drive Voltages for Optimal Efficiency Tri-State Input for Bridge Shutdown Supply Under-Voltage Protection RoHS Compliant and 100% Lead (Pb)-Free The RT9607/A can provide flexible gate driving for both high side and low side drivers. This gives more flexibility of MOSFET selection. The output drivers of the part are capble to driver a 3nF load in 30/40ns rising/falling time with fast propagation delay from input transition to the gate of the power MOSFET. This device implements bootstrapping on the upper gates with only a single external capacitor required for each power channel. This reduces implementation complexity and allows the use of higher performance, cost effective, N-MOSFETs. Adaptive shoot-through protect-ion is integrated to prevent both MOSFETs from conducting simultaneously. z z z z z z z Applications z z z Core Voltage Supplies for motherboard/desktop PC microprocessor core power High Frequency Low Profile DC-DC Converters High Current Low Voltage DC-DC Converters Ordering Information RT9607/A Package Type QV : VQFN-16L 3x3 (V-Type) S : SOP-14 The RT9607/A can detect high side MOSFET drain-tosource electrical short at power on and pull the 12V power by low side MOS and cause power supply to go into over current shutdown to prevent damage of CPU. RT9607 has longer UGATE/LGATE dead time which can drive the MOSFETs with large gate RC value, avoiding the shoot-through phenomenon. RT9607A is targeted to drive small gate RC value MOSFETs and performs better efficiency. Lead Plating System P : Pb Free G : Green (Halogen Free and Pb Free) Short Dead Time Long Dead Time Note : Richtek products are : ` RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. Marking Information For marking information, contact our sales representative directly or through a Richtek distributor located in your area. DS9607/A-07 April 2011 www.richtek.com 1 RT9607/A Pin Configurations PHASE1 VCC PWM1 PWM2 (TOP VIEW) PWM1 PWM2 GND LGATE1 PVCC PGND LGATE2 16 15 14 13 NC 3 PGND 4 GND 17 5 6 7 8 NC 2 PHASE2 LGATE1 PVCC 1 LGATE2 GND 12 UGATE1 11 BOOT1 10 BOOT2 9 UGATE2 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC PHASE1 UGATE1 BOOT1 BOOT2 UGATE2 PHASE2 SOP-14 VQFN-16L 3x3 Typical Application Circuit Optional 12V 12V 11 BOOT1 12 13 UGATE1 14 VCC PVCC 5 PHASE1 PWM1 1 From Controller PWM1 RT9607/A 4 VCORE 9 8 7 LGATE1 PWM2 2 From Controller PWM2 UGATE2 PHASE2 GND LGATE2 PGND 3 6 BOOT2 10 Optional www.richtek.com 2 DS9607/A-07 April 2011 RT9607/A Timing Diagram PWM tpdlLGATE 90% LGATE tpdlUGATE 2V 2V 90% 2V 2V UGATE tpdhUGATE tpdhLGATE Functional Pin Description Pin No. Pin Name Pin Function RT9607/A□S RT9607/A□QV 1 15 PWM1 Channel 1 PWM Input. 2 16 PWM2 Channel 2 PWM Input. 3 1 GND Ground Pin. 4 2 LGATE1 Lower Gate Drive of Channel 1. 5 5 PVCC Upper and Lower Gate Driver Power Rail. 6 4 PGND Lower Gate Driver Ground Pin. 7 6 LGATE2 Lower Gate Drive of Channel 2. 8 7 PHASE2 9 9 UGATE2 Upper Gate Drive of Channel 2. 10 10 BOOT2 Floating Bootstrap Supply Pin of Channel 2. 11 11 BOOT1 Floating Bootstrap Supply Pin of Channel 1. 12 12 UGATE1 Upper Gate Drive of Channel 1. 13 13 PHASE1 14 14 VCC Control Logic Power Supply. -- 3, 8 NC No Connection. Connect this pin to phase point of Channel 2. Phase point is the connection point of high side MOSFET source Connect this pin to phase point of Channel 1. -- Exposed Pad (17) GND DS9607/A-07 April 2011 Phase point is the connection point of high side MOSFET source The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. www.richtek.com 3 RT9607/A Function Block Diagram PVCC VCC BOOT1 Internal 5V Shoot-Through Protection UGATE1 R PWM1 Power-On OVP PHASE1 R PVCC Shoot-Through Protection Internal 5V Control Logic LGATE1 PGND PGND PVCC BOOT2 Shoot-Through Protection UGATE2 R PWM2 R Power-On OVP PHASE2 PVCC Shoot-Through Protection GND www.richtek.com 4 LGATE2 PGND DS9607/A-07 April 2011 RT9607/A Absolute Maximum Ratings z z z z z z z z z z z z z (Note 1) Supply Voltage, VCC ------------------------------------------------------------------------------------Supply Voltage, PVCC ----------------------------------------------------------------------------------BOOT Voltage, VBOOT-VPHASE ------------------------------------------------------------------------Input Voltage, VPWM -------------------------------------------------------------------------------------PHASE to GND DC -----------------------------------------------------------------------------------------------------------< 200ns ----------------------------------------------------------------------------------------------------BOOT to GND DC -----------------------------------------------------------------------------------------------------------< 200ns ----------------------------------------------------------------------------------------------------UGATE -----------------------------------------------------------------------------------------------------LGATE -----------------------------------------------------------------------------------------------------< 200ns ----------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C 15V VCC + 0.3V 15V GND - 0.3V to 7V VQFN−16L 3x3 -------------------------------------------------------------------------------------------SOP-14 ----------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) VQFN−16L 3x3, θJA -------------------------------------------------------------------------------------SOP-14, θJA ----------------------------------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Mode) ----------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------- 1.471W 0.909W Recommended Operating Conditions z z z −5V to 15V −10V to 30V −0.3V to VCC + 15V −0.3V to 42V VPHASE - 0.3V to VBOOT + 0.3V GND - 0.3V to VPVCC + 0.3V −2V to VCC + 0.3V 68°C/W 110°C /W −40°C to 150°C 260°C 2kV 200V (Note 4) Supply Voltage, VCC ------------------------------------------------------------------------------------- 12V ±10% Junction Temperature Range --------------------------------------------------------------------------- 0°C to 125°C Ambient Temperature Range --------------------------------------------------------------------------- 0°C to 70°C Electrical Characteristics (Recommended Operating Conditions, TA = 25°C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Units VCC Supply Current Bias Supply Current IVCC fPWM = 250kHz, VPVCC = 12V, CBOOT = 0.1μF, RPHASE = 20Ω -- 5.5 8.0 mA Power Supply Current IPVCC fPWM = 250kHz, VPVCC = 12V, CBOOT = 0.1μF, RPHASE = 20Ω -- 5.5 10.0 mA VCC Rising Threshold -- 8.0 -- V Hysteresis -- 1.0 -- V Power-On Reset To be continued DS9607/A-07 April 2011 www.richtek.com 5 RT9607/A Parameter Symbol Test Conditions Min Typ Max Units PWM Input Maximum Input Current VPWM = 0 or 5V -- 500 -- μA PWM Floating Voltage Vcc = 12V -- 2.5 -- V PWM Rising Threshold 3.3 3.7 4.3 V PWM Falling Threshold 1.0 1.26 1.5 V Output UGATE Rise Time trUGATE VPVCC = VVCC = 12V, 3nF load -- 30 -- ns UGATE Fall Time tfUGATE VPVCC = VVCC = 12V, 3nF load -- 40 -- ns LGATE Rise Time trLGATE VPVCC = VVCC = 12V, 3nF load -- 30 -- ns LGATE Fall Time tfLGATE VPVCC = VVCC = 12V, 3nF load -- 30 -- ns -- 75 -- -- 25 -- -- 40 -- -- 20 -- -- 35 -- 1.0 -- 4.3 V RT9607 RT9607A Propagation Delay RT9607/A tpdhUGATE VBOOT = VPHASE = 12V See Timing Diagram tpdlUGATE tpdhLGATE See Timing Diagram tpdlLGATE Shutdown Window ns UGATE Drive Source RUGATEsr VBOOT – VPHASE = 12V -- 1.8 -- Ω UGATE Drive Sink RUGATEsk VBOOT – VPHASE = 12V -- 1.7 -- Ω LGATE Drive Source RLGATEsr VCC = 12V -- 1.5 -- Ω LGATE Drive Sink RLGATEsk VCC = 12V -- 1.4 -- Ω Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective thermal conductivity test board (2S2P,4-layers) of JEDEC 51-7 thermal measurement standard. Note 3. Devices are ESD sensitive. Handling precaution recommended. Note 4. The device is not guaranteed to function outside its operating conditions. www.richtek.com 6 DS9607/A-07 April 2011 RT9607/A Typical Operating Characteristics For RT9607 Dead Time at LGATE Falling Dead Time at LGATE Falling Full Load (60A), PHASE1 Full Load (60A), PHASE2 UGATE UGATE PHASE PHASE (5V/Div) (5V/Div) LGATE LGATE (5V/Div) Time (25ns/Div) Time (25ns/Div) Dead Time at LGATE Rising Dead Time at LGATE Rising Full Load (60A), PHASE1 Full Load (60A), PHASE2 UGATE UGATE PHASE PHASE (5V/Div) LGATE LGATE Time (25ns/Div) Time (25ns/Div) Dead Time at LGATE Falling Dead Time at LGATE Falling No Load, PHASE2 No Load, PHASE1 UGATE UGATE PHASE PHASE (5V/Div) LGATE Time (50ns/Div) DS9607/A-07 April 2011 (5V/Div) LGATE Time (50ns/Div) www.richtek.com 7 RT9607/A Dead Time at LGATE Rising Dead Time at LGATE Rising No Load, PHASE1 No Load, PHASE2 UGATE UGATE PHASE PHASE (5V/Div) (5V/Div) LGATE LGATE Time (50ns/Div) www.richtek.com 8 Time (50ns/Div) DS9607/A-07 April 2011 RT9607/A For RT9607A Dead Time at LGATE Falling Full Load (60A), PHASE1 Full Load (60A), PHASE2 UGATE UGATE PHASE PHASE LGATE - PHASE LGATE - PHASE (5V/Div) (5V/Div) Dead Time at LGATE Falling LGATE (5V/Div) LGATE Time (25ns/Div) Time (25ns/Div) Dead Time at LGATE Rising Dead Time at LGATE Rising Full Load (60A), PHASE1 Full Load (60A), PHASE2 UGATE UGATE PHASE PHASE LGATE - PHASE LGATE - PHASE (5V/Div) LGATE LGATE Time (25ns/Div) Time (25ns/Div) Dead Time at LGATE Falling Dead Time at LGATE Falling No Load , PHASE1 (5V/Div) DS9607/A-07 April 2011 UGATE PHASE PHASE LGATE - PHASE LGATE - PHASE LGATE Time (25ns/Div) No Load , PHASE2 UGATE (5V/Div) LGATE Time (25ns/Div) www.richtek.com 9 RT9607/A Dead Time at LGATE Rising Dead Time at LGATE Rising (5V/Div) No Load, PHASE1 No Load, PHASE2 UGATE UGATE PHASE PHASE LGATE - PHASE LGATE - PHASE (5V/Div) LGATE Time (25ns/Div) www.richtek.com 10 LGATE Time (25ns/Div) DS9607/A-07 April 2011 RT9607/A Application Information The RT9607/A has power on protection function which held UGATE and LGATE low before VCC up cross the rising threshold voltage. After the initialization, the PWM signal takes the control. The rising PWM signal first forces the LGATE signal turns low then UGATE signal is allowed to go high just after a non-overlapping time to avoid shootthrough current. The falling of PWM signal first forces UGATE to go low. When UGATE and PHASE signal reach a predetermined low level, LGATE signal is allowed to turn high. The non-overlapping function is also presented between UGATE and LGATE signal transient. The PWM signal is recognized as high if above rising threshold and as low if below falling threshold. Any signal level in this window is considered as tri-state, which causes turn-off of both high side and low-side MOSFET. When PWM input is floating (not connected), internal divider will pull the PWM to 1.9V to give the controller a recognizable level. The maximum sink/source capability of internal PWM reference is 60μA. The PVCC pin provides flexibility of both high side and low side MOSFET gate drive voltages. If 8V, for example, is applied to PVCC, then high side MOSFET gate drive is 8V to 1.5V (approximately, internal diode plus series resistance voltage drop). The low side gate drive voltage is exactly 8V. The RT9607/A implements a power on over-voltage protection function. If the PHASE voltage exceeds 1.5V at power on, the LGATE would be turn on to pull the PHASE low until the PHASE voltage goes below 1.5V. Such function can protect the CPU from damage by some short condition happened before power on, which is sometimes encountered in the M/B manufacturing line. if the PHASE pin had not gone high after LGATE turns low, the LGATE has to wait for 200ns before turn high only under short pulse (tON<60ns) condition. By waiting for the voltages of the PHASE pin and high side gate drive to fall below 1.2V, the non-overlap protection circuit ensures that UGATE is low before LGATE turns high. Also to prevent the overlap of the gate drives during LGATE turn low and UGATE turn high, the non-overlap circuit monitors the LGATE voltage. When LGATE go below 1.2V, UGATE is allowed to go high. Driving power MOSFETs The DC input impedance of the power MOSFET is extremely high. When Vgs at 12V (or 5V), the gate draws the current only few nanoamperes. Thus once the gate has been driven up to “ON”ON level, the current could be negligible. However, the capacitance at the gate to source terminal should be considered. It requires relatively large currents to drive the gate up and down 12V (or 5V) rapidly. It also required to switch drain current on and off with the required speed. The required gate drive currents are calculated as follows. D1 d1 s1 L VO Vi Cgd1 Cgs1 Igd1 Ig1 Cgd2 d2 Igs1 g1 Ig2 Igd2 g2 D1 Igs2 Cgs2 s2 GND Vg1 Vphase +12V Non-overlap Control To prevent the overlap of the gate drives during the UGATE turn low and the LGATE turn high, the non-overlap circuit monitors the voltages at the PHASE node and high side gate drive (UGATE-PHASE). When the PWM input signal goes low, UGATE begins to turn low (after propagation delay). Before LGATE can turn high, the non-overlap protection circuit ensures that the monitored voltages have gone below 1.2V. Once the monitored voltages fall below 1.2V, LGATE begins to turn high. For short pulse condtion, DS9607/A-07 April 2011 t Vg2 +12V t Figure1. The gate driver must supply Igs to Cgs and Igd to Cgd www.richtek.com 11 RT9607/A In Figure 1, the current Ig1 and Ig2 are required to move the from equation. (3) and (4) gate up to 12V.The operation consists of charging Cgd and Cgs. Cgs1 and Cgs2 are the capacitances from gate to source of the high side and the low side power MOSFETs, respectively. In general data sheets, the Cgs is referred as “Ciss” which is the input capacitance. Cgd1 and Cgd2 are the capacitances from gate to drain of the high side and the low side power MOSFETs, respectively and referred to the data sheets as "C rss ," the reverse transfer capacitance. For example, tr1 and tr2 are the rising time of the high side and the low side power MOSFETs respectively, the required current Igs1 and Igs2, are showed below Igs1 = dVg1 Cgs1 x 12 Igs1 = Cgs1 = dt tr1 dVg2 Cgs2 x 12 Igs2 = Cgs2 = dt tr2 (1) (2) According to the design of RT9607/A, before driving the gate of the high side MOSFET up to 12V (or 5V), the low side MOSFET has to be off; and the high side MOSFET is turned off before the low side is turned on. From Figure 1, the body diode "D2" had been turned on before high side MOSFETs turned on Igd1 = Cg1 dV 12V = Cgd1 dt tr1 (3) Before the low side MOSFET is turned on, the Cgd2 have been charged to Vi. Thus, as Cgd2 reverses its polarity and g2 is charged up to 12V, the required current is Igd2 = Cgd2 dV Vi + 12V = Cgd2 dt tr2 (4) It is helpful to calculate these currents in a typical case. Assume a synchronous rectified BUCK converter, input voltage Vi = 12V, Vg1 = Vg2 = 12V. The high side MOSFET is PHB83N03LT whose Ciss = 1660pF, Crss = 380pF,and tr = 14nS. The low side MOSFET is PHB95N03LT whose Ciss = 2200pF, Crss = 500pF, and tr = 30nS, from the equation (1) and (2) we can obtain Igs1 = 1660 x 10 -12 x 12 14 x 10 Igs2 = -9 2200 x 10 -12 x 12 30 x 10 www.richtek.com 12 -9 = 1.428A = 0.88A (5) Igs2 = 380 x 10 -12 x 12 14 x 10 -9 500 x 10 -12 x (12 + 12) 30 x 10 -9 (7) = 0.326A = 0.4A (8) the total current required from the gate driving source is Ig1 = Igs + Igd1 = (1.428 + 0.326) = 1.745A Ig2 = Igs2 + Igd2 = (0.88 + 0.4) = 1.28A (9) (10) By a similar calculation, we can also get the sink current required from the turned off MOSFET. Layout Consider Figure 2. shows the schematic circuit of a two-phase synchronous-buck converter to implement the RT9607/A. The converter operates for the input rang from 5V to 12V. When layout the PC board, it should be very careful. The power-circuit section is the most critical one. If not configured properly, it will generate a large amount of EMI. The junction of Q1, Q2, L2 and Q3, Q4, L4 should be very close. The connection from Q1, and Q3 drain to positive sides of C1, C2, C3, and C4; the connection from Q2, and Q4 source to the negative sides of C1, C2, C3, and C4 should be as short as possible. Next, the trace from Ugate1, Ugate2, Lgate1, and Lgate2 should also be short to decrease the noise of the driver output signals. Phase1 and phase2 signals from the junction of the power MOSFET, carrying the large gate drive current pulses, should be as heavy as the gate drive trace. The bypass capacitor C7 should be connected to PGND directly. Furthermore, the bootstrap capacitors (Cb1, Cb2) should always be placed as close to the pins of the IC as possible. Select the Bootstrap Capacitor Figure 3. shows part of the bootstrap circuit of RT9607/A. The VCB (the voltage difference between BOOT1 and PHASE1 on RT9607/A) provides a voltage to the gate of the high side power MOSFET. This supply needs to be ensured that the MOSFET can be driven. For this, the capacitance C B has to be selected properly. It is (6) DS9607/A-07 April 2011 RT9607/A determined by following constraints. In practice, a low value capacitor CB will lead the overcharging that could damage the IC. Therefore to minimize the risk of overcharging and reducing the ripple on VCB, the bootstrap capacitor should not be smaller than 0.1μF, and the larger the better. In general design, using 1μF can provide better performance. At least one low-ESR capacitor should be used to provide good local de-coupling. Here, to adopt either a ceramic or tantalum capacitor is suitable. D1 R1 L1 VIN 1.2uH 12V Cb1 1uF C2 1uF C1 1000uF 12 Q1 L2 PHB83N03LT 13 2uH 11 BOOT1 UGATE1 14 VCC PVCC 12V 5 PHASE1 PWM1 1 PWM1 RT9607/A C5 1500uF PHB95N03LT Q2 4 LGATE1 PWM2 9 C4 1uF C3 1000uF 8 Q3 L3 7 2 PWM2 UGATE2 PHASE2 GND LGATE2 PGND 3 6 PHB83N03LT 2uH C6 1500uF C7 10 1uF Q4 Cb2 1uF BOOT2 10 D2 PHB95N03LT VCORE Figure 2. Two- Phase Synchronous-Buck Converter Circuit PVCC Vin BOOT1 UGATE1 PHASE1 + CB VCB - PVCC LGATE1 PGND Figure 3. Part of Bootstrap Circuit of RT9607/A DS9607/A-07 April 2011 www.richtek.com 13 RT9607/A Outline Dimension D SEE DETAIL A D2 L 1 E E2 e b A A1 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A3 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.800 1.000 0.031 0.039 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 1.300 1.750 0.051 0.069 E 2.950 3.050 0.116 0.120 E2 1.300 1.750 0.051 0.069 e L 0.500 0.350 0.020 0.450 0.014 0.018 V-Type 16L QFN 3x3 Package www.richtek.com 14 DS9607/A-07 April 2011 RT9607/A H A M J B F C I D Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 8.534 8.738 0.336 0.344 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.178 0.254 0.007 0.010 I 0.102 0.254 0.004 0.010 J 5.791 6.198 0.228 0.244 M 0.406 1.270 0.016 0.050 14–Lead SOP Plastic Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. DS9607/A-07 April 2011 www.richtek.com 15