RT9719 Charging System Safety Device General Description Features The RT9719 is an integrated circuit (IC) designed to replace passive device in charging system with extra protection function. It is optimized to protect low voltage system from up to 28V high voltage input. The IC monitors the input voltage to make sure all parameters are operating in normal range. It also monitors its own temperature and turn off the MOSFET when the chip temperature exceeds 140°C. When the input voltage exceeds the threshold, the IC turns off the power MOSFET within 1us to remove the power before any damage occurs. User can monitor the adapter input voltage from CHRIN pin which has 50mA current capability. The gate of the P-MOSFET will be controlled by the external charging controller from GATEDRV pin if all parameters are operating in normal range. z ` RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Application z z z z Cellular Phones Digital Cameras PDAs and Smart Phones Portable Instruments Pin Configurations ACIN ACIN ACIN GND 1 2 3 4 GND (TOP VIEW) 9 8 7 6 5 ISENSE ISENSE CHRIN GATEDRV WDFN-8L 2x2 ISENSE Richtek products are : z 6 5 4 2 3 ACIN Note : OVP Default : 6.25V A : 7.20V z CHRIN Package Type E : SOT-23-6 QW : WDFN-8L 2x2 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) z GND RT9719 z GATEDRV Ordering Information z μs Overvoltage Turn Off Time of Less Than 1μ High Accuracy Protection Thresholds Over Temperature Protection High Immunity of False Triggering Under Transients Thermal Enhanced SOT-23-6 and 8-Lead WDFN Packages RoHS Compliant and Halogen Free NC The RT9719 is available in SOT-23-6 and WDFN-8L 2x2 tiny packages to achieve best solution for PCB space and total BOM cost saving considerations. z No External Blocking Diode Requiring SOT-23-6 Suitable for use in SnPb or Pb-free soldering processes. Marking Information For marking information, contact our sales representative directly or through a Richtek distributor located in your area. DS9719-01 April 2011 www.richtek.com 1 RT9719 Typical Application Circuit SOC RT9719 ACIN CHRIN VACIN CHRIN CIN 1µF COUT 1µF GATEDRV GND GATEDRV ISENSE ISENSE 1µF 0.2 VBAT Battery Functional Pin Description Pin No. Pin Name Pin Function SOT-23-6 WDFN-8L 2x2 1 -- NC No Internal Connection. 2 4 GND Analog Ground. 3 1, 2, 3 ACIN The Input Power Source. The VIN can withstand up to 30V input. 4 7, 8 ISENSE Connect to ISENSE resistor and ISENSE pin of charging controller. 5 6 CHRIN Voltage is equal to VIN as VIN in power good range and providing ~25mA for system at most. 6 5 GATEDRV External control pin for controlling the P-MOSFET by charging controller. -- 9 GND (Exposed pad) Ground Pin. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. Function Block Diagram SW ACIN CHRIN Control Logic MUX GATEDRV ISENSE SW GND INOVP www.richtek.com 2 UVLO OTP DS9719-01 April 2011 RT9719 Absolute Maximum Ratings z z z z z z z z z z (Note 1) Supply Input Voltage, VIN ------------------------------------------------------------------------------------------------Output (as VIN > VOUT, normal mode) ---------------------------------------------------------------------------------Output (as sleep mode) --------------------------------------------------------------------------------------------------Other Pins -------------------------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C SOT-23-6 --------------------------------------------------------------------------------------------------------------------WDFN-8L 2x2 --------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) SOT-23-6, θJA ---------------------------------------------------------------------------------------------------------------WDFN-8L 2x2, θJA ---------------------------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Mode) ----------------------------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------------------------- Recommended Operating Conditions z z −0.3V to 30V −0.3V to 7V −0.3V to 4.5V −0.3V to 6V 0.556W 0.8W 180°C/W 125°C/W 150°C 260°C −65°C to 150°C 2kV 200V (Note 4) Junction Temperature Range --------------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range --------------------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VIN = 5V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit 2.5 2.7 2.9 V -- 100 -- mV When enable -- 200 600 μA As ACIN floating -- 5 10 μA Operation Voltage 4.3 -- 6.5 V Operation Current -- -- 1 A RT9719 6 6.25 6.5 V RT9719A 7 7.2 7.4 V Input OVP Hysteresis -- 60 100 mV Input OVP Propagation Delay -- -- 1 μs OTP Rising Thershold -- 140 -- °C OTP Hysteresis -- 20 -- °C Power On Reset Rising VIN Threshold UVLO POR Hysteresis VIN Bias Current Reverse Leakage ILEAKAGE Protections Input OVP Reference Voltage INOVP To be continued DS9719-01 April 2011 www.richtek.com 3 RT9719 Parameter Power MOSFET RDS(ON) Between ACIN to ISENSE RDS(ON) Between ACIN to CHRIN Symbol Conditions Measure @ 500mA. 4.3V < VIN < 6V Measure @ 50mA. 4.3V < VIN < RDS(ON)_CHRIN 6V RDS(ON)_ISENSE Min Typ Max Unit -- -- 500 mΩ -- -- 3 Ω Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2. θJA is measured in the natural convection at TA = 25°C on a low effective single layer thermal conductivity test board of JEDEC 51-3 thermal measurement standard. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. www.richtek.com 4 DS9719-01 April 2011 RT9719 Typical Operating Characteristics CHRIN RDS(ON) vs. Input Voltage 3.0 450 2.8 400 2.6 350 2.4 RDS(ON) ( Ω ) ISENSE Current (mA) GATEDRV Voltage vs. ISENSE Current 500 300 250 200 150 0 2.0 1.8 1.6 100 50 2.2 1.4 2.5 2.7 2.9 ACIN = 5V, ISENSE = Open, CHRIN = 50mA, GATEDRV = 5V 1.2 ACIN = 4.5V, RLOAD = 9.1Ω 1.0 3.1 3.3 3.5 2.7 3.7 3.1 3.5 2.6 2.4 0.7 2.2 2.0 RDS(ON) ( Ω ) RDS(ON) ( Ω ) 0.6 0.5 0.4 0.3 1.8 1.6 1.4 1.2 0.2 1.0 ACIN = 5V, ISENSE = 500mA, CHRIN = Open, GATEDRV = 0V 2.7 3.1 3.5 ACIN = 5V, ISENSE = Open, CHRIN = 50mA, GATEDRV = 5V 0.8 0.6 0 3.9 4.3 -40 -25 -10 4.7 5 0.5 100 Supply Current (μA) RDS(ON) ( Ω ) 120 0.4 0.3 0.2 20 35 50 65 80 95 110 125 60 40 ACIN = 5V, ISENSE = Open, CHRIN = Open, GATEDRV = 5V 0 65 Temperature (°C) DS9719-01 April 2011 50 80 20 ACIN = 5V, ISENSE = 500mA, CHRIN = Open, GATEDRV = 0V 5 35 Supply Current vs. Temperature RDS(ON) vs. Temperature 0.6 -40 -25 -10 20 Temperature (°C) Input Voltage (V) 0 4.7 CHRIN RDS(ON) vs. Temperature ISENSE RDS(ON) vs. Input Voltage 0.8 0.1 4.3 Input Voltage (V) GATEDRV Voltage (V) 0.1 3.9 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) www.richtek.com 5 RT9719 Input OVP Propagation Delay OVP vs. Temperature 6.50 CHRIN = 1kΩ, GATEDRV = ACIN ACIN 6.25 OVP (V) 6.00 5.75 5.50 5.25 CHRIN (1V/Div) ACIN = 5V, ISENSE = Open, CHRIN = 1kΩ, GATEDRV = 5V 5.00 -40 -25 -10 5 20 35 50 65 80 95 110 125 Time (500ns/Div) Temperature (°C) Input OVP Recovery Delay CHRIN = 1kΩ, GATEDRV = ACIN ACIN CHRIN (1V/Div) Time (1μs/Div) www.richtek.com 6 DS9719-01 April 2011 RT9719 Application information Internal Over Temperature Protection Operation State The operation state can be shown as following Figure 1. At power-off state, the RT9719 will check whether VIN is > UVLO threshold. If the VIN is higher than the UVLO threshold, the RT9719 will check whether the Junction temperature is over the OTP threshold. If the Junction temperature is higher than the OTP threshold, the internal P-MOSFET will be turned off. If the Junction temperature is lower than the OTP threshold, the RT9719 will check whether VIN is higher than the OVP threshold or not, if the VIN is higher than the OVP threshold, the RT9719 will turn off the internal P-MOSFET immediately within 1us. And, if all of the checks including VIN > UVLO, TJ < OTP and VIN < OVP are ok, the IC will operate normally. The RT9719 monitors its own internal temperature to prevent thermal failures. When the internal temperature reaches 140°C with a built-in hysteresis of 20°C, the IC turns off the power MOSFET. The IC does not resume operation until the internal temperature drops below 120°C. Input Under Voltage Protection (UVLO) The RT9719 monitors input voltage to prevent the input voltage lead to output system failures. The RT9719 input under voltage protection threshold is set to 2.7V. When the input voltage is under the threshold, the RT9719 will turn off the power MOSFET within 1us. When the input voltage returns to normal operation voltage range, the RT9719 re-enables the MOSFET. VACIN Start V IN > UVLO Y T J > OTP N Power-Off Status Y OTP Status PFET=OFF N V IN > OVP N Normal Status P-MOSFET = ON and Control by GATEDRV Y OVP Status P-MOSFET = Off(Fast) RT9719 CHRIN SOC CHRIN COUT 1µF ACIN CIN 1µF GATEDRV GATEDRV ISENSE ISENSE GND 1µF Figure 1. Operation State Diagram for OVP Function Input Over Voltage Protection (OVP) The RT9719 monitors input voltage to prevent the input voltage lead to output system failures. When the input voltage exceeds the threshold, the RT9719 will turn off the power MOSFET within 1us to prevent the high input voltage from damaging the electronics in the handheld system. The hysteresis for the input OVP threshold is 100mV. When the input voltage returns to normal operation voltage range, the RT9719 re-enables the MOSFET. The RT9719 allows the input voltage to rise up to 30V without damaging the IC. Battery Voltage Monitor The RT9719 monitors the battery voltage by the ISENSE pin. When the battery voltage exceeds the voltage level of (VACIN − 0.2V), the RT9719 will turn off the MOSFET and the battery will not be charged. The RT9719 will recharge the battery when the battery voltage is lower than the voltage of (VACIN − 0.2V). DS9719-01 April 2011 0.2 VBAT Battery Figure 2. Application Diagram of RT9719 with SOC Figure 2 shows the connection of RT9719 in a system diagram. The ISENSE pin of the SOC will sense the voltage of the 0.2Ω sense resistor and the voltage of the VBAT pin. The GATEDRV pin of the SOC can control the MOSFET of the RT9719 to determine the level of the charge current. The power of the SOC is provided by the CHRIN pin of the RT9719. The RT9719 provides OVP function, once the input voltage at the ACIN pin is higher than the OVP level, the RT9719 will be shutdown to prevent the SOC from damaging. If the voltage of the battery connected to the VBAT pin is full, the RT9719 stops charging by turning off the ISENSE pin. Input and output capacitors of 1uF are recommended to place as close to IC as possible. Thermal Considerations The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between www.richtek.com 7 RT9719 PD(MAX) = ( TJ(MAX) − TA ) / θJA Where T J(MAX) is the maximum operation junction temperature, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of RT9719, where TJ(MAX) is 125°C and TA is the operated ambient temperature. The junction to ambient thermal resistance θJA for WDFN-8L 2x2 package is 165°C/W and SOT-23-6 package is 250°C/W on the standard JEDEC 51-3 single-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by following formula : PD(MAX) = (125°C − 25°C) / (165°C/W) = 0.606 W for WDFN-8L 2x2 packages PD(MAX) = (125°C − 25°C) / (250°C/W) = 0.400 W for SOT-23-6 packages The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θJA . For RT9719 packages, the Figure 3 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. 1.0 Power Dissipation (W) 0.9 0.8 The RT9719 is a protection device. Careful PCB layout is necessary. For best performance, place all peripheral components as close to the IC as possible. A short connection is highly recommended. The following guidelines should be strictly followed when designing a PCB layout for the RT9719. ` The exposed pad, GND must be soldered to a large ground plane for heat sinking and noise prevention. The through-hole vias located at the exposed pad is connected to ground plane of internal layer. ` ACIN traces should be wide to minimize inductance and handle the high currents. The trace running from input to chip should be placed carefully and shielded strictly. ` The capacitors must be placed close to the part. The connection between pins and capacitor pads should be copper traces without any through-hole via connection. From Adapter ACIN ACIN ACIN C IN GND 1 2 3 4 8 7 6 5 9 ISENSE ISENSE CHRIN GATEDRV To Baseband Gate Controller To Battery To Baseband Charger Controller GND The capacitor must be placed between GND and ACIN to reduce noise. The exposed pad, GND must be soldered to a large ground plane for heat sinking and noise prevention. Input capacitor must be placed between GND and ACIN to reduce noise. Four Layouts PCB WDFN-8L 2x2 6 To Baseband Gate Controller GATEDRV 2 5 CHRIN 3 4 ISENSE NC 0.7 0.6 Layout Consideration GND junction to ambient. The maximum power dissipation can be calculated by following formula : GND From Adapter ACIN SOT-23-6 0.5 0.4 The capacitor must be placed between GND and ACIN to reduce noise. To Baseband Charger Controller To Battery C IN 0.3 GND Input capacitor must be placed between GND and ACIN to reduce noise. 0.2 0.1 0.0 0 25 50 75 100 The exposed pad, GND must be soldered to a large ground plane for heat sinking and noise prevention. 125 Ambient Temperature (°C) Figure 4. PCB Layout Guide Figure 3. Derating Curves for RT9719 Packages www.richtek.com 8 DS9719-01 April 2011 RT9719 Outline Dimension H D L C B b A A1 e Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.889 1.295 0.031 0.051 A1 0.000 0.152 0.000 0.006 B 1.397 1.803 0.055 0.071 b 0.250 0.560 0.010 0.022 C 2.591 2.997 0.102 0.118 D 2.692 3.099 0.106 0.122 e 0.838 1.041 0.033 0.041 H 0.080 0.254 0.003 0.010 L 0.300 0.610 0.012 0.024 SOT-23-6 Surface Mount Package DS9719-01 April 2011 www.richtek.com 9 RT9719 D2 D L E E2 1 e SEE DETAIL A b 2 1 2 1 A A1 A3 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 D 1.950 2.050 0.077 0.081 D2 1.000 1.250 0.039 0.049 E 1.950 2.050 0.077 0.081 E2 0.400 0.650 0.016 0.026 e L 0.500 0.300 0.020 0.400 0.012 0.016 W-Type 8L DFN 2x2 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. www.richtek.com 10 DS9719-01 April 2011