RT9725A/B Express Card Power Interface Switch General Description Features The RT9725A/B power distribution switches are designed to fulfill power management requirements of Express Card specification. The RT9725A/B supports systems with single slot ExpressCard|34 and ExpressCard|54 socket. The device distributes 3.3V, AUX and 1.5V to the Express Card socket. Each power rail is protected with current limit circuitry when output load exceeds over-current threshold or short-circuits occurs. A thermal protection circuit turns off switches to prevent the device from damage when power dissipation is increased by continuous heavy overloads or short-circuits in the switches. The RT9725A/B is available in WQFN-20L 3x3 package. z Meets Express Card Standard (ExpressCard|34 and ExpressCard|54) z Compliant with the Express Card Compliance Check Lists, Compliance ID : EC100328 Fully Satisfy the Express Card Implementation Guidelines Supports Systems with WAKE Function TTL-Logic Compatible Input Under-Voltage Lockout Protection Over Current Protection Over Temperature Protection RoHS Compliant and Halogen Free Ordering Information Applications RT9725A/B z z z z z z z z z Lead Plating System G : Green (Halogen Free and Pb Free) SYSRST Pull High Resistor A : With Internal Resistor B : Without Internal Resistor z PCs PDAs Digital Cameras TV and Set Top Boxes Pin Configurations (TOP VIEW) SHDN FLG RCLKEN AUXIN NC Note : Richtek products are : ` RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. Marking Information For marking information, contact our sales representative directly or through a Richtek distributor located in your area. 20 19 18 17 16 STBY 3.3VIN 3.3VOUT NC NC 1 15 2 14 GND 3 4 13 12 21 5 11 6 7 8 9 AUXOUT NC NC 1.5VIN 1.5VOUT 10 SYSRST GND PERST CPUSB CPPE Package Type QW : WQFN-20L 3x3 (W-Type) z WQFN-20L 3x3 DS9725A/B-01 April 2011 www.richtek.com 1 RT9725A/B Typical Application Circuit RT9725A/B 15 17 AUXIN AUXOUT 4.7µF 3.3V AUXOUT 22µF 100k 19 FLG 2 3.3VIN FLG 3.3V 4.7µF 3.3VOUT 3 1.5VOUT 11 4.7µF PERST 20 SHDN SHDN 1 STBY 6 SYSRST STBY SYSRST 1.5VOUT 22µF 12 1.5VIN 1.5V 3.3VOUT 22µF CPPE 8 10 PERST CPPE 9 CPUSB CPUSB 18 RCLKEN RCLKEN 7, Exposed Pad (21) GND Functional Pin Description Pin No. Pin Name Pin Function 1 STBY Standby input-active low, logic level signal, Internal pulled up to AUXIN. 2 3.3VIN Input pin for 3.3V output voltage. 3 3.3VOUT Switched output that delivers 0V,3.3V or high impedance to card. NC No Internal Connection. System reset input-active low, logic level signal, Internal pulled up to AUXIN for RT9725A or floating for RT9725B. Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. 4, 5, 13, 14, 16 6 SYSRST 7, 21 (Exposed Pad) GND 8 PERST A logic level power good to slot (with delay). 9 CPUSB Card present input for USB cards, Internal pulled up to AUXIN. 10 CPPE Card present input for PCI cards, Internal pulled up to AUXIN. 11 1.5VOUT Switched output that delivers 0V,1.5V or high impedance to card. 12 1.5VIN Input pin for 1.5V output voltage. 15 AUXOUT Switched output that delivers 0V,AUX or high impedance to card. 17 AUXIN 18 RCLKEN AUX input for AUXOUT and chip power. Reference Clock Enable signal. As an output, a logic power good to host for slot (no delay-open drain). As an input, if kept inactive(low) by the host, prevents PERST from being de-asserted. Internal pulled up to AUXIN 19 FLG Over current or over temperature status output for slot (open drain) 20 SHDN Shutdown input-active low, logic level signal. Internal pulled up to AUXIN www.richtek.com 2 DS9725A/B-01 April 2011 RT9725A/B Function Block Diagram AUXOUT AUXIN Current Limit 3.3VOUT 3.3VIN Current Limit 1.5VOUT 1.5VIN UVLO Current Limit Power Good FLG CPUSB CPPE Gate Control AUXIN STBY SHDN Delay Charge Pump OTP RCLKEN AUXIN PERST Oscillator GND DS9725A/B-01 April 2011 RT9725A Only SYSRST www.richtek.com 3 RT9725A/B Operation Table 1. Truth Table for Voltage Outputs Input Power (1) Logic Input AUXIN 3.3VIN 1.5VIN Off X On On Output (2) Mode (3) CPXX (4) AUXOUT 3.3VOUT 1.5VOUT X Off Off Off X SHDN X STBY X X X 0 X X GND GND GND Shutdown X X 1 X 1 GND GND GND No Card Off On Off 1 1 1 >> 0 Off Off Off Off On ON >> Off 1 1 0 On Off Off Standby (5) On On On 1 0 0 On Off Off Standby On On On 1 1 0 On On On Card Inserted (1) For Power Input : “On” means the respective input voltage is higher than its turn on threshold voltage; “Off” means the input voltage is lower than its UVLO falling threshold voltage. (for AUX input, “Off ” means the voltage is close to 0V). (2) For Output : “On” means the respective power switch is turned on, so that the input is connected to the output; “Off” means the power switch and its output discharge FET are both off; “GND ” means the powers switch is off but the output discharge FET is on, so that the voltage on the output is pulled down to 0V. (3) Mode assigns each set of input conditions and respective output voltage results to a different name. These modes are referred to as input conditions in the following “Truth Table” for Logic Outputs. (4) CPXX = 1 when both CPUSB and CPPE signals are logic high, or CPXX = 0 when either CPUSB or CPPE is low. (5) The card is inserted prior to the removal of the Primary or Secondary power (either 3.3VIN or 1.5VIN or both) at the input of the ExpressCard power switch, then only the Primary and Secondary power (both 3.3VOUT and 1.5VOUT) are removed and the auxiliary power is sent to the ExpressCard slot. (6) “X” means “Don'st Care”. Table 2. Truth Table for Logic Output Input Conditions Mode Logic Outputs SYSRST RCLKEN (1) PERST RCLKEN (2) X X 0 0 0 Hi-Z 0 1 0 0 0 0 1 Hi-Z 1 1 1 0 0 0 OFF Shutdown No Card Standby Card Inserted (1) RCLKEN acts as a logic input in this column. RCLKEN is an I/O pin and it can be driven low externally, left open, or connected to high-impedance terminals, such as the gate of a MOSFET. It must not be driven high externally. (2) RCLKEN acts as a logic output in this column. www.richtek.com 4 DS9725A/B-01 April 2011 RT9725A/B Absolute Maximum Ratings z z z z z z z z z (Note 1) Supply Voltage (AUXIN, 3.3VIN) ----------------------------------------------------------------------------------- −0.3V to 5V Supply Voltage 1.5VIN ----------------------------------------------------------------------------------------------- −0.3V to 2.5V Logic Input/Output Voltage ------------------------------------------------------------------------------------------ −0.3V to 5V Power Dissipation, PD @ TA = 25°C WQFN-20L 3x3 -------------------------------------------------------------------------------------------------------- 1.667W Package Thermal Resistance (Note 2) WQFN-20L 3x3, θJA --------------------------------------------------------------------------------------------------- 60°C/W WQFN-20L 3x3, θJC -------------------------------------------------------------------------------------------------- 7.5°C/W Junction Temperature ------------------------------------------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------- 260°C Storage Temperature Range ---------------------------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility (Note 3) HBM (Human Body Mode) ------------------------------------------------------------------------------------------ 2kV MM (Machine Mode) -------------------------------------------------------------------------------------------------- 200V Recommended Operating Conditions z z z z (Note 4) Supply Voltage (AUXIN, 3.3VIN) ----------------------------------------------------------------------------------- 3V to 3.6V Supply Voltage (1.5VIN) --------------------------------------------------------------------------------------------- 1.35V to 1.65V Junction Temperature Range ---------------------------------------------------------------------------------------- −40°C to 100°C Ambient Temperature Range ---------------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (V(3.3VIN) = V(AUXIN) = 3.3V, V(1.5VIN) = 1.5V, VSHDN = VSTBY = VSYSRST =3.3V, VCPPE = VCPUSB = 0V, PERST, FLG, RCLKEN are open, all output voltage are unloaded; TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max -- 90 120 -- 90 120 -- 120 160 100 300 500 1350 2000 2500 670 1000 1300 275 450 600 -- 25 30 -- 25 30 -- 250 280 -- 5 10 -- 5 10 -- 280 310 Unit Power Switch RDS(ON)_33 Switch On Resistance RDS(ON)_15 RDS(ON)_AUX Discharge Resistance (3.3V/1.5V/AUX Output) RDischarge ISC_33 Output Short-Circuit Current ISC_15 (steady state value) ISC _AUX Total Input Quiescent Current (Normal Operation) IQ_33 IQ_15 3.3VIN to 3.3VOUT, IOUT = 1300mA 1.5VIN to 1.5VOUT, IOUT = 650mA AUXIN to AUXOUT, IOUT = 275mA VSHDN = 0V, IDischarge = 1mA Output power into a short Output are unloaded (Include CPPE and CPUSB logic pull-up current) IQ _AUX Total Input Quiescent Current (Shutdown Mode) ISHDN_33 ISHDN_15 ISHDN _AUX VCPPE = VCPUSB = VSHDN = 0V, discharge FETs are on (Include CPPE, CPUSB and SHDN pull-up current) mΩ Ω mA μA μA To be continued DS9725A/B-01 April 2011 www.richtek.com 5 RT9725A/B Parameter Symbol Test Conditions Min Typ Max Unit VCPPE = VCPUSB = V SHDN = 3.3V, (no card present, discharge FETs are on) current measured at input pins, include RCLKEN pull-up current -- 0.1 50 -- 0.1 50 -- 20 50 V3.3VOUT = VAUXVOUT = 3.3V, V1.5VOUT = 1.5V, all voltage inputs are grounded (current measured from output pins going in) -- 5 10 -- 5 10 -- 5 10 -- 130 -- -- 100 -- -- 20 -- VSHDN = 3.3V, Sinking -- 0 1 VSHDN = 0V, Sourcing -- 20 35 VSTBY = 3.3V, Sinking -- 0 1 VSTBY = 0V, Sourcing -- 20 35 VCPPE or VCPUSB = 3.3V, Sinking -- 0 1 VCPPE or VCPUSB = 0V, Sourcing -- 20 35 VSYSRST = 3.3V, Sinking -- 0 1 VSYSRST = 0V, Sourcing -- 20 35 IRCLKEN VRCLKEN = 0V, Sourcing -- 20 35 VIH High Level 2 -- -- VIL Low Level -- -- 0.8 IRCLKEN = 60uA -- 0.2 0.4 3.3VOUT Falling 2.7 2.85 3 1.5VOUT Falling 1.2 1.27 1.35 AUXOUT Falling 2.7 2.85 3 -- 300 500 ns 4 10 20 ms -- -- 500 ns 100 250 -- μs Power Switch ILKF_33 Forward Leakage Current ILKF_15 ILKF _AUX ILKR_33 Reverse Leakage Current ILKR_15 ILKR _AUX TSD Thermal Shutdown TSD ΔT SD Rising temperature, not in overcurrent condition Rising temperature, in over-current condition Hysteresis μA μA °C Logic Selection (SHDN, STBY, CPPE, CPUSB, SYSRST, PERST, FLG, RCLKEN ISHDN ISTBY Logic Input Supply Current ICPPE or ICPUSB ISYSRST Logic Input Voltage RCLKEN Output Low Voltage PERST Assertion VPGOOD_33 Threshold of Output VPGOOD _15 Voltage (PERST asserted when any of outputs falls VPGOOD _AUX below the threshold) PERST Assertion Delay from Output Voltage PERST De-assertion Delay from Output Voltage PERST Assertion Delay from SYSRST PERST Minimum Pulse Width PERST Output Voltage 3.3VOUT, AUXOUT or 1.5VOUT falling 3.3VOUT, AUXOUT and 1.5VOUT rising within tolerance Maximum time from SYSRST assertion 3.3VOUT, AUXOUT or 1.5VOUT falling out of tolerance or triggered by SYSRST High Level, IPERST = 500μA 2.4 -- -- Low Level, IPERST = 500μA -- -- 0.4 μA V V V V To be continued www.richtek.com 6 DS9725A/B-01 April 2011 RT9725A/B Parameter Symbol Test Conditions Min Typ Max Unit FLG Output Low Voltage VFLG IFLG = 2mA -- 0.2 0.4 V FLG Leakage Current ILK_FLG VFLG = 3.3V -- 0 1 μA FLG Delay Time tD Falling into an over-current or over temperature condition 4 10 20 ms 2.6 2.75 2.9 1 1.125 1.25 2.6 2.75 2.9 -- 100 -- 0.1 -- 3 0.1 -- 6 0.1 -- 3 0.1 -- 6 0.1 -- 3 0.1 -- 6 10 -- 150 μs 2 -- 30 ms 10 -- 150 μs UVLO 3.3VIN UVLO VUVLO_33 1.5VIN UVLO VUVLO_15 AUXIN UVLO VUVLO_AUX Hysteresis ΔVUVLO Below which 3.3VIN and 1.5VIN switches are off (rising VIN) Below which all switches are off (rising VIN) Falling VIN V mV Switching tRISE_33 Output Rising Time tRISE _15 tRISE _AUX tFALL_NC_33 Output Falling Time when Card Removed (both CPPE and CPUSB tFALL_NC _15 de-asserted) tFALL_NC _AUX tFALL_SD_33 Output Falling Time when SHDN Asserted (Card is present) tFALL_SD _15 tFALL_SD _AUX DS9725A/B-01 April 2011 3.3VIN to 3.3VOUT, C3.3VOUT = 0.1μF, I3.3OUT = 0A 3.3VIN to 3.3VOUT, C3.3VOUT = 100μF, RLOAD_3.3 = V 3.3VIN/1A 1.5VIN to 1.5VOUT, C1.5VOUT = 0.1μF, I1.5OUT = 0A 1.5VIN to 1.5VOUT, C1.5VOUT = 100μF, RLOAD_1.5 = V 1.5VIN/0.5A AUXIN to AUXOUT, CAUXOUT = 0.1μF, IAUXOUT = 0A AUXIN to AUXOUT, CAUXOUT = 100μF, RLOAD_AUX = VAUXIN/0.25A 3.3VIN to 3.3VOUT, C3.3VOUT = 0.1uF, I3.3OUT = 0A 3.3VIN to 3.3VOUT, C3.3VOUT = 20uF, I3.3OUT = 0A 1.5VIN to 1.5VOUT, C1.5VOUT = 0.1μF, I1.5OUT = 0A ms 1.5VIN to 1.5VOUT, C1.5VOUT = 20μF, I1.5OUT = 0A AUXIN to AUXOUT, CAUXOUT = 0.1uF, IAUXOUT = 0A AUXIN to AUXOUT, CAUXOUT = 20uF, IAUXOUT = 0A 2 -- 30 ms 10 -- 150 μs 2 -- 30 ms 3.3VIN to 3.3VOUT, C3.3VOUT = 0.1μF, I3.3OUT = 0A 10 -- 150 μs 3.3VIN to 3.3VOUT, C3.3VOUT = 100uF, RLOAD_3.3 = V 3.3VIN/1A 0.1 -- 5 ms 1.5VIN to 1.5VOUT, C1.5VOUT = 0.1uF, I1.5OUT = 0A 1.5VIN to 1.5VOUT, C1.5VOUT = 100μF, RLOAD_1.5 = V 1.5VIN/0.5A AUXIN to AUXOUT, CAUXOUT = 0.1μF, IAUXOUT = 0A 10 -- 150 μs 0.1 -- 5 ms 10 -- 150 μs AUXIN to AUXOUT, CAUXOUT = 100μF, RLOAD_AUX = VAUXIN/0.25A 0.1 -- 5 ms www.richtek.com 7 RT9725A/B Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective four layers thermal conductivity test board of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad for the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. www.richtek.com 8 DS9725A/B-01 April 2011 RT9725A/B Typical Operating Characteristics Power On Power On When Card Inserted CPUSB /CPPE (2V/Div) RCLKEN (2V/Div) AUXOUT (2V/Div) PERST (2V/Div) 3.3VOUT (1V/Div) 3.3VOUT (2V/Div) 1.5VOUT (1V/Div) Time (250μs/Div) Time (2.5ms/Div) Power Off PERST Asserted by SYSRST When Power is On When Card Removed SYSRST (2V/Div) AUXOUT (2V/Div) RCLKEN (2V/Div) PERST (2V/Div) PERST (2V/Div) Time (50μs/Div) Time (500ns/Div) PERST DE-Asserted by SYSRST Power Off from AUXIN R L(3.3OUT) = 3.6Ω, R L(1.5OUT) = 2.7Ω, RL(AUXOUT) = 12Ω, CL(3.3/1.5/AUXOUT) = 68μF When Power is On 3.3VOUT (5V/Div) SYSRST (2V/Div) AUXOUT (5V/Div) 1.5VOUT (2V/Div) PERST (2V/Div) AUXIN (5V/Div) Time (100μs/Div) DS9725A/B-01 April 2011 When AUXIN Removed Time (5ms/Div) www.richtek.com 9 RT9725A/B FLG Response In 3.3VOUT Short Circuit Power Off from 1.5VIN R L(3.3OUT) = 3.6Ω, R L(1.5OUT) = 2.7Ω, RL(AUXOUT) = 12Ω, CL(3.3/1.5/AUXOUT) = 68μF 3.3VOUT (5V/Div) FLG (2V/Div) AUXOUT (5V/Div) 1.5VOUT (2V/Div) 1.5VIN (2V/Div) When 1.5VIN Removed I3.3OUT (1A/Div) Time (5ms/Div) Time (500μs/Div) AUXIN Switch RDS(ON) vs. Output Current 3.3V Switch RDS(ON) vs. Output Current 140 100 98 96 130 (mΩ) R DS(ON) (m ٛ) R DS(ON) (m (mΩ) ¬) 135 125 120 94 92 90 88 86 84 115 82 110 80 25 50 75 100 125 150 175 200 225 250 275 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 Output Current (A) Output Current (mA) Switch RDS(ON) vs. Temperature 1.5V Switch RDS(ON) vs. Output Current 90 170 88 160 I1.5V = 0.65A, I3.3V = 1.3A, IAUX = 0.275A 150 86 AUXIN 84 R DS(ON) (mΩ) (m ∪ ) (mΩ) R DS(ON) (m ∪) 140 82 80 78 76 130 3.3VIN 120 110 100 1.5VIN 90 80 74 70 72 70 0.05 60 50 0.15 0.25 0.35 0.45 Output Current (A) www.richtek.com 10 0.55 0.65 -50 -25 0 25 50 75 100 Temperature (°C) DS9725A/B-01 April 2011 RT9725A/B AUXIN Quiescent Current vs. Temperature 220 3.3VIN & 1.5VIN Quiescent Current vs. Temperature 30 No Load Quiescent Current (uA) Quiescent Current (uA) 210 200 190 180 170 160 No Load 25 3.3VIN 20 15 10 1.5VIN 5 0 150 -50 -25 0 25 50 75 -50 100 -25 0 50 75 100 Temperature (°C) Temperature (°C) AUXIN Shutdown Current vs. Temperature 3.3VIN & 1.5VIN Shutdown Current vs. Temperature 20 200 18 Shutdown Current (uA) 190 Shutdown Current (uA) 25 180 170 160 150 140 16 14 12 10 3.3VIN 8 6 4 2 1.5VIN 0 130 -50 -25 0 25 50 75 -50 100 -25 0 Temperature (°C) 25 50 75 100 Temperature (°C) 3.3VOUT Current Limit vs. Temperature AUXOUT Current Limit vs. Temperature 0.6 2.0 1.9 1.8 Current Limit (A) Current Limit (A) 0.5 0.4 0.3 0.2 1.7 1.6 1.5 1.4 1.3 1.2 0.1 1.1 0 1.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature (°C) DS9725A/B-01 April 2011 -40 -20 0 20 40 60 80 Temperature (°C) www.richtek.com 11 RT9725A/B 1.5VOUT Current Limit vs. Temperature AUXIN UVLO Threshold vs. Temperature 1.3 3.4 1.2 3.2 UVLO Threshold (V) Current Limit (A) 1.1 1.0 0.9 0.8 0.7 0.6 3.0 Rising 2.8 2.6 Falling 2.4 2.2 0.5 0.4 2.0 -40 -20 0 20 40 60 80 -40 -20 0 3.3VIN UVLO Threshold vs. Temperature 40 60 80 100 1.5VIN UVLO Threshold vs. Temperature 3.4 2.0 3.2 1.8 3.0 Rising 2.8 2.6 Falling 2.4 2.2 UVLO Threshold (V) UVLO Threshold (V) 20 Temperature (°C) Temperature (°C) 1.6 1.4 Rising 1.2 1.0 Falling 0.8 0.6 2.0 0.4 -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 Temperature (°C) Temperature (°C) FLG Delay Time vs. Temperature 13.0 FLG Delay Time (ms) 12.5 12.0 11.5 11.0 10.5 10.0 9.5 9.0 -40 -20 0 20 40 60 80 Temperature (°C) www.richtek.com 12 DS9725A/B-01 April 2011 RT9725A/B Applications Information Power States OFF Mode The following conditions define the operation of the host power controller : Shutdown Mode 1. When both primary power and auxiliary power at the input of the ExpressCard power switch are off, then all power to the ExpressCard connector is off regardless of whether a card is present. If AUXIN is available and SHDN is asserted (logic low), then all input-to-output power switches will be kept off and the output discharge FETs will be turned on. If SHDN is asserted and then de-asserted, the state on the output will be resumed to the state prior to SHDN assertion. 2. When both primary power and auxiliary power at the input of the ExpressCard power switch are on, then power is only applied to the ExpressCard after the ExpressCard power switch detects that a card is present. No Card Mode 3. When primary power (either +3.3 V or +1.5 V) at the input of the ExpressCard power switch is off and auxiliary power at the input of the ExpressCard power switch is on, then the ExpressCard power switch behaves in the following manner : If AUXIN is not available, and then all input-to-output power switches will be kept off. If 3.3VIN, AUXIN and 1.5VIN are all available at the input of the power switch and no card is inserted, then all input-tooutput power switches will be kept off and the output discharge FETs will be turned on. Card Inserted Mode If 3.3VIN, AUXIN and 1.5VIN are available at the input of the power switch before a card is inserted, then all inputto-output power switches will be turned on once a cardpresent signal (CPUSB and/or CPPE) is detected. Standby Mode 1. If a card is existed and all output voltages are being applied, then the STBY is asserted (logic low); the AUXOUT voltage is provided to the card, and the 3.3VOUT and 1.5VOUT switches will be turned off. a. If neither of the Card Present inputs is detected (no card inserted), then no power is applied to the ExpressCard slot. b. If the card is inserted after the system has entered this power state, then no power is applied to the ExpressCard slot. c. If the card is inserted prior to the removal of the primary power (either +3.3 V or +1.5 V or both) at the input of the ExpressCard power switch, then only the primary power (both +3.3 V and +1.5 V) is removed and the auxiliary power is sent to the ExpressCard slot. 2. If a card is existed and all output voltages are being applied, then the 1.5VIN or 3.3VIN is removed from the input of the power switch; the AUXOUT voltage is provided to the card and the 3.3VOUT and 1.5VOUT switches will be turned off. ExpressCard Power Switch Operation The ExpressCard power switch resides on the host, and its main function is to control when to send power to the ExpressCard slot. The ExpressCard power switch makes decisions based on the Card Present inputs and on the state of the host system as defined by the primary and auxiliary voltage rails. DS9725A/B-01 April 2011 www.richtek.com 13 RT9725A/B Express Card Timing Diagrams Host Power (AUXIN / 3.3VIN / 1.5VIN) SYSRST a CPUSB / CPPE Card Power (AUXOUT / 3.3VOUT / 1.5VOUT) Tpd RCLKEN a b PERST d c e b c d e Min Max System Dependent -100 -10 100 --20 Units Min ---- Units ms ms ms μs ms μs ms Figure 1. Card Present Before Host Power Host Power (AUXIN / 3.3VIN / 1.5VIN) SYSRST CPUSB / CPPE Card Power (AUXOUT / 3.3VOUT / 1.5VOUT) RCLKEN a PERST b c Tpd a b c Max 100 10 20 Figure 2. Host Power is On Prior to Card Insertion Host Power (AUXIN) Host Power (3.3VIN / 1.5VIN) SYSRST CPUSB / CPPE Card Power (AUXOUT / 3.3VOUT / 1.5VOUT) RCLKEN PERST Figure 3. Host System In Standby Prior to Card Insertion www.richtek.com 14 DS9725A/B-01 April 2011 RT9725A/B Host Power (AUXIN / 3.3VIN / 1.5VIN) a SYSRST CPUSB / CPPE Card Power (AUXOUT / 3.3VOUT / 1.5VOUT) Tpd b a RCLKEN c b PERST d c d Min Max System Dependent Load Dependent -500 -500 Units Min Max System Dependent System Dependent Load Dependent -500 -500 Units Min Max Load Dependent -500 -500 Units ns ns Figure 4. Host Controlled Power Down Host Power (AUXIN / 3.3VIN / 1.5VIN) a SHDN CPUSB / CPPE b Card Power (AUXOUT / 3.3VOUT / 1.5VOUT) Tpd c a RCLKEN b d c PERST e d e ns ns Figure 5. Controlled Power Down when SHDN Asserted Host Power (AUXIN / 3.3VIN / 1.5VIN) SYSRST CPUSB / CPPE Tpd Card Power (AUXOUT / 3.3VOUT / 1.5VOUT) a a b c RCLKEN ns ns b PERST c Figure 6. Surprise Card Removal DS9725A/B-01 April 2011 www.richtek.com 15 RT9725A/B Thermal Considerations For continuous operation, do not exceed absolute maximum operation junction temperature. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : PD(MAX) = ( TJ(MAX) − TA ) / θJA Where T J(MAX) is the maximum operation junction temperature, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of RT9725, The maximum junction temperature is 125°C. The junction to ambient thermal resistance θJA is layout dependent. For WQFN-20L 3x3 packages, the thermal resistance θJA is 60°C/W on the standard JEDEC 51-7 four layers thermal test board. The maximum power dissipation at TA = 25°C can be calculated by following formula : PD(MAX) = (125°C − 25°C) / (60°C/W) = 1.667W for WQFN-20L 3x3 The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θJA. For RT9725 package, the Figure 7 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power dissipation allowed. Maximum Power Dissipation (W) 1.8 Four Layers PCB 1.6 1.4 1.2 WQFN -20 3x3 1.0 0.8 0.6 0.4 0.2 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 7. Derating Curves for RT9725 Package www.richtek.com 16 DS9725A/B-01 April 2011 RT9725A/B Outline Dimension 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 D 2.900 3.100 0.114 0.122 D2 1.650 1.750 0.065 0.069 E 2.900 3.100 0.114 0.122 E2 1.650 1.750 0.065 0.069 e L 0.400 0.350 0.016 0.450 0.014 0.018 W-Type 20L QFN 3x3 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. DS9725A/B-01 April 2011 www.richtek.com 17