SANYO LC717A10AR

Ordering number : ENA2161
CMOS LSI
LC717A10AR
Capacitance-Digital-Converter LSI
for Electrostatic Capacitive Touch
Sensors
Overview
The LC717A10AR is a high-performance and low-cost capacitance-digital-converter LSI for electrostatic capacitive
touch sensor, especially focused on usability.
It has 16 channels capacitance-sensor input. This makes it ideal for use in the products that need many switches.
Since the calibration function and the judgment of ON/OFF are automatically performed in LSI internal, it can make
development time more short. A detection result (ON/OFF) for each input can be read out by the serial interface (I2C
compatible bus or SPI).
Also, measurement value of each input can be read out as 8-bit digital data. Moreover, gain and other parameters can
be adjusted using serial interface.
Features
• Detection system: Differential capacitance detection (Mutual capacitance type)
• Input capacitance resolution: Can detect capacitance changes in the femto Farad order
• Measurement interval (16 differential inputs): 30ms (Typ) (at initial configuration),
6ms (Typ) (at minimum interval configuration)
• External components for measurement: Not required
• Interface: I2C * compatible bus or SPI selectable.
• Current consumption: 570μA (Typ) (VDD = 2.8V), 1.3mA (Typ) (VDD = 5.5V)
• Supply voltage: 2.6V to 5.5V
• Detection operations: Switch
• Packages: VCT28
* I2C Bus is a trademark of Philips Corporation.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment. The products mentioned herein
shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life,
aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system,
safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives
in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any
guarantee thereof. If you should intend to use our products for new introduction or other application different
from current conditions on the usage of automotive device, communication device, office equipment, industrial
equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the
intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely
responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer ' s products or
equipment.
Ver1.0.1
D1912HKPC 20121129-S00004 No.A2161-1/11
LC717A10AR
Specifications
Absolute Maximum Ratings at Ta = +25°C
Parameter
Symbol
Supply voltage
VDD
Input voltage
Ratings (VSS = 0V)
Unit
-0.3 to +6.5
V
VIN
-0.3 to VDD+0.3
V
Output voltage
VOUT
-0.3 to VDD+0.3
V
Power dissipation
Pd max
Storage temperature
Tstg
160
mW
Remarks
*1
*2
Ta = +105°C,
Mounted on a substrate *3
°C
-55 to +125
*1) Apply to Cin0 to 15, Cref, CrefAdd, nRST, SCL, SDA, SA0, SA1, SCK, SI, nCS
*2) Apply to Cdrv, SDA, SO, INTOUT
*3) 4-layer glass epoxy board (40×50×0.8t mm)
Recommended Operating Conditions
Parameter
Symbol
Operating supply voltage
VDD
Supply ripple + noise
Vpp
Operating temperature
Topr
Conditions
min
typ
max
2.6
-40
25
Unit
5.5
V
±20
mV
105
°C
Remarks
*1
*1) We recommend connecting large and small capacitance between VDD and VSS.
In this case, the small capacitance is equal to or more than 0.1μF, and layout nearby LSI.
Electrical Characteristics at VSS = 0V, VDD = 2.6 to 5.5V, Ta = -40 to +105°C
* Unless otherwise specified, the Cdrv drive frequency is fCDRV = 143kHz.
* Not tested at low temperature before shipment.
Parameter
Symbol
Capacitance detection resolution
N
Output noise RMS
NRMS
Input offset capacitance
CoffRANGE
Conditions
min
typ
minimum gain setting
±1.0
CoffRESO
adjustment resolution
Cin offset drift
CinDRIFT
minimum gain setting
Cin detection sensitivity
CinSENSE
minimum gain setting
Cin pin leak current
ICin
Cin = Hi-Z
Cin allowable parasitic input
CinSUB
Cin against VSS
fCDRV
*1 *3
±8.0
pF
*1 *3
8
bit
LSB
*1
0.12
±8
LSB/fF
*2
±500
nA
30
pF
143
186
kHz
±25
±500
nA
μs
*1
20
ms
*1
ms
*1
V
*1
V/ms
*1
0.04
±25
Cdrv pin leak current
ICDRV
nRST minimum pulse width
tNRST
Power-on reset time
tPOR
Power-on reset operation
tPOROP
100
Cdrv = Hi-Z
1
10
condition: Hold time
Power-on reset operation
VPOROP
0.1
condition: Input voltage
Power-on reset operation
tVDD
0V to VDD
1
Remarks
bit
LSB
capacitance
Cdrv drive frequency
Unit
8
adjustment range
Input offset capacitance
max
*1 *3
condition: Power supply rise rate
Continued to the next page.
No.A2161-2/11
LC717A10AR
Continued from the previous page.
Parameter
Pin input voltage
Pin output voltage
Symbol
Conditions
VIH
High input
VIL
Low input
VOH
High output
(IOH = +3mA)
VOL
min
typ
0.2VDD
VOL I2C
Low output
ILEAK
Current consumption
IDD
Remarks
V
*1 *4
V
*5
0.2VDD
SDA Low output
0.4
V
±1
μA
*6
570
700
μA
*1 *3
1.3
1.6
mA
*1 *3
1
μA
*3
(IOL = -3mA)
Pin leak current
Unit
0.8VDD
(IOL = -3mA)
SDA pin output voltage
max
0.8VDD
When initial setting and
non-touch
VDD = 2.8V
When initial setting and
non-touch
ISTBY
VDD = 5.5V
During Sleep process
*1) Design guarantee values (not tested before shipment)
*2) Measurements conducted using the test mode in the LSI
*3) Ta = +25°C
*4) Apply to nRST, SCL, SDA, SA0, SA1, SCK, SI, nCS
*5) Apply to Cdrv, SO, INTOUT
*6) Apply to nRST, SCL, SDA, SA0, SA1, SCK, SI, nCS
No.A2161-3/11
LC717A10AR
I2C Compatible Bus Timing Characteristics at VSS = 0, VDD = 2.6 to 5.5V, Ta = -40 to +105°C
*Not tested at low temperature before shipment
Parameter
Symbol
Pin Name
SCL clock frequency
fSCL
SCL
START condition hold time
tHD;STA
SCL
Conditions
min
typ
max
Unit
400
SDA
kHz
0.6
μs
SCL clock low period
tLOW
SCL
1.3
μs
SCL clock high period
tHIGH
SCL
0.6
μs
Repeated START condition
tSU;STA
SCL
0.6
μs
setup time
SDA
Data hold time
tHD;DAT
SCL
0
SDA
Data setup time
tSU;DAT
SCL
100
SDA
SDA, SCL rise/fall time
tr / tf
0.9
SCL
300
SDA
STOP condition setup time
tSU;STO
SCL
SDA
STOP-to-START bus release
tBUF
time
SCL
SDA
Remarks
*1
μs
μs
*1
μs
*1
0.6
μs
1.3
μs
*1
Unit
Remarks
*1) Design guarantee values (not tested before shipment)
SPI Bus Timing Characteristics at VSS = 0, VDD = 2.6 to 5.5V, Ta = -40 to +105°C
*Not tested at low temperature before shipment
Parameter
SCK clock frequency
Symbol
fSCK
Pin Name
Conditions
min
typ
SCK
max
5
MHz
SCK clock Low time
tLOW
SCK
90
ns
*1
SCK clock High time
tHIGH
SCK
90
ns
*1
Input signal rise/fall time
tr / tf
ns
*1
90
ns
*1
90
ns
*1
20
ns
*1
30
ns
*1
90
ns
*1
90
ns
*1
90
ns
*1
80
ns
*1
80
ns
*1
0
ns
*1
0
ns
*1
nCS
SCK
300
SI
nCS setup time
tSU;NCS
nCS
SCK
SCK clock setup time
tSU;SCK
nCS
SCK
Data setup time
tSU;SI
SCK
SI
Data hold time
tHD;SI
SCK
SI
nCS hold time
tHD;NCS
nCS
SCK
SCK clock hold time
tHD;SCK
nCS
SCK
nCS standby pulse width
tCPH
nCS
Output high impedance time
tCHZ
nCS
from nCS
Output data determination time
SO
tv
SCK
SO
Output data hold time
tHD;SO
SCK
SO
Output low impedance time
from SCK clock
tCLZ
SCK
SO
*1) Design guarantee values (not tested before shipment)
No.A2161-4/11
LC717A10AR
Power-on Reset (POR)
When power is turned on, power-on reset is enabled inside the LSI and its state is released after a certain power-on reset
time, tPOR. Power-on Reset operation condition; Power supply rise rate tVDD must be at least 1V/ms.
Since INTOUT pin changes from “High” to “Low” at the same time as the released of power-on reset, it is possible to
verify the timing of release of power-on reset externally.
During power-on reset, Cin, Cref and CrefAdd are unknown.
VDD
tVDD
VPOROP
tPOR
tPOR
tPOROP
POR
(LSI internal signal)
RESET
UNKNOWN
RELEASE
INTOUT
VALID
Cin,
Cref,
CrefAdd
UNKNOWN
RESET
RELEASE
UNKNOWN
UNKNOWN
VALID
fig.1
I2C Compatible Bus Data Timing
90%
SDA
10%
90%
10%
tHD;DTA
tLOW
tSU;DTA
90% 90%
10%
tSU;STA
90%
SCL
tHD;STA
10%
tHIGH
tr
10%
tHD;STA
90%
10% 10%
90%
90%
90%
tBUF
10%
tSU;STO
90%
10%
tf
repeated START
condition
START
condition
STOP
condition
START
condition
fig.2
I2C Compatible Bus Communication Formats
• Write format (data can be written into sequentially incremented addresses)
START
Slave Address
Write=L ACK
Register Address (N)
Slave
ACK Data written to Register Address (N) ACK Data written to Register Address (N+1) ACK STOP
Slave
Slave
Slave
fig.3
• Read format (data can be read from sequentially incremented addresses)
START
Slave Address
Write=L ACK
Slave
RESTART
Slave Address
Register Address (N)
ACK
Slave
Read=H ACK Data read from Register Address (N) ACK Data read from Register Address (N+1) ACK Data read from Register Address (N+2) NACK STOP
Slave
Master
Master
Master
fig.4
No.A2161-5/11
LC717A10AR
I2C Compatible Bus Slave Address
Selection of two kinds of addresses is possible through the SA0 and SA1 terminals.
SA1 input
SA0 input
7bit slave address
Low
Low
0x16
Low
High
0x17
High
Low
0x18
High
High
0x19
Binary notation
8bit slave address
00101100b (Write)
0x2C
00101101b (Read)
0x2D
00101110b (Write)
0x2E
00101111b (Read)
0x2F
00110000b (Write)
0x30
00110001b (Read)
0x31
00110010b (Write)
0x32
00110011b (Read)
0x33
SPI Data Timing (SPI Mode 0 / Mode 3)
tCPH
nCS
tSU;SCK
tSU;NCS
tHIGH
tHD;NCS
tf
tr
tLOW
tHD;SCK
SCK
tSU;SI
tHD;SI
VALID
SI
tCLZ
SO
tHD;SO
tCHZ
VALID
Hi-Z
tV
fig.5
SPI Communication Formats (Example of Mode 0)
• Write format (data can be written into sequentially incremented addresses with preserving nCS = L)
nCS
SCK
SI
SO
Write=L
7 6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Data written to Register Address(N)
Register Address(N)
7
6
5
4
3
2
1
0
Data written to Register Address(N+1)
Hi-Z
fig.6
• Read format (data can be read from sequentially incremented addresses with preserving nCS = L)
nCS
SCK
SI
Read=H
7 6 5
4
3
2
1
0
Register Address(N)
SO
Hi-Z
7
6
5
4
3
2
1
0
Data read from Register Address(N)
7
6
5
4
3
2
1
0
7
Data read from Register Address(N+1)
fig.7
No.A2161-6/11
LC717A10AR
Package Dimensions
[LC717A10AR]
unit : mm (typ)
3357
TOP VIEW
SIDE VIEW
BOTTOM VIEW
(0.125)
(0.09)
3.5
0.4
3.5
(C0.09)
28
2 1
0.19
0.4
(0.55)
(0.035)
0.8
SIDE VIEW
SANYO : VCT28(3.5X3.5)
Pin Assignment
Pin No.
Pin Name
Pin No.
Pin Name
1
Cin0
15
Cin12
2
Cin1
16
Cin13
3
Cin2
17
Cin14
4
Cin3
18
Cin15
5
VDD
19
Cref
6
VSS
20
CrefAdd
7
Cin4
21
Cdrv
8
Cin5
22
INTOUT
9
Cin6
23
SA1
10
Cin7
24
SCL/SCK
11
Cin8
25
SDA/SI
SA0/SO
12
Cin9
26
13
Cin10
27
nCS
14
Cin11
28
nRST
No.A2161-7/11
LC717A10AR
Block Diagram
Cin0
Cin1
Cin2
Cin3
VDD
Cin4
VSS
Cin5
Cin6
1st
AMP
Cin7
Cin8
2nd
AMP
A/D
CONVERTER
MUX
Cin9
Cin10
Cin11
Cdrv
CONTROL
LOGIC
Cin12
INTOUT
Cin13
nRST
Cin14
Cin15
nCS
POR
OSCILLATOR
SCL/SCK
2
I C/SPI
Cref
CrefAdd
MUX
SDA/SI
SA0/SO
SA1
LC717A10AR is capacitance-digital-converter LSI capable of detecting changes in capacitance in the order of femto
Farads. It consists of an oscillation circuit that generates the system clock, a power-on reset circuit that resets the system
when the power is turned on, a multiplexer that selects the input channels, a two-stage amplifier that detects the changes
in the capacitance and outputs analog-amplitude values, a A/D converter that converts the analog-amplitude values into
digital data, an I2C compatible bus or a SPI that enables serial communication with external devices and a control logic
that controls the entire chip.
No.A2161-8/11
LC717A10AR
Pin Functions
Pin Name
I/O
Pin Functions
Cin0
I/O
Capacitance sensor input
Cin1
I/O
Capacitance sensor input
Cin2
I/O
Capacitance sensor input
Cin3
I/O
Capacitance sensor input
Cin4
I/O
Capacitance sensor input
Cin5
I/O
Capacitance sensor input
Cin6
I/O
Capacitance sensor input
Cin7
I/O
Capacitance sensor input
Cin8
I/O
Capacitance sensor input
Cin9
I/O
Capacitance sensor input
Cin10
I/O
Capacitance sensor input
Cin11
I/O
Capacitance sensor input
Cin12
I/O
Capacitance sensor input
Cin13
I/O
Capacitance sensor input
Cin14
I/O
Capacitance sensor input
Cin15
I/O
Capacitance sensor input
Cref
I/O
Reference capacitance input
CrefAdd
I/O
Reference capacitance input for addition
Pin Type
VDD
AMP
R
VSS
Buffer
VDD
Cdrv
O
Output for capacitance sensors drive
Buffer
INTOUT
O
Interrupt output
VSS
Clock input (I2C)
SCL/SCK
I
nCS
I
nRST
I
External reset signal inverting input
SA1
I
Slave address selection (I2C)
/ Clock input (SPI)
VDD
Interface selection
R
/ Chip select inverting input (SPI)
VSS
VDD
R
SDA/SI
I/O
Data input and output (I2C)
/ Data input (SPI)
VSS
Continued to the next page.
No.A2161-9/11
LC717A10AR
Continued from the previous page.
Pin Name
I/O
Pin Functions
Pin Type
VDD
SA0/SO
I/O
R
Slave address selection (I2C)
/ Data output (SPI)
VSS
VDD
Power supply (2.6V to 5.5V) *1
VSS
Ground (Earth) *1 *2
Buffer
*1) Inserting a high-valued capacitor and a low-valued capacitor in parallel between VDD and VSS is recommended.
In this case, the small-valued capacitor should be at least 0.1μF, and is mounted near the LSI.
*2) When VSS terminal is not grounded in battery-powered mobile equipment, detection sensitivity may be degraded.
Details of Pin Functions
●Cin0 to Cin15
These are the capacitance-sensor-input pins. These pins are used by connecting them to the touch switch pattern.
Cin and the Cdrv wire patterns should be close to each other. By doing so, Cdrv and Cin patterns are capacitively
coupled. Therefore, LSI can detect capacitance change near each pattern as 8bit digital data.
However, if the shape of each pattern or the capacitively coupled value of Cdrv is not appropriate, it may not be able
to detect the capacitance change correctly.
In this LSI, there is a two-stage amplifier that detects the changes in the capacitance and outputs analog-amplitude
values. Cin0 to Cin15 are connected to the inverting input of the 1st amplifier.
During measurement process, channels other than the one being measured are all in “Low” condition.
Leave the unused terminals open.
●Cref, CrefAdd
These are the reference-capacitance-input pins. These are used by connecting to the wire pattern like Cin pins or are
used by connecting any capacitance between this pin and Cdrv pin.
In this LSI, there is a two-stage amplifier that detects the changes in the capacitance and outputs analog-amplitude
values. Cref is connected to the non-inverting input of the 1st amplifier.
Due to the parasitic capacitance generated in the wire connections of Cin pins and their patterns, as well as the one
generated between the wire patterns of Cin and Cdrv pins, Cref may not detect capacitance change of each Cin pin
accurately. In this case, connect an appropriate capacitance between Cref and Cdrv to detect capacitance change
accurately.
However, if the difference between the parasitic capacitance of each Cin pin is extremely large, it may not detect
capacitance change of each Cin pin correctly.
CrefAdd can be used as additional terminal for Cref. Leave the CrefAdd open if not in used.
●Cdrv
It is the output pin for capacitance sensors drive. It outputs the pulse voltage which is needed to detect capacitance at
Cin0 to Cin15.
Cdrv and Cin wire patterns should be close to each other so that they are capacitively coupled.
●INTOUT
It is the interrupt-output pin.
It is used by connecting to a main microcomputer if necessary, and use as interrupt signal. (High Active)
Leave the terminal open if not in used.
●SCL/SCK
Clock input (I2C) / Clock input (SPI)
It is the clock input pin of the I2C compatible bus or the SPI depending on the mode of operation.
No.A2161-10/11
LC717A10AR
●nCS
Interface selection / Chip-select-inverting input (SPI)
Selection of I2C compatible bus mode or SPI mode is through this terminal. After initialization, the LSI is
automatically in I2C compatible bus mode. To continually use I2C compatible bus mode, fix nCS pin to “High”. To
switch to SPI mode after LSI initialization, change the nCS input “High” → “Low”. The nCS pin is used as the chipselect-inverting input pin of SPI, and SPI mode is kept until LSI is again initialized.
●nRST
It is the external-reset-signal-inverting-input pin. When nRST pin is “Low”, LSI is in reset state.
Each pin (Cin0 to 15, Cref, CrefAdd) is “Hi-Z” during reset state.
●SDA/SI
Data input and output (I2C) / Data input (SPI)
It is the data input and output pin of the I2C compatible bus or the data input pin of the SPI depending on the mode of
operation.
●SA0/SO
Slave address selection (I2C) / Data output (SPI)
It is the slave address selection pin of the I2C compatible bus or the data output pin of the SPI depending on the mode
of operation.
●SA1
Slave address selection (I2C)
It is the slave address selection pin of the I2C compatible bus.
When SPI mode, connect to the SA1 pin to GND.
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
Regarding monolithic semiconductors, if you should intend to use this IC continuously under high temperature,
high current, high voltage, or drastic temperature change, even if it is used within the range of absolute
maximum ratings or operating conditions, there is a possibility of decrease reliability. Please contact us for a
confirmation.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
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without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellectual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of December, 2012. Specifications and information herein are subject
to change without notice.
PS No.A2161-11/11