SANYO LC75897PW

Ordering number : EN*A0549
CMOS IC
LC75897PW
1/3, 1/4-Duty General-Purpose
LCD Display Driver
Overview
The LC75897PW is 1/3 duty and 1/4 duty general-purpose LCD display driver that can be used for frequency display in
electronic tuners under the control of a microcontroller. The LC75897PW can drive an LCD with up to 512 segments
directly. The LC75897PW can also control up to 8 general-purpose output ports. The LC75897PW has a built-in of up to
three PWM output port channels, which enables to adjust the brightness of the RGB LED backlight.
Features
• Switching between 1/3 duty and 1/4 duty drive techniques under serial data control.
• Switching between 1/2 bias and 1/3 bias drive techniques under serial data control.
• Up to 387 segments for 1/3 duty drive and 512 segments for 1/4 duty drive can be displayed.
• Switching between the segment, general-purpose, PWM, and clock output ports can be controlled using serial data
(up to 8 general-purpose output ports, up to 3-channel PWM output ports, and one clock output port).
• Serial data input supports CCB format communication with the system controller.
• Serial data control of the power-saving mode based backup function and all the segments forced off function.
• Serial data control of the frame frequency for common and segment output waveforms.
• Serial data control of switching between the RC oscillator operating mode and external clock operating mode.
• High generality, since display data is displayed directly without decoder intervention.
• Built-in display contrast adjustment circuit
• Independent VLCD for the LCD driver block
• The INH pin can force the display to the off state.
• RC oscillator circuit
•
•
CCB is a trademark of SANYO Electric Co., Ltd.
CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
41807HKIM No.A0549-1/34
LC75897PW
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0V
Parameter
Maximum supply voltage
Input voltage
Output voltage
Output current
Allowable power dissipation
Symbol
Conditions
Ratings
Unit
VDD max
VDD
-0.3 to +7.0
VLCD max
VLCD
-0.3 to +7.0
VIN1
CE, CL, DI, INH
VIN2
OSC
VIN3
VLCD1, VLCD2
V
-0.3 to +7.0
-0.3 to VDD+0.3
V
-0.3 to VLCD+0.3
VOUT1
OSC
VOUT2
VLCD0, S1 to S129, COM1 to COM4, P1 to P8
IOUT1
S1 to S129
IOUT2
COM1 to COM4
3
IOUT3
P1 to P8
5
Pd max
Ta = 85°C
-0.3 to VDD+0.3
V
-0.3 to VLCD+0.3
300
200
µA
mA
mW
Operating temperature
Topr
-40 to +85
°C
Storage temperature
Tstg
-55 to +125
°C
Allowable Operating Ranges at Ta = -40 to +85°C, VSS = 0V
Ratings
Parameter
Supply voltage
Symbol
Conditions
min
typ
unit
max
VDD
VDD
2.7
6.0
VLCD
VLCD,
VLCD0 = 0.70VLCD to 0.95VLCD
4.0
6.0
VLCD, VLCD0 = VLCD
2.7
6.0
Output voltage
VLCD0
VLCD0
2.7
VLCD
Input voltage
VLCD1
VLCD1
2/3VLCD0
VLCD0
VLCD2
VLCD2
1/3VLCD0
VLCD0
VIH1
CE, CL, DI, INH
0.8VDD
6.0
VIH2
OSC external clock operating mode
0.7VDD
VDD
VIL1
CE, CL, DI, INH
0
0.2VDD
VIL2
OSC external clock operating mode
0
0.3VDD
ROSC
OSC RC oscillator operating mode
COSC
OSC RC oscillator operating mode
Guaranteed range of RC oscillation
fOSC
OSC RC oscillator operating mode
External clock operating frequency
fCK
OSC external clock operating mode
Input high-level voltage
Input low-level voltage
Recommended external resistor
for RC oscillation
Recommended external capacitor
for RC oscillation
[Figure 4]
External clock duty cycle
DCK
OSC external clock operating mode
[Figure 4]
Data setup time
tds
Data hold time
tdh
CE wait time
tcp
CE setup time
tcs
CE hold time
High-level clock pulse width
Low-level clock pulse width
tφL
CL,DI
V
V
V
V
V
10
kΩ
470
pF
150
300
600
kHz
150
300
600
kHz
30
50
70
%
[Figure 2],[ Figure 3]
160
ns
CL,DI
[Figure 2],[ Figure 3]
160
ns
CE,CL
[Figure 2],[ Figure 3]
160
ns
CE,CL
[Figure 2],[ Figure 3]
160
ns
tch
CE,CL
[Figure 2],[ Figure 3]
160
ns
tφH
CL
[Figure 2],[ Figure 3]
160
ns
CL
[Figure 2],[ Figure 3]
160
ns
Rise time
tr
CE, CL, DI
[Figure 2],[ Figure 3]
160
ns
Fall time
tf
CE, CL, DI
[Figure 2],[ Figure 3]
160
ns
INH switching time
tc
INH, CE
[Figure 5],[ Figure 6]
10
µs
No.A0549-2/34
LC75897PW
Electrical Characteristics for the Allowable Operating Ranges
Parameter
Symbol
Pin
Conditions
Hysteresis
VH
CE, CL, DI, INH
Input high-level current
IIH1
CE, CL, DI, INH
VI = 6.0V
IIH2
OSC
VI = VDD
Ratings
min
typ
0.1VDD
IIL1
CE, CL, DI, INH
VI = 0V
IIL2
OSC
VI = 0V
5.0
Output low-level voltage
Output middle-level
VOH1
IO = -20µA
VLCD0-0.9
VLCD0-0.9
VOH2
COM1 to COM4
IO = -100µA
P1 to P8
IO = -1mA
VOL1
S1 to S129
IO = 20µA
0.9
VOL2
COM1 to COM4
IO = 100µA
0.9
VOL3
P1 to to P8
IO = 1mA
0.9
VMID1
COM1 to COM4
1/2 bias, IO = ±100µA
1/2VLCD0
+0.9
2/3VLCD0
S1 to S129
1/3 bias, IO = ±20µA
2/3VLCD0
-0.9
+0.9
VMID3
S1 to S129
1/3 bias, IO = ±20µA
1/3VLCD0
1/3VLCD0
-0.9
+0.9
2/3VLCD0
2/3VLCD0
VMID5
fOSC
COM1 to COM4
1/3 bias, IO = ±100µA
COM1 to COM4
1/3 bias, IO = ±100µA
OSC
RC oscillator operating mode
-0.9
+0.9
1/3VLCD0
1/3VLCD0
-0.9
+0.9
ROSC = 10kΩ
COSC = 470pF
210
IDD1
VDD
Power-saving mode
IDD2
VDD
VDD = 6.0V, output open,
fOSC = 300kHz
ILCD1
VLCD
Power-saving mode
ILCD2
VLCD
VLCD = 6.0V, output open,
1/2 bias, fOSC = 300kHz,
V
1/2VLCD0
-0.9
VMID2
VMID4
Current drain
V
VLCD-0.9
voltage *1
Oscillator frequency
µA
-5.0
S1 to S129
VOH3
µA
-5.0
External clock operating mode
Output high-level voltage
V
5.0
External clock operating mode
Input low-level current
unit
max
300
390
V
kHz
10
700
1400
15
600
1200
500
1000
450
900
350
700
VLCD0 = 0.70VLCD to 0.95VLCD
ILCD3
VLCD
VLCD = 6.0V, output open,
1/2 bias, fOSC = 300kHz,
µA
VLCD0 = VLCD
ILCD4
VLCD
VLCD = 6.0V, output open,
1/3 bias, fOSC = 300kHz,
VLCD0 = 0.70VLCD to 0.95VLCD
ILCD5
VLCD
VLCD = 6.0V, output open,
1/3 bias, fOSC = 300kHz,
VLCD0 = VLCD
Note: *1 Excluding the bias voltage generation divider resistors built in the VLCD0, VLCD1, VLCD2, and VSS.
(See Figure 1.)
VLCD
CONTRAST
ADJUSTER
VLCD0
VLCD1
To the common and segment drivers
VLCD2
VSS
Except these resistors.
Figure 1
No.A0549-3/34
LC75897PW
≈
1. When CL is stopped at the low level
VIH1
CE
≈
VIL1
tφL
≈
tf
tcp
tch
tcs
≈ ≈
DI
tr
≈ ≈
CL
≈
tφH
VIH1
50%
VIL1
VIH1
VIL1
tdh
tds
Figure 2
≈
2. When CL is stopped at the high level
VIH1
CE
≈
VIL1
tφH
VIH1
50%
VIL1
tf
≈
CL
≈
tφL
tr
tch
tcs
≈ ≈
≈ ≈
tcp
VIH1
VIL1
DI
tds
tdh
Figure 3
3. OSC pin clock timing in external clock operating mode
tCKH
OSC
VIH2
50%
VIL2
tCKL
fCK =
1
tCKH+ tCKL
[kHz]
tCKH
×100[%]
DCK =
tCKH+ tCKL
Figure 4
No.A0549-4/34
LC75897PW
Package Dimensions
unit : mm (typ)
3214A
22.0
0.5
20.0
73
72
144
37
20.0
109
1
36
0.5
0.2
22.0
108
0.145
0.1
1.6max
(1.4)
(1.25)
SANYO : SQFP144 (20X20)
S108
S107
S106
S105
S104
S103
S102
S101
S100
S99
S98
S97
S96
S95
S94
S93
S92
S91
S90
S89
S88
S87
S86
S85
S84
S83
S82
S81
S80
S79
S78
S77
S76
S75
S74
S73
Pin Assignment
108
73
72
109
S109
S110
S111
S112
S113
S114
S115
S116
S117
S118
S119
S120
S121
S122
S123
S124
S125
S126
S127
S128
S129/COM4
COM3
COM2
COM1
VDD
VLCD
VLCD0
VLCD1
VLCD2
VSS
VSS
OSC
INH
CE
CL
DI
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
LC75897PW
1
36
P1/S1
P2/S2
P3/S3
P4/S4
P5/S5
P6/S6
P7/S7
P8/S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
144
37
Top view
No.A0549-5/34
LC75897PW
COMMON
DRIVER
S1/P1
S2/P2
S8/P8
S9
S128
S127
COM4/S129
COM3
COM2
COM1
Block Diagram
SEGMENT DRIVER & LATCH
INH
OSC
CLOCK
GENERATOR
CONTROL
REGISTER
VDD
VLCD
SHIFT REGISTER
CONTRAST
ADJUSTER
VLCD0
CCB INTERFACE
VLCD1
VLCD2
CE
CL
DI
VSS
No.A0549-6/34
LC75897PW
Pin Functions
Handling
Symbol
Pin No.
Function
Active
I/O
when
unused
S1/P1 to S8/P8
1 to 8
Segment outputs for displaying the display data transferred by serial data
S9 to S128
9 to 128
input. Also, by the control data, S1/P1 to S3/P3 can be used as a general-
-
O
OPEN
-
O
OPEN
-
I/O
VDD
H
I
GND
purpose output port or PWM output port, while S4/P4 can be used as a
general-purpose output port or clock output port and S5/P5 to S8/P8 can be
used as a general-purpose output port.
COM1 to COM3
132 to 130
COM4/S129
129
OSC
140
Common driver outputs. The frame frequency is fo [Hz]. The COM4/S129 pin
can be used as a segment output in 1/3 duty.
Oscillator connection. An oscillator circuit is formed by connecting an
external resistor and capacitor to this pin. This pin can also be used as the
external clock input pin as controlled by control data.
CE
142
Serial data transfer inputs. These pins are connected to the control
CL
143
microprocessor.
DI
144
I
CE: Chip enable
-
I
L
I
GND
-
O
OPEN
-
I
OPEN
-
I
OPEN
CL: Synchronization clock
DI: Transfer data
INH
141
Display off control input
• INH = low (VSS) ...Off
S1/P1 to S8/P8 = low (VSS)
(These pins are forcibly set to the segment output port
function and fixed at the VSS level.)
S9 to S128 = low (VSS)
COM1 to COM3 = low (VSS)
COM4/S129 = low (VSS)
OSC = "Z" (high impedance)
RC oscillation stopped
External clock input inhibited
Display contrast adjustment circuit stopped
• INH = high (VDD) ...On
RC oscillation enabled (RC oscillator operating mode)
Enables external clock input (external clock operating
mode).
Display contrast adjustment circuit enabled
Note that serial data transfers can be performed when the display is forced
off by this pin.
VLCD0
135
LCD drive 3/3 bias voltage (high level) supply. This level can be modified
using the display contrast adjustment circuit. However, note that VLCD0
must be greater than or equal to 2.7V. Also, since this IC provides the builtin display contrast adjustment circuit, applications must not attempt to
provide this level from external circuits.
VLCD1
136
LCD drive 2/3 bias voltage (middle level) supply. It is possible to supply the
2/3VLCD0 voltage to this pin externally. This pin must be shorted to VLCD2
if 1/2 bias is used.
VLCD2
137
LCD drive 1/3 bias voltage (middle level) supply. It is possible to supply the
1/3VLCD0 voltage to this pin externally. This pin must be shorted to VLCD1
if 1/2 bias is used.
VDD
133
Logic block power supply. Provide a voltage in the range 2.7 to 6.0V.
-
-
-
VLCD
134
LCD driver block power supply. When VLCD0 is between 0.70VLCD and
0.95VLCD, supply a voltage in the range 4.0 to 6.0V. When VLCD0 and
-
-
-
-
-
-
VLCD will be equal, supply a voltage in the range 2.7 to 6.0V.
VSS
138,139
Ground pin. Connect to ground.
No.A0549-7/34
LC75897PW
Serial Data Transfer Formats
(1) 1/3 duty
1. When CL is stopped at the low level
• When the display data is transferred
CL
DI
0
1
1
0
0
0
0
1
D1
D112 D113 D114 D115 D116D117 D118 D119 D120 D121 D122 D123 D124D125 D126 D127D128 D129 0
0
0
0
0
0
1
∼ ∼ ∼
∼
CE
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Fixed data
4 bits
DD
3 bits
∼
0
1
1
0
0
0
0
1
D130
D241 D242 D243 D244 D245D246 D247 D248 D249 D250 D251 D252 D253D254 D255 D256 D257 D258 0
0
0
0
0
1
0
∼ ∼ ∼
∼ ∼ ∼
∼
Display data
129 bits
B0 B1 B2 B3 A0 A1 A2 A3
Display data
129 bits
Fixed data
4 bits
DD
3 bits
∼ ∼ ∼
∼
CCB address
8 bits
0
1
1
0
0
0
0
1
D259
D370 D371 D372 D373 D374D375 D376 D377 D378 D379 D380 D381 D382D383 D384 D385 D386 D387 0
0
0
0
0
1
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
129 bits
Fixed data
4 bits
DD
3 bits
• When the control data is transferred
CE
CL
DI
0
1
1
0
0
0
0
1
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
53 bits
PS10 PS11 PS20 PS21 PS30 PS31 PS40 PS41 PS5 PS6 PS7 PS8 CT0 CT1 CT2 DR DT OC FC0 FC1 FC2 PF0 PF1 PF2 SC BU 0
0
0
0
DD
3 bits
Note: DD is the direction data.
No.A0549-8/34
LC75897PW
2. When CL is stopped at the high level
• When the display data is transferred
∼ ∼
CE
DI
0
1
1
0
0
0
0
1
D1
D112 D113 D114 D115 D116D117 D118 D119 D120 D121 D122 D123 D124D125 D126 D127 D128 D129 0
0
0
0
0
0
1
∼ ∼
CL
B0 B1 B2 B3 A0 A1 A2 A3
Display data
129 bits
Fixed data
4 bits
DD
3 bits
0
1
1
0
0
0
0
1
D130
D241 D242 D243 D244 D245D246 D247 D248 D249 D250 D251 D252 D253D254 D255 D256 D257 D258 0
0
0
0
0
1
0
∼ ∼
∼ ∼
∼ ∼
∼ ∼
CCB address
8 bits
B0 B1 B2 B3 A0 A1 A2 A3
Display data
129 bits
Fixed data
4 bits
DD
3 bits
∼ ∼
∼ ∼
CCB address
8 bits
0
1
1
0
0
0
0
1
D259
D370 D371 D372 D373 D374D375 D376 D377 D378 D379 D380 D381 D382D383 D384 D385 D386 D387 0
0
0
0
0
1
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
129 bits
Fixed data
4 bits
DD
3 bits
No.A0549-9/34
LC75897PW
• When the control data is transferred
CE
CL
DI
0
1
1
0
0
0
0
1
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
53 bits
PS10 PS11 PS20 PS21 PS30 PS31 PS40 PS41 PS5 PS6 PS7 PS8 CT0 CT1 CT2 DR DT OC FC0 FC1 FC2 PF0 PF1 PF2 SC BU 0
0
0
0
DD
3 bits
Note: DD is the direction data.
• CCB address ....... "86H"
• D1 to D387 ......... Display data
• W10 to W15, W20 to W25, W30 to W35
......... PWM data at PWM output ports
• PC1 to PC8 ......... General-purpose output port state setting control data
• PS10, PS11, PS20, PS21, PS30, PS31, PS40, PS41, PS5 to PS8
......... Segment output port/general-purpose output port/PWM output port/clock output port switching
control data
• CT0 to CT2 ......... Display contrast setting control data
• DR ...................... 1/2 bias drive or 1/3 bias drive switching control data
• DT ...................... 1/3 duty drive or 1/4 duty drive switching control data
• OC ...................... RC oscillator operating mode/external clock operating mode switching control data
• FC0 to FC2 ......... Common and segment output waveforms frame frequency setting control data
• PF0 to PF2 ......... PWM output waveforms frame frequency setting control data
• SC ...................... Segments on/off control data
• BU ...................... Normal mode/power-saving mode control data
No.A0549-10/34
LC75897PW
(2) 1/4 duty
1. When CL is stopped at the low level
• When the display data is transferred
CL
DI
0
1
1
0
0
0
0
1
D1
D112 D113 D114 D115 D116D117 D118 D119 D120 D121 D122 D123 D124D125 D126 D127 D128 0
0
0
0
0
0
0
1
∼ ∼ ∼
∼
CE
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Fixed data
5 bits
DD
3 bits
∼
0
1
1
0
0
0
0
1
D129
D240 D241 D242 D243 D244D245 D246 D247 D248 D249 D250 D251 D252D253 D254 D255D256 0
0
0
0
0
0
1
0
∼ ∼ ∼
∼ ∼ ∼
∼
Display data
128 bits
B0 B1 B2 B3 A0 A1 A2 A3
Display data
128 bits
Fixed data
5 bits
DD
3 bits
∼
0
1
1
0
0
0
0
1
D257
D368 D369 D370 D371 D372D373 D374 D375 D376 D377 D378 D379 D380D381 D382 D383 D384 0
0
0
0
0
0
1
1
∼ ∼ ∼
∼ ∼ ∼
∼
CCB address
8 bits
B0 B1 B2 B3 A0 A1 A2 A3
Display data
128 bits
Fixed data
5 bits
DD
3 bits
∼ ∼ ∼
∼
CCB address
8 bits
0
1
1
0
0
0
0
1
D385
D496 D497 D498 D499 D500D501 D502 D503 D504 D505 D506 D507 D508D509 D510 D511 D512 0
0
0
0
0
1
0
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
128 bits
Fixed data
5 bits
DD
3 bits
• When the control data is transferred
CE
CL
DI
0
1
1
0
0
0
0
1
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
53 bits
PS10 PS11 PS20 PS21 PS30 PS31 PS40 PS41 PS5 PS6 PS7 PS8 CT0 CT1 CT2 DR DT OC FC0 FC1 FC2 PF0 PF1 PF2 SC BU 0
0
0
0
DD
3 bits
Note: DD is the direction data.
No.A0549-11/34
LC75897PW
2. When CL is stopped at the high level
• When the display data is transferred
∼ ∼
CE
DI
0
1
1
0
0
0
0
1
D1
D112 D113 D114 D115 D116D117 D118 D119 D120 D121 D122 D123 D124D125 D126 D127D128 0
0
0
0
0
0
0
1
∼ ∼
CL
B0 B1 B2 B3 A0 A1 A2 A3
Display data
128 bits
Fixed data
5 bits
DD
3 bits
∼ ∼
0
1
1
0
0
0
0
1
D129
D240 D241 D242 D243 D244D245 D246 D247 D248 D249 D250 D251 D252D253 D254 D255 D256 0
0
0
0
0
0
1
0
∼ ∼
∼ ∼
∼ ∼
CCB address
8 bits
B0 B1 B2 B3 A0 A1 A2 A3
Display data
128 bits
Fixed data
5 bits
DD
3 bits
∼ ∼
0
1
1
0
0
0
0
1
D257
D368 D369 D370 D371 D372D373 D374 D375 D376 D377 D378 D379 D380D381 D382 D383 D384 0
0
0
0
0
0
1
1
∼ ∼
∼ ∼
∼ ∼
CCB address
8 bits
B0 B1 B2 B3 A0 A1 A2 A3
Display data
128 bits
Fixed data
5 bits
DD
3 bits
∼ ∼
0
1
1
0
0
0
0
1
D385
D496 D497 D498 D499 D500D501 D502 D503 D504 D505 D506 D507 D508D509 D510 D511 D512 0
0
0
0
0
1
0
0
∼ ∼
∼ ∼
∼ ∼
CCB address
8 bits
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
128 bits
Fixed data
5 bits
DD
3 bits
No.A0549-12/34
LC75897PW
• When the control data is transferred
CE
CL
DI
0
1
1
0
0
0
0
1
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
53 bits
PS10 PS11 PS20 PS21 PS30 PS31 PS40 PS41 PS5 PS6 PS7 PS8 CT0 CT1 CT2 DR DT OC FC0 FC1 FC2 PF0 PF1 PF2 SC BU 0
0
0
0
DD
3 bits
Note: DD is the direction data.
• CCB address ....... "86H"
• D1 to D512 ......... Display data
• W10 to W15, W20 to W25, W30 to W35
......... PWM data at PWM output ports
• PC1 to PC8 ......... General-purpose output port state setting control data
• PS10, PS11, PS20, PS21, PS30, PS31, PS40, PS41, PS5 to PS8
......... Segment output port/general-purpose output port/PWM output port/clock output port switching
control data
• CT0 to CT2 ......... Display contrast setting control data
• DR ...................... 1/2 bias drive or 1/3 bias drive switching control data
• DT ...................... 1/3 duty drive or 1/4 duty drive switching control data
• OC ...................... RC oscillator operating mode/external clock operating mode switching control data
• FC0 to FC2 ......... Common and segment output waveforms frame frequency setting control data
• PF0 to PF2 ......... PWM output waveforms frame frequency setting control data
• SC ...................... Segments on/off control data
• BU ...................... Normal mode/power-saving mode control data
No.A0549-13/34
LC75897PW
Serial Data Transfer Example
(1) 1/3 duty
• When 259 or more segments are used
All 496 bits of serial data (including CCB addresses) must be sent.
56 bits
8 bits
0 1 1 0 0 0 0 1
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8
B0 B1 B2 B3 A0 A1 A2 A3
PS10 PS11 PS20 PS21PS30 PS31 PS40 PS41 PS5 PS6 PS7 PS8 CT0 CT1 CT2 DR DT OC FC0 FC1 FC2 PF0 PF1 PF2 SC BU 0 0 0 0
8 bits
136 bits
0 1 1 0 0 0 0 1
D1
D112 D113 D114 D115 D116 D117 D118 D119 D120 D121 D122 D123 D124 D125 D126 D127 D128 D129 0 0 0 0 0 0 1
0 1 1 0 0 0 0 1
B0 B1 B2 B3 A0 A1 A2 A3
D130
D241 D242 D243 D244 D245 D246 D247 D248 D249 D250 D251 D252 D253 D254 D255 D256 D257 D258 0 0 0 0 0 1 0
0 1 1 0 0 0 0 1
B0 B1 B2 B3 A0 A1 A2 A3
D259
D370 D371 D372 D373 D374 D375 D376 D377 D378 D379 D380 D381 D382 D383 D384 D385 D386 D387 0 0 0 0 0 1 1
B0 B1 B2 B3 A0 A1 A2 A3
• When fewer than 259 segments are used
Either 208 or 352 bits (including CCB addresses) of serial data may be sent, depending on the number of
segments used. However, the serial data shown below (control data) must be sent.
56 bits
8 bits
0 1 1 0 0 0 0 1
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8
B0 B1 B2 B3 A0 A1 A2 A3
PS10 PS11 PS20 PS21PS30 PS31 PS40 PS41 PS5 PS6 PS7 PS8 CT0 CT1 CT2 DR DT OC FC0 FC1 FC2 PF0 PF1 PF2 SC BU 0 0 0 0
No.A0549-14/34
LC75897PW
(2) 1/4 duty
• When 385 or more segments are used
All 640 bits of serial data (including CCB addresses) must be sent.
56 bits
8 bits
0 1 1 0 0 0 0 1
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8
B0 B1 B2 B3 A0 A1 A2 A3
PS10 PS11 PS20PS21 PS30 PS31 PS40 PS41 PS5 PS6 PS7 PS8 CT0 CT1 CT2 DR DT OC FC0 FC1 FC2 PF0 PF1 PF2 SC BU 0 0 0 0
136 bits
8 bits
0 1 1 0 0 0 0 1
D1
D112 D113 D114 D115 D116 D117 D118 D119 D120 D121 D122 D123 D124 D125 D126 D127 D128 0 0 0 0 0 0 0 1
0 1 1 0 0 0 0 1
B0 B1 B2 B3 A0 A1 A2 A3
D129
D240 D241 D242 D243 D244 D245 D246 D247 D248 D249 D250 D251 D252 D253 D254 D255 D256 0 0 0 0 0 0 1 0
0 1 1 0 0 0 0 1
B0 B1 B2 B3 A0 A1 A2 A3
D257
D368 D369 D370 D371 D372 D373 D374 D375 D376 D377 D378 D379 D380 D381 D382 D383 D384 0 0 0 0 0 0 1 1
0 1 1 0 0 0 0 1
B0 B1 B2 B3 A0 A1 A2 A3
D385
D496 D497 D498 D499 D500 D501 D502 D503 D504 D505 D506 D507 D508 D509 D510 D511 D512 0 0 0 0 0 1 0 0
B0 B1 B2 B3 A0 A1 A2 A3
• When fewer than 385 segments are used
Either 208, 352 or 496 bits (including CCB addresses) of serial data may be sent, depending on the number of
segments used. However, the serial data shown below (control data) must be sent.
56 bits
8 bits
0 1 1 0 0 0 0 1
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8
B0 B1 B2 B3 A0 A1 A2 A3
PS10 PS11 PS20PS21 PS30 PS31 PS40 PS41 PS5 PS6 PS7 PS8 CT0 CT1 CT2 DR DT OC FC0 FC1 FC2 PF0 PF1 PF2 SC BU 0 0 0 0
No.A0549-15/34
LC75897PW
Control Data Functions
(1) W10 to W15, W20 to W25, W30 to W35: PWM data at PWM output ports
This control data determines the pulse width of the PWM at PWM output ports P1/S1 to P3/S3.
Pulse width of
Wn0
Wn1
Wn2
Wn3
Wn4
Wn5
Pulse width of
PWM output
Wn0
Wn1
Wn2
Wn3
Wn4
Wn5
port Pn
PWM output
port Pn
0
0
0
0
0
0
(1/64)×Tp
0
0
0
0
0
1
(33/64)×Tp
1
0
0
0
0
0
(2/64)×Tp
1
0
0
0
0
1
(34/64)×Tp
0
1
0
0
0
0
(3/64)×Tp
0
1
0
0
0
1
(35/64)×Tp
1
1
0
0
0
0
(4/64)×Tp
1
1
0
0
0
1
(36/64)×Tp
0
0
1
0
0
0
(5/64)×Tp
0
0
1
0
0
1
(37/64)×Tp
1
0
1
0
0
0
(6/64)×Tp
1
0
1
0
0
1
(38/64)×Tp
0
1
1
0
0
0
(7/64)×Tp
0
1
1
0
0
1
(39/64)×Tp
1
1
1
0
0
0
(8/64)×Tp
1
1
1
0
0
1
(40/64)×Tp
0
0
0
1
0
0
(9/64)×Tp
0
0
0
1
0
1
(41/64)×Tp
1
0
0
1
0
0
(10/64)×Tp
1
0
0
1
0
1
(42/64)×Tp
0
1
0
1
0
0
(11/64)×Tp
0
1
0
1
0
1
(43/64)×Tp
1
1
0
1
0
0
(12/64)×Tp
1
1
0
1
0
1
(44/64)×Tp
0
0
1
1
0
0
(13/64)×Tp
0
0
1
1
0
1
(45/64)×Tp
1
0
1
1
0
0
(14/64)×Tp
1
0
1
1
0
1
(46/64)×Tp
0
1
1
1
0
0
(15/64)×Tp
0
1
1
1
0
1
(47/64)×Tp
1
1
1
1
0
0
(16/64)×Tp
1
1
1
1
0
1
(48/64)×Tp
0
0
0
0
1
0
(17/64)×Tp
0
0
0
0
1
1
(49/64)×Tp
1
0
0
0
1
0
(18/64)×Tp
1
0
0
0
1
1
(50/64)×Tp
0
1
0
0
1
0
(19/64)×Tp
0
1
0
0
1
1
(51/64)×Tp
1
1
0
0
1
0
(20/64)×Tp
1
1
0
0
1
1
(52/64)×Tp
0
0
1
0
1
0
(21/64)×Tp
0
0
1
0
1
1
(53/64)×Tp
1
0
1
0
1
0
(22/64)×Tp
1
0
1
0
1
1
(54/64)×Tp
0
1
1
0
1
0
(23/64)×Tp
0
1
1
0
1
1
(55/64)×Tp
1
1
1
0
1
0
(24/64)×Tp
1
1
1
0
1
1
(56/64)×Tp
0
0
0
1
1
0
(25/64)×Tp
0
0
0
1
1
1
(57/64)×Tp
1
0
0
1
1
0
(26/64)×Tp
1
0
0
1
1
1
(58/64)×Tp
0
1
0
1
1
0
(27/64)×Tp
0
1
0
1
1
1
(59/64)×Tp
1
1
0
1
1
0
(28/64)×Tp
1
1
0
1
1
1
(60/64)×Tp
0
0
1
1
1
0
(29/64)×Tp
0
0
1
1
1
1
(61/64)×Tp
1
0
1
1
1
0
(30/64)×Tp
1
0
1
1
1
1
(62/64)×Tp
0
1
1
1
1
0
(31/64)×Tp
0
1
1
1
1
1
(63/64)×Tp
1
1
1
1
1
0
(32/64)×Tp
1
1
1
1
1
1
(64/64)×Tp
Note: Wn0 to Wn5 (n = 1 to 3): PWM data at output pins S1/P1 to S3/P3
Tp =
1
fp
(2) PC1 to PC8: General-purpose output port state setting control data
This control data is used to set the high/low state of general-purpose output ports P1 to P8.
Output pins
P1
P2
P3
P4
P5
P6
P7
P8
Control data
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
Note: PCn = 1: The output pin Pn is set high (VLCD) (n = 1 to 8).
PCn = 0: The output pin Pn is set low (VSS) (n = 1 to 8).
For example, if output pins S4/P4 and S5/P5 are selected as general-purpose output ports, setting PC4 to 1 and PC5 to 0
causes the output pin P4 to be set high (VLCD) and P5 to be set low (VSS).
No.A0549-16/34
LC75897PW
(3) PS10, PS11, PS20, PS21, PS30, PS31, PS40, PS41, PS5 to PS8: Segment output port/general-purpose output
port/PWM output port/clock output port switching control data
This control data is used to set the state of output pins S1/P1 to S8/P8.
PS10 and PS11: Output pin (S1/P1) state settings
PS10
PS11
0
0
1
0
0
1
PS20 and PS21: Output pin (S2/P2) state settings
Output pin (S1/P1) state
PS20
PS21
Segment output port (S1)
0
0
Segment output port (S2)
General-purpose output port (P1)
1
0
General-purpose output port (P2)
PWM output port (P1)
0
1
PWM output port (P2)
PS30 and PS31: Output pin (S3/P3) state settings
PS30
PS31
0
0
1
0
0
1
PWM output port (P3)
Output pin (S2/P2) state
PS40 and PS41: Output pin (S4/P4) state settings
Output pin (S3/P3) state
PS40
PS41
Segment output port (S3)
0
0
Segment output port (S4)
General-purpose output port (P3)
1
0
General-purpose output port (P4)
0
1
1
1
PS5: Output pin (S5/P5) state settings
PS5
Output pin (S4/P4) state
Clock output port (P4)
(clock frequency fosc/2, fCK/2)
Clock output port (P4)
(clock frequency fosc/8, fCK/8)
PS6: Output pin (S6/P6) state settings
Output pin (S5/P5) state
PS6
Output pin (S6/P6) state
0
Segment output port (S5)
0
Segment output port (S6)
1
General-purpose output port (P5)
1
General-purpose output port (P6)
PS7: Output pin (S7/P7) state settings
PS7
PS8: Output pin (S8/P8) state settings
Output pin (S7/P7) state
PS8
Output pin (S8/P8) state
0
Segment output port (S7)
0
Segment output port (S8)
1
General-purpose output port (P7)
1
General-purpose output port (P8)
For example, if PS10 and PS11 are set to 0 and 1 respectively, PS20 and PS21 to 0 and 1 respectively, PS30 and PS31
to 0 and 1 respectively, PS40 and PS41 to 1 and 0 respectively, PS5 to 1, PS6 to 1, PS7 to 0, and PS8 to 0, the output
pins S1/P1 to S3/P3 are selected as PWM output ports, the output pins S4/P4 to S6/P6 as general-purpose output ports,
and the output pins S7/P7 and S8/P8 as segment output ports.
(4) CT0 to CT2: Display contrast setting control data
This control data is used to set the display contrast.
CT0 to CT2: Display contrast settings (7 steps)
CT0
CT1
CT2
0
0
0
1.00VLCD = VLCD- (0.05VLCD×0)
Level of LCD drive bias 3/3 voltage power supply VLCD0
1
0
0
0.95VLCD = VLCD- (0.05VLCD×1)
0
1
0
0.90VLCD = VLCD- (0.05VLCD×2)
1
1
0
0.85VLCD = VLCD- (0.05VLCD×3)
0
0
1
0.80VLCD = VLCD- (0.05VLCD×4)
1
0
1
0.75VLCD = VLCD- (0.05VLCD×5)
0
1
1
0.70VLCD = VLCD- (0.05VLCD×6)
Note that although the contrast of the display can be adjusted by running the internal display contrast adjustment circuit,
it is also possible to adjust it by changing the voltage level on the LCD driver block power supply VLCD pin. However,
VLCD0 must always be greater than or equal to 2.7V.
(5) DR: 1/2 bias drive or 1/3 bias drive switching control data
This control data bit selects either 1/2 bias drive or 1/3 bias drive.
DR
Bias drive scheme
0
1/3 bias drive
1
1/2 bias drive
No.A0549-17/34
LC75897PW
(6) DT: 1/3 duty drive or 1/4 duty drive switching control data
This control data bit selects either 1/3 duty drive or 1/4 duty drive.
DT
Duty drive scheme
Output pin state (COM4/S129)
0
1/4 duty drive
COM4
1
1/3 duty drive
S129
Note: COM4: Common output
S129: Segment output
(7) OC: RC oscillator operating mode/external clock operating mode switching control data
This control data bit selects either RC oscillator operating mode or external clock operating mode.
OC
OSC pin function
0
RC oscillator operating mode
1
External clock operating mode
Note: When selecting the RC oscillator operating mode, be sure to connect an external resistor Rosc and an external
capacitor Cosc to the OSC pin.
(8) FC0 to FC2: Common and segment output waveforms frame frequency setting control data
This control data bits set the frame frequency for the common and segment output waveforms.
Control data
Common/segment output waveform
FC0
FC1
FC2
frame frequency fo [Hz]
0
0
0
fosc/6144, fCK/6144
1
0
0
fosc/4608, fCK/4608
0
1
0
fosc/3072, fCK/3072
1
1
0
fosc/2304, fCK/2304
0
0
1
fosc/1536, fCK/1536
(9) PF0 to PF2: PWM output waveforms frame frequency setting control data
This control data bits set the frame frequency for the PWM output waveforms.
Control data
PWM output waveform
PF0
PF1
PF2
frame frequency fp [Hz]
0
0
0
fosc/1536, fCK/1536
1
0
0
fosc/1408, fCK/1408
0
1
0
fosc/1280, fCK/1280
1
1
0
fosc/1152, fCK/1152
0
0
1
fosc/1024, fCK/1024
1
0
1
fosc/896, fCK/896
0
1
1
fosc/768, fCK/768
1
1
1
fosc/640, fCK/640
(10) SC: Segments on/off control data
This control data bit controls the on/off state of the segments.
SC
Display state
0
On
1
Off
However, note that the segments are turned off by setting SC to 1, the segments are turned off by outputing segment off
waveforms from the segment output pins.
(11) BU: Normal mode/power-saving mode control data
This control data bit selects either normal mode or power-saving mode.
BU
0
Mode
Normal mode
Power save mode
The LC75897PW stops the oscillation at the OSC pin if it is set up for the RC oscillator operating mode (OC = 0) and stops
1
receiving the external clock if it is set up for the external clock operating mode (OC = 1). The IC also sets the common and
segment output pins to the VSS level. The output pins S1/P1 to S8/P8, however, remain available as general-purpose
output ports as configured by control data bits PS10, PS11, PS20, PS21, PS30, PS31, PS40, PS41, and PS5 to PS8 (not
available as PWM output or clock output ports).
No.A0549-18/34
LC75897PW
Display Data to Segment Output Pin Correspondence
1. 1/3 duty
Segment
COM1
COM2
COM3
S1/P1
D1
D2
D3
S2/P2
D4
D5
D6
S3/P3
D7
D8
S4/P4
D10
S5/P5
D13
S6/P6
Segment
COM1
COM2
COM3
S44
D130
D131
D132
S45
D133
D134
D135
D9
S46
D136
D137
D11
D12
S47
D139
D14
D15
S48
D142
D16
D17
D18
S49
S7/P7
D19
D20
D21
S8/P8
D22
D23
D24
S9
D25
D26
S10
D28
S11
S12
Segment
COM1
COM2
COM3
S87
D259
D260
D261
S88
D262
D263
D264
D138
S89
D265
D266
D267
D140
D141
S90
D268
D269
D270
D143
D144
S91
D271
D272
D273
D145
D146
D147
S92
D274
D275
D276
S50
D148
D149
D150
S93
D277
D278
D279
S51
D151
D152
D153
S94
D280
D281
D282
D27
S52
D154
D155
D156
S95
D283
D284
D285
D29
D30
S53
D157
D158
D159
S96
D286
D287
D288
D31
D32
D33
S54
D160
D161
D162
S97
D289
D290
D291
D34
D35
D36
S55
D163
D164
D165
S98
D292
D293
D294
S13
D37
D38
D39
S56
D166
D167
D168
S99
D295
D296
D297
S14
D40
D41
D42
S57
D169
D170
D171
S100
D298
D299
D300
S15
D43
D44
D45
S58
D172
D173
D174
S101
D301
D302
D303
S16
D46
D47
D48
S59
D175
D176
D177
S102
D304
D305
D306
S17
D49
D50
D51
S60
D178
D179
D180
S103
D307
D308
D309
S18
D52
D53
D54
S61
D181
D182
D183
S104
D310
D311
D312
S19
D55
D56
D57
S62
D184
D185
D186
S105
D313
D314
D315
S20
D58
D59
D60
S63
D187
D188
D189
S106
D316
D317
D318
S21
D61
D62
D63
S64
D190
D191
D192
S107
D319
D320
D321
S22
D64
D65
D66
S65
D193
D194
D195
S108
D322
D323
D324
S23
D67
D68
D69
S66
D196
D197
D198
S109
D325
D326
D327
S24
D70
D71
D72
S67
D199
D200
D201
S110
D328
D329
D330
S25
D73
D74
D75
S68
D202
D203
D204
S111
D331
D332
D333
S26
D76
D77
D78
S69
D205
D206
D207
S112
D334
D335
D336
S27
D79
D80
D81
S70
D208
D209
D210
S113
D337
D338
D339
S28
D82
D83
D84
S71
D211
D212
D213
S114
D340
D341
D342
S29
D85
D86
D87
S72
D214
D215
D216
S115
D343
D344
D345
S30
D88
D89
D90
S73
D217
D218
D219
S116
D346
D347
D348
S31
D91
D92
D93
S74
D220
D221
D222
S117
D349
D350
D351
S32
D94
D95
D96
S75
D223
D224
D225
S118
D352
D353
D354
Output pins
Output pins
Output pins
S33
D97
D98
D99
S76
D226
D227
D228
S119
D355
D356
D357
S34
D100
D101
D102
S77
D229
D230
D231
S120
D358
D359
D360
S35
D103
D104
D105
S78
D232
D233
D234
S121
D361
D362
D363
S36
D106
D107
D108
S79
D235
D236
D237
S122
D364
D365
D366
S37
D109
D110
D111
S80
D238
D239
D240
S123
D367
D368
D369
S38
D112
D113
D114
S81
D241
D242
D243
S124
D370
D371
D372
S39
D115
D116
D117
S82
D244
D245
D246
S125
D373
D374
D375
S40
D118
D119
D120
S83
D247
D248
D249
S126
D376
D377
D378
S41
D121
D122
D123
S84
D250
D251
D252
S127
D379
D380
D381
S42
D124
D125
D126
S85
D253
D254
D255
S128
D382
D383
D384
S43
D127
D128
D129
S86
D256
D257
D258
COM4/S129
D385
D386
D387
Note: This applies to the case where the S1/P1 to S8/P8, and COM4/S129 output pins are set to be segment output
ports.
No.A0549-19/34
LC75897PW
For example, the table below lists the segment output states for the S11 output pin.
Display data
Segment output pin (S11) state
D31
D32
D33
0
0
0
The LCD segments corresponding to COM1, COM2, and COM3 are off.
0
0
1
The LCD segment corresponding to COM3 is on.
0
1
0
The LCD segment corresponding to COM2 is on.
0
1
1
The LCD segments corresponding to COM2 and COM3 are on.
1
0
0
The LCD segment corresponding to COM1 is on.
1
0
1
The LCD segments corresponding to COM1 and COM3 are on.
1
1
0
The LCD segments corresponding to COM1 and COM2 are on.
1
1
1
The LCD segments corresponding to COM1, COM2, and COM3 are on.
2. 1/4 duty
Segment
COM1
COM2
COM3
COM4
S1/P1
D1
D2
D3
D4
S2/P2
D5
D6
D7
D8
S3/P3
D9
D10
D11
S4/P4
D13
D14
S5/P5
D17
D18
S6/P6
D21
S7/P7
S8/P8
Segment
COM1
COM2
COM3
COM4
S37
D145
D146
D147
D148
S38
D149
D150
D151
D152
D12
S39
D153
D154
D155
D156
D15
D16
S40
D157
D158
D159
D160
D19
D20
S41
D161
D162
D163
D164
D22
D23
D24
S42
D165
D166
D167
D168
D25
D26
D27
D28
S43
D169
D170
D171
D172
D29
D30
D31
D32
S44
D173
D174
D175
D176
S9
D33
D34
D35
D36
S45
D177
D178
D179
D180
S10
D37
D38
D39
D40
S46
D181
D182
D183
D184
S11
D41
D42
D43
D44
S47
D185
D186
D187
D188
S12
D45
D46
D47
D48
S48
D189
D190
D191
D192
S13
D49
D50
D51
D52
S49
D193
D194
D195
D196
S14
D53
D54
D55
D56
S50
D197
D198
D199
D200
S15
D57
D58
D59
D60
S51
D201
D202
D203
D204
S16
D61
D62
D63
D64
S52
D205
D206
D207
D208
S17
D65
D66
D67
D68
S53
D209
D210
D211
D212
S18
D69
D70
D71
D72
S54
D213
D214
D215
D216
S19
D73
D74
D75
D76
S55
D217
D218
D219
D220
S20
D77
D78
D79
D80
S56
D221
D222
D223
D224
S21
D81
D82
D83
D84
S57
D225
D226
D227
D228
S22
D85
D86
D87
D88
S58
D229
D230
D231
D232
S23
D89
D90
D91
D92
S59
D233
D234
D235
D236
S24
D93
D94
D95
D96
S60
D237
D238
D239
D240
S25
D97
D98
D99
D100
S61
D241
D242
D243
D244
S26
D101
D102
D103
D104
S62
D245
D246
D247
D248
S27
D105
D106
D107
D108
S63
D249
D250
D251
D252
S28
D109
D110
D111
D112
S64
D253
D254
D255
D256
S29
D113
D114
D115
D116
S65
D257
D258
D259
D260
S30
D117
D118
D119
D120
S66
D261
D262
D263
D264
S31
D121
D122
D123
D124
S67
D265
D266
D267
D268
S32
D125
D126
D127
D128
S68
D269
D270
D271
D272
S33
D129
D130
D131
D132
S69
D273
D274
D275
D276
S34
D133
D134
D135
D136
S70
D277
D278
D279
D280
S35
D137
D138
D139
D140
S71
D281
D282
D283
D284
S36
D141
D142
D143
D144
S72
D285
D286
D287
D288
Output pins
Output pins
Continued on next page.
No.A0549-20/34
LC75897PW
Continued from preceding page.
Segment
COM1
COM2
COM3
COM4
S73
D289
D290
D291
D292
S74
D293
D294
D295
D296
S75
D297
D298
D299
S76
D301
D302
S77
D305
S78
D309
S79
Segment
COM1
COM2
COM3
COM4
S101
D401
D402
D403
D404
S102
D405
D406
D407
D408
D300
S103
D409
D410
D411
D412
D303
D304
S104
D413
D414
D415
D416
D306
D307
D308
S105
D417
D418
D419
D420
D310
D311
D312
S106
D421
D422
D423
D424
D313
D314
D315
D316
S107
D425
D426
D427
D428
S80
D317
D318
D319
D320
S108
D429
D430
D431
D432
S81
D321
D322
D323
D324
S109
D433
D434
D435
D436
S82
D325
D326
D327
D328
S110
D437
D438
D439
D440
S83
D329
D330
D331
D332
S111
D441
D442
D443
D444
S84
D333
D334
D335
D336
S112
D445
D446
D447
D448
S85
D337
D338
D339
D340
S113
D449
D450
D451
D452
S86
D341
D342
D343
D344
S114
D453
D454
D455
D456
S87
D345
D346
D347
D348
S115
D457
D458
D459
D460
S88
D349
D350
D351
D352
S116
D461
D462
D463
D464
S89
D353
D354
D355
D356
S117
D465
D466
D467
D468
S90
D357
D358
D359
D360
S118
D469
D470
D471
D472
S91
D361
D362
D363
D364
S119
D473
D474
D475
D476
S92
D365
D366
D367
D368
S120
D477
D478
D479
D480
S93
D369
D370
D371
D372
S121
D481
D482
D483
D484
S94
D373
D374
D375
D376
S122
D485
D486
D487
D488
S95
D377
D378
D379
D380
S123
D489
D490
D491
D492
S96
D381
D382
D383
D384
S124
D493
D494
D495
D496
S97
D385
D386
D387
D388
S125
D497
D498
D499
D500
S98
D389
D390
D391
D392
S126
D501
D502
D503
D504
Output pins
Output pins
S99
D393
D394
D395
D396
S127
D505
D506
D507
D508
S100
D397
D398
D399
D400
S128
D509
D510
D511
D512
Note: This applies to the case where the S1/P1 to S8/P8 output pins are set to be segment output ports.
For example, the table below lists the segment output states for the S11 output pin.
Display data
Segment output pin (S11) state
D41
D42
D43
D44
0
0
0
0
The LCD segments corresponding to COM1, COM2, COM3, and COM4 are off.
0
0
0
1
The LCD segment corresponding to COM4 is on.
0
0
1
0
The LCD segment corresponding to COM3 is on.
0
0
1
1
The LCD segments corresponding to COM3 and COM4 are on.
0
1
0
0
The LCD segment corresponding to COM2 is on.
0
1
0
1
The LCD segments corresponding to COM2 and COM4 are on.
0
1
1
0
The LCD segments corresponding to COM2 and COM3 are on.
0
1
1
1
The LCD segments corresponding to COM2, COM3, and COM4 are on.
1
0
0
0
The LCD segment corresponding to COM1 is on.
1
0
0
1
The LCD segments corresponding to COM1 and COM4 are on.
1
0
1
0
The LCD segments corresponding to COM1 and COM3 are on.
1
0
1
1
The LCD segments corresponding to COM1, COM3, and COM4 are on.
1
1
0
0
The LCD segments corresponding to COM1 and COM2 are on.
1
1
0
1
The LCD segments corresponding to COM1, COM2, and COM4 are on.
1
1
1
0
The LCD segments corresponding to COM1, COM2, and COM3 are on.
1
1
1
1
The LCD segments corresponding to COM1, COM2, COM3, and COM4 are on.
No.A0549-21/34
LC75897PW
Output Waveforms (1/3-Duty 1/2-Bias Drive Scheme)
fo[Hz]
VLCD0
VLCD1,VLCD2
COM1
0V
VLCD0
VLCD1,VLCD2
COM2
0V
VLCD0
VLCD1,VLCD2
COM3
0V
LCD driver output when all LCD segments
corresponding to COM1, COM2, and COM3
are turned off.
VLCD0
LCD driver output when only LCD segments
corresponding to COM1 are on.
VLCD0
VLCD1,VLCD2
0V
VLCD1,VLCD2
0V
VLCD0
VLCD1,VLCD2
LCD driver output when only LCD segments
corresponding to COM2 are on.
0V
VLCD0
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
VLCD1,VLCD2
0V
VLCD0
VLCD1,VLCD2
LCD driver output when only LCD segments
corresponding to COM3 are on.
0V
VLCD0
VLCD1,VLCD2
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
0V
VLCD0
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
VLCD1,VLCD2
0V
VLCD0
VLCD1,VLCD2
LCD driver output when all LCD segments
corresponding to COM1, COM2,
and COM3 are on.
0V
Control data
Common/segment output waveform
FC0
FC1
FC2
frame frequency fo [Hz]
0
0
0
fosc/6144, fCK/6144
1
0
0
fosc/4608, fCK/4608
0
1
0
fosc/3072, fCK/3072
1
1
0
fosc/2304, fCK/2304
0
0
1
fosc/1536, fCK/1536
No.A0549-22/34
LC75897PW
Output Waveforms (1/3-Duty 1/3-Bias Drive Scheme)
fo[Hz]
VLCD0
VLCD1
COM1
VLCD2
0V
VLCD0
VLCD1
COM2
VLCD2
0V
VLCD0
VLCD1
COM3
VLCD2
0V
VLCD0
VLCD1
LCD driver output when all LCD segments
corresponding to COM1, COM2, and COM3
are turned off.
VLCD2
0V
VLCD0
VLCD1
LCD driver output when only LCD segments
corresponding to COM1 are on.
VLCD2
0V
VLCD0
VLCD1
LCD driver output when only LCD segments
corresponding to COM2 are on.
VLCD2
0V
VLCD0
VLCD1
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
VLCD2
0V
VLCD0
VLCD1
LCD driver output when only LCD segments
corresponding to COM3 are on.
VLCD2
0V
VLCD0
VLCD1
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
VLCD2
0V
VLCD0
VLCD1
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
VLCD2
0V
VLCD0
VLCD1
LCD driver output when all LCD segments
corresponding to COM1, COM2,
and COM3 are on.
VLCD2
0V
Control data
Common/segment output waveform
FC0
FC1
FC2
frame frequency fo [Hz]
0
0
0
fosc/6144, fCK/6144
1
0
0
fosc/4608, fCK/4608
0
1
0
fosc/3072, fCK/3072
1
1
0
fosc/2304, fCK/2304
0
0
1
fosc/1536, fCK/1536
No.A0549-23/34
LC75897PW
Output Waveforms (1/4-Duty 1/2-Bias Drive Scheme)
fo[Hz]
COM1
VLCD0
VLCD1,VLCD2
0V
COM2
VLCD0
VLCD1,VLCD2
0V
COM3
VLCD0
VLCD1,VLCD2
0V
COM4
VLCD0
VLCD1,VLCD2
0V
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3,
and COM4 are turned off.
VLCD0
VLCD1,VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM1 are on.
VLCD0
VLCD1,VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM2 are on.
VLCD0
VLCD1,VLCD2
0V
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
VLCD0
VLCD1,VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM3 are on.
VLCD0
VLCD1,VLCD2
0V
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
VLCD0
VLCD1,VLCD2
0V
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
VLCD0
VLCD1,VLCD2
0V
LCD driver output when LCD segments
corresponding to COM1, COM2, and COM3 are on.
VLCD0
VLCD1,VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM4 are on.
VLCD0
VLCD1,VLCD2
0V
LCD driver output when LCD segments
corresponding to COM2 and COM4 are on.
VLCD0
VLCD1,VLCD2
0V
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3,
and COM4 are on.
VLCD0
VLCD1,VLCD2
0V
Control data
Common/segment output waveform
FC0
FC1
FC2
frame frequency fo [Hz]
0
0
0
fosc/6144, fCK/6144
1
0
0
fosc/4608, fCK/4608
0
1
0
fosc/3072, fCK/3072
1
1
0
fosc/2304, fCK/2304
0
0
1
fosc/1536, fCK/1536
No.A0549-24/34
LC75897PW
Output Waveforms (1/4-Duty 1/3-Bias Drive Scheme)
fo[Hz]
VLCD0
VLCD1
VLCD2
0V
VLCD0
VLCD1
VLCD2
0V
VLCD0
VLCD1
VLCD2
0V
VLCD0
VLCD1
VLCD2
0V
VLCD0
VLCD1
VLCD2
0V
VLCD0
VLCD1
VLCD2
0V
VLCD0
VLCD1
VLCD2
0V
VLCD0
VLCD1
VLCD2
0V
VLCD0
VLCD1
VLCD2
0V
VLCD0
VLCD1
VLCD2
0V
VLCD0
VLCD1
VLCD2
0V
VLCD0
VLCD1
VLCD2
0V
VLCD0
VLCD1
VLCD2
0V
VLCD0
VLCD1
VLCD2
0V
VLCD0
VLCD1
VLCD2
0V
COM1
COM2
COM3
COM4
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3,
and COM4 are turned off.
LCD driver output when only LCD segments
corresponding to COM1 are on.
LCD driver output when only LCD segments
corresponding to COM2 are on.
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
LCD driver output when only LCD segments
corresponding to COM3 are on.
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
LCD driver output when LCD segments
corresponding to COM1, COM2,
and COM3 are on.
LCD driver output when only LCD segments
corresponding to COM4 are on.
LCD driver output when LCD segments
corresponding to COM2 and COM4 are on.
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3,
and COM4 are on.
Control data
Common/segment output waveform
FC0
FC1
FC2
frame frequency fo [Hz]
0
0
0
fosc/6144, fCK/6144
1
0
0
fosc/4608, fCK/4608
0
1
0
fosc/3072, fCK/3072
1
1
0
fosc/2304, fCK/2304
0
0
1
fosc/1536, fCK/1536
No.A0549-25/34
LC75897PW
PWM output port waveforms
VLCD
P1
(56/64)×Tp
(1)
VSS
(56/64)×Tp
VLCD
P2
(48/64)×Tp
VSS
(48/64)×Tp
VLCD
P3
(40/64)×Tp
VSS
(40/64)×Tp
VLCD
P1
(8/64)×Tp
VSS
(8/64)×Tp
VLCD
P2
(2)
(16/64)×Tp
VSS
(16/64)×Tp
VLCD
P3
(24/64)×Tp
VSS
(24/64)×Tp
VLCD
P1
(32/64)×Tp
(3)
VSS
(32/64)×Tp
VLCD
P2
(32/64)×Tp
VSS
(32/64)×Tp
VLCD
P3
(32/64)×Tp
VSS
(32/64)×Tp
Tp
Tp
Tp=
1
fp
Control data
PWM output
W10
W11
W12
W13
W14
W15
W20
W21
W22
W23
W24
W25
W30
W31
W32
W33
W34
W35
port waveforms
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
0
0
1
(1)
1
1
1
0
0
0
1
1
1
1
0
0
1
1
1
0
1
0
(2)
1
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
(3)
Control data
PWM output waveform
PF0
PF1
PF2
frame frequency fp [Hz]
0
0
0
fosc/1536, fCK/1536
1
0
0
fosc/1408, fCK/1408
0
1
0
fosc/1280, fCK/1280
1
1
0
fosc/1152, fCK/1152
0
0
1
fosc/1024, fCK/1024
1
0
1
fosc/896, fCK/896
0
1
1
fosc/768, fCK/768
1
1
1
fosc/640, fCK/640
Clock output port P4
Control data
Clock output port waveform
clock signal frequency
PS40
PF41
0
1
Clock output port (fosc/2, fCK/2)
1
1
Clock output port (fosc/8, fCK/8)
fc (=1/Tc) [Hz]
P4
Tc=
Tc/2
1
fc
Tc
No.A0549-26/34
LC75897PW
The INH pin and Display Control
Since the IC internal data (1/3 duty: the display data D1 to D387 and the control data, 1/4 duty: the display data D1 to
D512 and the control data) is undefined when power is first applied, applications should set the INH pin low at the same
time as power is applied to turn off the display (This sets the S1/P1 to S8/P8, S9 to S128, COM1 to COM3, and
COM4/S129 to the VSS level.) and during this period send serial data from the controller. The controller should then set
the INH pin high after the data transfer has completed. This procedure prevents meaningless displays at power on. (See
Figures 5 and 6.)
Notes on the Power On/Off Sequences
Applications should observe the following sequences when turning the LC75897PW power on and off.
(See Figures 5 and 6)
• At power on: Logic block power supply (VDD) on → LCD driver block power supply (VLCD) on
• At power off: LCD driver block power supply (VLCD) off → Logic block power supply (VDD) off
However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and
off at the same time.
1. 1/3 duty
t2
≈
t1
t3
≈
VDD
≈
VLCD
INH
VIL1
CE
VIL1
≈ ≈≈ ≈ ≈ ≈ ≈≈ ≈
tc
W10 to W15, W20 to W25, W30 to W35,
PC1 to PC8, PS10, PS11, PS20,
Internal data PS21, PS30, PS31, PS40, PS41,
PS5 to PS8, CT0 to CT2, DR, DT, OC,
FC0 to FC2, PF0 to PF2, SC, BU
Undefined
Defined
Undefined
Internal data (D1 to D129)
Undefined
Defined
Undefined
Internal data (D130 to D258)
Undefined
Defined
Undefined
Internal data (D259 to D387)
Undefined
Defined
Undefined
Display data and control data transter
Note: t1≥0
t2>0
t3≥0 (t2>t3)
tc⋅⋅⋅10µs min
Figure 5
No.A0549-27/34
LC75897PW
2. 1/4 duty
t2
≈
t1
t3
≈
VDD
≈
VLCD
INH
tc
VIL1
CE
≈ ≈ ≈ ≈≈ ≈ ≈ ≈≈ ≈≈
VIL1
W10 to W15, W20 to W25, W30 to W35,
PC1 to PC8, PS10, PS11, PS20,
Internal data PS21, PS30, PS31, PS40, PS41,
PS5 to PS8, CT0 to CT2, DR, DT, OC,
FC0 to FC2, PF0 to PF2, SC, BU
Undefined
Defined
Undefined
Internal data (D1 to D128)
Undefined
Defined
Undefined
Internal data (D129 to D256)
Undefined
Defined
Undefined
Internal data (D257 to D384)
Undefined
Defined
Undefined
Internal data (D385 to D512)
Undefined
Defined
Undefined
Display data and control data transter
Note: t1≥0
t2>0
t3≥0 (t2>t3)
tc⋅⋅⋅10µs min
Figure 6
No.A0549-28/34
LC75897PW
Notes on Controller Transfer of Display Data
Since the LC75897PW accepts the display data (D1 to D387) divided into three separate transfer operations when using
1/3 duty drive scheme and the data (D1 to D512) divided into four separate transfer operations when using 1/4 duty
drive scheme, we recommend that applications transfer all of the display data within a period of less than 30ms to
prevent observable degradation of display quality.
OSC pin peripheral circuits
(1) RC oscillator operating mode (control data OC = 0)
When RC oscillator operating mode is selected, an external resistor Rosc and an external capacitor Cosc must be
connected between the OSC pin and GND.
OSC
Rosc
Cosc
(2) External clock operating mode (control data OC = 1)
When selecting the external clock operating mode, connect a current protection resistor Rg (2.2 to 22kΩ) between
the OSC pin and the external clock output pin (external oscillator). Determine the value of the resistance according
to the maximum allowable current value of the external clock output pin. Also make sure that the waveform of the
external clock is not excessively distorted.
External clock output pin
OSC
Rg
External oscillator
Note:
VDD
Allowable current value at external clock output pin >
Rg
P1 to P3 pin peripheral circuit
It is recommended the circuit shown below be used to adjust the brightness of the LED backlight using PWM output
ports P1 to P3.
+5V
LED
P1 to P3
No.A0549-29/34
LC75897PW
Sample Application Circuit 1
(P1)
1/3 Duty, 1/2 Bias (for use with normal panels)
(P2)
(P3)
(P4)
(P5)
+3.3V
VDD
OSC
*2
General-purpose
output ports
Used for functions
such as backlight
control
(P8)
COM1
VLCD
COM3
P1/S1
P2/S2
P3/S3
VLCD0
P4/S4
VLCD1
P5/S5
VLCD2
P8/S8
VSS
+5.8V
OPEN
S9
C
C≥0.047µF
INH
CE
From the controller
LCD panel (up to 387 segments)
COM2
VSS
S127
CL
S128
DI
COM4/S129
Note: *2 Connect an external resistor Rosc and an external capacitor Cosc between the OSC pin and GND when
selecting the RC oscillator operating mode and connect a current protection resistor Rg (2.2 to 22kΩ) between
the OSC pin and the external clock output pin (external oscillator) when selecting the external clock operating
mode (see the note on the OSC pin peripheral circuits).
Sample Application Circuit 2
(P1)
1/3 Duty, 1/2 Bias (for use with large panels)
(P2)
(P3)
(P4)
(P5)
+3.3V
VDD
OSC
*2
General-purpose
output ports
Used for functions
such as backlight
control
(P8)
COM1
VLCD
COM3
P1/S1
P2/S2
P3/S3
VLCD0
P4/S4
VLCD1
P5/S5
VSS
+5.8V
R
10kΩ≥R≥2.2kΩ
C≥0.047µF
From the controller
C
R
VLCD2
INH
CE
P8/S8
S9
LCD panel (up to 387 segments)
COM2
VSS
S127
CL
S128
DI
COM4/S129
Note: *2 Connect an external resistor Rosc and an external capacitor Cosc between the OSC pin and GND when
selecting the RC oscillator operating mode and connect a current protection resistor Rg (2.2 to 22kΩ) between
the OSC pin and the external clock output pin (external oscillator) when selecting the external clock operating
mode (see the note on the OSC pin peripheral circuits).
No.A0549-30/34
LC75897PW
Sample Application Circuit 3
(P1)
1/3 Duty, 1/3 Bias (for use with normal panels)
+3.3V
(P2)
(P3)
(P4)
(P5)
VDD
OSC
*2
General-purpose
output ports
Used for functions
such as backlight
control
(P8)
COM1
VLCD
COM3
P1/S1
P2/S2
P3/S3
VLCD0
P4/S4
VLCD1
P5/S5
VSS
+5.8V
OPEN
P8/S8
VLCD2
C≥0.047µF
C
S9
C
INH
CE
From the controller
LCD panel (up to 387 segments)
COM2
VSS
S127
CL
S128
DI
COM4/S129
Note: *2 Connect an external resistor Rosc and an external capacitor Cosc between the OSC pin and GND when
selecting the RC oscillator operating mode and connect a current protection resistor Rg (2.2 to 22kΩ) between
the OSC pin and the external clock output pin (external oscillator) when selecting the external clock operating
mode (see the note on the OSC pin peripheral circuits).
Sample Application Circuit 4
(P1)
1/3 Duty, 1/3 Bias (for use with large panels)
(P2)
(P3)
(P4)
(P5)
+3.3V
VDD
OSC
*2
General-purpose
output ports
Used for functions
such as backlight
control
(P8)
COM1
VSS
VLCD
+5.8V
VLCD0
R
VLCD1
R
10kΩ≥R≥2.2kΩ
C≥0.047µF
VLCD2
C
From the controller
C
R
INH
CE
COM3
P1/S1
P2/S2
P3/S3
P4/S4
P5/S5
P8/S8
S9
LCD panel (up to 387 segments)
COM2
VSS
S127
CL
S128
DI
COM4/S129
Note: *2 Connect an external resistor Rosc and an external capacitor Cosc between the OSC pin and GND when
selecting the RC oscillator operating mode and connect a current protection resistor Rg (2.2 to 22kΩ) between
the OSC pin and the external clock output pin (external oscillator) when selecting the external clock operating
mode (see the note on the OSC pin peripheral circuits).
No.A0549-31/34
LC75897PW
Sample Application Circuit 5
1/4 Duty, 1/2 Bias (for use with normal panels)
(P1)
(P2)
(P3)
(P4)
(P5)
+3.3V
VDD
OSC
*2
General-purpose
output ports
Used for functions
such as backlight
control
(P8)
COM1
COM2
VSS
+5.8V
P1/S1
P2/S2
P3/S3
VLCD
OPEN
LCD panel (up to 512 segments)
COM3
S129/COM4
VSS
VLCD0
P4/S4
VLCD1
P5/S5
VLCD2
P8/S8
C
C≥0.047µF
S9
INH
CE
From the controller
CL
S127
DI
S128
Note: *2 Connect an external resistor Rosc and an external capacitor Cosc between the OSC pin and GND when
selecting the RC oscillator operating mode and connect a current protection resistor Rg (2.2 to 22kΩ) between
the OSC pin and the external clock output pin (external oscillator) when selecting the external clock operating
mode (see the note on the OSC pin peripheral circuits).
(P1)
Sample Application Circuit 6
(P2)
(P3)
(P4)
(P5)
1/4 Duty, 1/2 Bias (for use with large panels)
+3.3V
VDD
OSC
*2
General-purpose
output ports
Used for functions
such as backlight
control
(P8)
COM1
VSS
VLCD
+5.8V
VLCD0
R
10kΩ≥R≥2.2kΩ
C≥0.047µF
C
R
VLCD1
VLCD2
COM3
S129/COM4
P1/S1
P2/S2
P3/S3
P4/S4
P5/S5
P8/S8
S9
From the controller
INH
CE
CL
S127
DI
S128
LCD panel (up to 512 segments)
COM2
VSS
Note: *2 Connect an external resistor Rosc and an external capacitor Cosc between the OSC pin and GND when
selecting the RC oscillator operating mode and connect a current protection resistor Rg (2.2 to 22kΩ) between
the OSC pin and the external clock output pin (external oscillator) when selecting the external clock operating
mode (see the note on the OSC pin peripheral circuits).
No.A0549-32/34
LC75897PW
Sample Application Circuit 7
(P1)
1/4 Duty, 1/3 Bias (for use with normal panels)
+3.3V
(P2)
(P3)
(P4)
(P5)
VDD
OSC
*2
General-purpose
output ports
Used for functions
such as backlight
control
(P8)
COM1
COM2
VSS
P1/S1
P2/S2
P3/S3
VLCD
+5.8V
OPEN
VLCD0
P4/S4
VLCD1
P5/S5
VLCD2
C≥0.047µF
C
LCD panel (up to 512 segments)
COM3
S129/COM4
VSS
P8/S8
C
S9
INH
CE
From the controller
CL
S127
DI
S128
Note: *2 Connect an external resistor Rosc and an external capacitor Cosc between the OSC pin and GND when
selecting the RC oscillator operating mode and connect a current protection resistor Rg (2.2 to 22kΩ) between
the OSC pin and the external clock output pin (external oscillator) when selecting the external clock operating
mode (see the note on the OSC pin peripheral circuits).
Sample Application Circuit 8
(P1)
1/4 Duty, 1/3 Bias (for use with large panels)
(P2)
(P3)
(P4)
(P5)
+3.3V
VDD
OSC
*2
General-purpose
output ports
Used for functions
such as backlight
control
(P8)
COM1
VSS
VLCD
+5.8V
VLCD0
R
VLCD1
R
10kΩ≥R≥2.2kΩ
C≥0.047µF
From the controller
VLCD2
C
C
R
COM3
S129/COM4
P1/S1
P2/S2
P3/S3
P4/S4
P5/S5
P8/S8
S9
INH
CE
CL
S127
DI
S128
LCD panel (up to 512 segments)
COM2
VSS
Note: *2 Connect an external resistor Rosc and an external capacitor Cosc between the OSC pin and GND when
selecting the RC oscillator operating mode and connect a current protection resistor Rg (2.2 to 22kΩ) between
the OSC pin and the external clock output pin (external oscillator) when selecting the external clock operating
mode (see the note on the OSC pin peripheral circuits).
No.A0549-33/34
LC75897PW
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products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
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export license from the authorities concerned in accordance with the above law.
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Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
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above.
This catalog provides information as of April, 2007. Specifications and information herein are subject
to change without notice.
PS No.A0549-34/34