MM58174A Microprocessor-Compatible Real-Time Clock Y General Description Y The MM58174A is a low-threshold metal-gate CMOS circuit that functions as a real-time clock and calendar in bus-oriented microprocessor systems. The device includes an interrupt timer which may be programmed to one of three times. Timekeeping is maintained down to 2.2V to allow low power standby battery operation. The timebase is generated from a 32768 Hz crystal-controlled oscillator. Y Y Y Applications Y Features Y Y Y Y Y Y Y Microprocessor compatible Tenths of seconds, seconds, tens of seconds, minutes, tens of minutes, day of week, days, tens of days, months, tens of months, independent registers Automatic leap year calculation Internal pull-ups to safeguard data Protection for read during data changing Independent interrupt system with open drain output TTL compatible Low power standby operation (2.2V, 10 mA) Low cost internally biased oscillator Low cost 16-pin dual-in-line package Available for commercial and military temperature ranges Y Y Y Y Y Y Point-of-sale terminals Word processors Teller terminals Event recorders Microprocessor-controlled instrumentation Microprocessor time clock TV/VCR reprogramming Intelligent telephone Block Diagram TL/F/6681 – 1 FIGURE 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/6681 RRD-B30M105/Printed in U. S. A. MM58174A Microprocessor-Compatible Real-Time Clock May 1991 Absolute Maximum Ratings Storage Temperature If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage at All Inputs and Outputs 6.5V Lead Temperature (Soldering, 10 seconds) VDD a 0.3 to VSS b 0.3 Operating Temperature MM58174AN b 65§ C to a 150§ C VDD –VSS 300§ C b 40§ C to a 85§ C Electrical Characteristics TA e b40§ C to a 85§ C, VSS e 0V Symbol VDD IDD Parameter Supply Voltage Conditions Standby Mode (no READ or WRITE Instructions) Operational Mode Supply Current VDD e 2.2V (Standby) VDD e 5V (Operating) Input Logic Levels for Signals: AD0–AD3, DB0–DB3, WR, RD, CS Logic ‘‘1’’ Logic ‘‘0’’ VDD e 5V Min Typ Max Units 2.2 5.5 V 4.5 5.5 V 10 1 mA mA 0.8 V V 10 pF 30 mA 2 Input Capacitance Input Current Levels VDD e 5V Current to VSS for Signals: AD0–AD3, DB0–DB3, RD VIN e VDD Internal Resistor to VDD for Signals: WR CS Output Logic Levels for Signals: DB0–DB3 Logic ‘‘1’’ Logic ‘‘0’’ INTERRUPT (Open Drain) Logic ‘‘0’’ Off Leakage 30 30 100 100 kX kX VDD e 5V IOH e b0.1 mA IOL e 1.6 mA For IDS e 1.6 mA VOUT e 5V 2 2.4 0.4 V V 0.4 5 V mA Functional Description Connection Diagram The MM58174 is a microprocessor bus-oriented real-time clock. The circuit includes addressable real-time counters for tenths of seconds through months and a write only register for leap year calculation. The counters are arranged as bytes of four bits each. When addressed a byte will appear on the data I/O bus so that each word can be accessed independently. If any byte does not contain four bits (e.g., days of the week uses only 3 bits), the unused bits will be unrecognized during a write operation and tied to VSS during a read operation. The addressable reset latch causes the pre-scaler, tenths of seconds, seconds, and tens of seconds to be held in a reset condition. If a register is updated during a read operation the I/O data is prevented from updating and a subsequent read will return the illegal b.c.d. code ’1111’. The interrupt timer may be programmed for intervals of 0.5 second, 5 seconds, or 60 seconds and may be coded as a single or repeated operation. The open drain interrupt output is pulled to VSS when the timer times out and reading the interrupt register provides the internal selected information. Dual-In-Line Package TL/F/6681 – 2 Top View Order Number MM58174AN See NS Package Number N16A The possibility may be overcome by implementing a further read of the tenths of seconds register at the end of every series of reads (starting with a read at the tenths of seconds register) and checking for unchanged data. Circuit Description The block diagram shown in Figure 1 shows the structure of the CMOS clock chip. A 16-pin DIL package is used. SECONDS COUNTERS There are three counters for Seconds: a) tenths of seconds b) units of seconds c) tens of seconds The outputs of all three counters can be separately multiplexed on to the command 4-bit output bus. Table I shows the address decoding for each counter. All three counters are reset to zero by the start/stop F/F. CRYSTAL OSCILLATOR This consists of a CMOS inverter/amplifier with on-chip bias resistor and capacitors. A single 6 pF–36 pF trimmer is all that is required to fine tune the crystal (see Figure 2 ). However, for improved stability, some crystals may require a capacitor of typical value 20 pF to be added between pin 14 and ground. The output of the oscillator is blocked by the start/stop F/F. NON-INTEGER DIVIDER This counter divides the incoming 32,768 Hz frequency by 15/16 down to 30,720 Hz. MINUTES COUNTERS There are two Minutes counters: a) units of minutes b) tens of minutes Both counters are parallel loaded with data from the 4-bit input bus when addressed by the microprocessor and a Write Data Strobe pulse given. Similarly, the output of both counters can be read separately onto the common 4-bit output bus (Table I). FIXED DIVIDER (512) This is a standard 9-stage binary ripple counter. Output frequency is 60 Hz. This counter is reset to zero by start/stop F/F. FIXED DIVIDER (6) This is a 3-stage Johnson counter with a 10 Hz output signal. This counter is reset to zero state by the start/stop F/F. HOURS COUNTERS There are two Hours counters which will count in a 24-hour mode: a) units of hours SYNCHRONIZATION STAGE Both 10 Hz and 32,768 Hz clocks are fed into this section. It is used to generate a pulse of 15.25 ms width on the rising edge of each 10 Hz pulse. This pulse is used to increment all the seconds, minutes, hours, days, months, and year counter and also to set the data changed F/F. b) tens of hours Both counters have identical parallel load and read multiplex features to the Minutes counters. SEVEN DAY COUNTER There is a 7-state counter which increments every 24 hours. It will have identical parallel load and read multiplex capabilities to the Minutes and Hours counters. The counter counts cyclically from 1 – 7. DATA CHANGED F/F This is set by the rising edge of each 10 Hz pulse to indicate that the clock value has changed since the last read operation. It is reset by any clock read command. The flip flop sets all data bus bits to a ‘‘1’’ during RD time indicating that a register has been updated. This transient condition may occur at the end of the Read Data strobe. Hence, invalid data may still be read from the clock, if the strobe width was less than 3 ms. 3 Circuit Description (Continued) TL/F/6681–3 FIGURE 2. Crystal Oscillator DAYS COUNTER There are two Days counters: a) units of days b) tens of days The Days counters will count up to 28, 29, 30, or 31 days depending on the state of the Months counters and the Years Status Register. Days counters have parallel load and read multiplex capabilities. TL/F/6681 – 4 FIGURE 3. Test Mode Organization MONTHS COUNTERS There are two Months counters: a) units of months b) tens of months The Months counters have parallel load and read multiplex capabilities. START/STOP (RESET) LATCH A logic ‘‘1’’ on DB0 at chip address 14 (E) will start the clock running, a logic ‘‘0’’ will stop the clock. This function allows the loading of time data into the clock and its precise starting. The clock starts at 0.1 seconds. YEARS STATUS REGISTER The Years Status register is a shift register of 4 bits. It will be shifted every year on December 31st. The status register must be set in accordance with Table III. No readout capability is provided. TEST MODE This mode is incorporated to facilitate production testing of the circuit. In this mode, the 32,768 Hz clock is fed forward as shown in Figure 3. For normal operation, the circuit must be set to the non-test mode as part of the system initialization. This is accomplished by writing a logic ‘‘0’’ to DB3 at AD0. CHIP SELECT (CS) An external chip select is provided. The chip enable is active low. TABLE I. Address Decoding for Internal Registers Selected Counter COUNTER AND REGISTER SELECTION Table I shows the coding on the address lines AD0–AD3 which select the registers in the circuit to be either parallel loaded or read on to the output bus. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 4 Test Only Tenths of Secs. Units of Secs. Tens of Secs. Units of Mins. Tens of Mins. Units of Hours Tens of Hours Units of Days Tens of Days Day of Week Units of Months Tens of Months Years Stop/Start Interrupt Address Bits Mode AD3 AD2 AD1 AD0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Write Only Read Only Read Only Read Only Read or Write Read or Write Read or Write Read or Write Read or Write Read or Write Read or Write Read or Write Read or Write Write Only Write Only Read or Write Circuit Description (Continued) TABLE IIa. Interrupt Selection Data Mode: Address 15, Write Mode Function DB3 DB2 DB1 DB0 No Interrupt Int. at 60 Sec. Intervals* Int. at 5.0 Sec. Intervals* Int. at 0.5 Sec. Intervals* X 0/1 0/1 0/1 0 1 0 0 0 0 1 0 0 0 0 1 TL/F/6681 – 5 C1 & 0.003 pF C0 & 3.0 pF FIGURE 4. Typical Crystal Parameters * a 16.6 ms DEVICE INITIALIZATION AND OSCILLATOR SETTING When first installed or if the battery back-up has failed, the MM58174A will require to be properly initialized. The following sequence is a suggested flow of operations to achieve this. Action Result 1) Apply power. Clears interrupt timer chain. 2) Write ‘‘0’’ to address 15. 3) Read 3 times from Clears interrupt output address 15. logic. 4) Write ‘‘0’’ on DB3 to Clears test mode. address 0. 5) Write ‘‘0’’ on DB0 to Stops clock running. address 14. 6) Set up timekeeping Load real-time into device registers. time registers, minutes to leap years. 7) Write ‘‘1’’ on DB0 to Starts timekeeping address 14. synchronized to an external time source. 8) Program and start Commence interrupt interrupts. timing, if so required. DB3 e 0, single interrupt DB3 e 1, repeated interrupt TABLE IIb. Interrupt Read Back (Status) Mode: Address 15, Read Mode Interrupt Status DB3 DB2 DB1 DB0 X X X X 0 1 0 0 0 0 1 0 0 0 0 1 Reset 60 Sec. Signal 5.0 Sec. Signal 0.5 Sec. Signal X e don’t care state TABLE III. Years Status Register Mode: Address 13, Write Mode Leap Year Leap Year-1 Leap Year-2 Leap Year-3 DB3 DB2 DB1 DB0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 Note: Leap year counter rolls over on December 31 @ RS & 35 kX 23:59:59. OSCILLATOR SETTING Directly connecting a frequency meter to the Crystal Out pin (14) will not allow correct frequency setting because of the extra capacitive loading of the meter. One possibility for setting is to use a high impedance probe or a CMOS buffer to keep the loading as low as possible (e.g., 100 x 2 pF probe). Alternatively, a buffered output of 16.384 kHz OSC/2 can be produced on DB0 by applying the following procedure: Action Result 1) Write a ‘‘1’’ on DB3 to Selects test mode. address 0. 2) Write a ‘‘1’’ on DB0 to Starts clock timing. address 14. 3) Read at address 1 (tenths ‘‘Data Changed’’ signal is of secs). read. 4) Read at address 1 and 16.384 kHz appears on HOLD the strobe LOW. DB0. 5) Adjust trimmer capacitor. There must be no extra activity on the RD line between steps 3 and 4 or only the normal ‘‘Data Changed’’ signal will be observed on the data bus. Thus if the normal host processor system is being used to generate the chip waveforms, proper care must be taken. INTERRUPT SYSTEM The interrupt output and its frequency of operation is enabled by writing to address 15 (see Table IIa). To ensure correct operation, the interrupt should be serviced within 16.6 ms. The interrupt is initialized by writing ‘‘0’’ to address 15 and reading the interrupt, i.e., reading at address 15 three times. Initialization must be performed at power on and also if the interrupt is not serviced correctly within 16.6 ms. SERVICING THE INTERRUPT In a typical system the open drain interrupt output is wired to the processor interrupt system. Hence, when the interrupt timer times out, the interrupt output is pulled low and the processor is interrupted. The processor may then reset the interrupt by utilizing the following procedure: Read Address 15 three times. This resets the interrupt output and restarts the interrupt timer when in the repeat mode. It is recommended that the interrupt output is connected to a unique processor port. CRYSTAL PARAMETERS Figure 4 is an electrical representation of the crystal along with some typical values. The 32.768 kHz crystal is an NT CUT (tuning fork type) or XY BAR for use in a parallel resonant Pierce oscillator. 5 Timing Waveforms WRITE MODE Figure 7 gives detailed timing for the transfer of data from microprocessor to peripheral. See Table V. READ MODE Figure 6 gives detailed timing for the transfer of data from peripheral to microprocessor. See Table IV. All times are measured from (or to) valid logic ‘‘0’’ level e 0.8V or valid logic ‘‘1’’ level e 2.0V. TL/F/6681 – 6 FIGURE 5. Typical Microprocessor Interface TL/F/6681 – 8 FIGURE 7. Write Cycle Waveforms TL/F/6681–7 FIGURE 6. Read Cycle Waveforms TL/F/6681 – 9 FIGURE 8. Typical Supply Current vs Supply Voltage during Power Down 6 Operating Conditions MM58174AN TA e b40§ C to 85§ C, VDD e 5V TABLE IV. Read Timing: Data from Peripheral to Microprocessor Symbol MM58174AN Parameter Min Typ Units tACS0 Address Bus Valid to Chip Select ON (CS e 0) 0 ns tCSR Chip Select ON to Read Strobe 0 ns tRD Read Cycle Access Time from Read Strobe to Data Bus Valid tRH Data Hold Time from Trailing Edge of Read Strobe 0 tRA Address Bus Hold Time from Trailing Edge of Read Strobe 70 tACS1 Address Change to Chip Select OFF 0 tAD Address Bus Valid to Data Valid tHZ Time from Trailing Edge of Read Strobe until Interface Device Bus Drivers are in TRI-STATEÉ Mode tRW Read Strobe Width tAR Address Bus Valid to Read Strobe 900 450 330 ns CL e 100 pF ns 500 1850 0 Comments Max ns 40 ns 850 ns 330 ns 14 ms 500 CL e 100 pF ns Note 1: In order not to degrade timekeeping accuracy, the number of Read strobes in any one second should be less than 10,000. Note 2: If address and read occur simultaneously then they must exist for tAR a tAD. TABLE V. Write Timing: Data from Microprocessor to Peripheral Symbol MM58174AN Parameter Min Typ Units Max tACS0 Address Bus Valid to Chip Select ON (CS e 0) 0 tCSW Chip Select ON to Write Strobe 0 tAW Address Bus Valid to Write Strobe 725 ns tWW Write Strobe Width 670 ns tDW Data Bus Valid before Write Strobe 70 ns tWA Address Bus Hold Time following Write Strobe 165 ns tWD Data Bus Hold Time following Write Strobe 185 ns tACS1 Address Change to Chip Select OFF (CS e 1) 0 ns Note 3: If address and write occur simultaneously, then they must exist for tAW and tWW. 7 ns 450 ns Comments MM58174A Microprocessor-Compatible Real-Time Clock Physical Dimensions inches (millimeters) Molded Dual-In-Line Package (N) Order Number MM58174AN NS Package Number N16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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