DS92LV1260 Six Channel 10 Bit BLVDS Deserializer General Description Features The DS92LV1260 integrates six deserializer devices into a single chip. The chip uses a 0.25u CMOS process technology. The DS92LV1260 can simultaneously deserialize up to six data streams that have been serialized by the National Semiconductor DS92LV1021 or DS92LV1023 Bus LVDS serializers. The device also includes a seventh serial input channel that serves as a redundant input. n Deserializes one to six BusLVDS input serial data streams with embedded clocks n Seven selectable serial inputs to support n+1 redundancy of deserialized streams n Seventh channel has single pin monitor output that reflects input from seventh channel input n Parallel clock rate up to 40MHz n On chip filtering for PLL n Absolute maximum worst case power dissipation = 1.9W at 3.6V n High impedance inputs upon power off (Vcc = 0V) n Single power supply at +3.3V n 196-pin LBGA package (Low-profile Ball Grid Array) package n Industrial temperature range operation: −40˚C to +85˚C Each deserializer block in the DS92LV1260 operates independently with its own clock recovery circuitry and lockdetect signaling. The DS92LV1260 uses a single +3.3V power supply with a typical power dissipation of 1.2W at 3.3V with a PRBS-15 pattern. Refer to the Connection Diagrams for packaging information. Block Diagram Application 20000202 © 2003 National Semiconductor Corporation DS200002 www.national.com DS92LV1260 Six Channel 10 Bit BLVDS Deserializer August 2003 DS92LV1260 Absolute Maximum Ratings Lead Temperature (Soldering 10 Sec) (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (Vcc) ESD Rating: > 3KV > 750V Human Body Model -0.3 to 4V Bus LVDS Input Voltage (Rin +/-) +225˚C Machine Model -0.3V to 3.9V Reliability Information Transistor Count Maximum Package Power Dissipation @ 25˚C 35,682 3.7W Recommended Operating Conditions Package Thermal Resistance θJA 196 LBGA: 34˚C/W θJC 196 LBGA: 8˚C/W Storage Temp. Range -65˚C to +150˚C Junction Termperature +150˚C Supply Voltage (VCC) 3.0V to 3.6V -40˚C to +85˚C Operating Free Air Temperature (TA) Operating Frequency 16-40 MHz Electrical Characteristics Basic functionality and specifications per deserializer channel will be similar to National Semiconductor’s DS92LV1212A. Over recommended operating supply and termperature ranges unless otherwise specified.(Note 2) Symbol Parameter Conditions Pin/Freq. Min Vin = 0 or 3.6V REN, REFCLK, PWRDWN, SEL (0:2), ROUT Typ Max Units 2.0 VCC V GND 0.8 V -0.87 -1.5 V LVCMOS/LVTTL DC Specifications: VIH High Level Input Voltage VIL Low Level Input Voltage VCL Input Clamp Voltage IIN Input Current VOH High Level Output Voltage VOL Low Level Output Voltage IOS IOZ +10 uA IOH = -6mA 2 3 VCC V IOL = 6mA GND 0.18 0.4 V -15 -46 -85 mA -10 +/-0.2 +10 uA +3 +50 mV Output short Circuit Current Vout = 0V,(Note 4) TRI-STATE Output Current PWRDWN or REN = 0.8V, Vout = 0V or VCC Rout, RCLK, LOCK -10 Bus LVDS DC specifications VTH Differential Threshold High Voltage VTL Differential Threshold Low Voltage IIN Input Current VCM = 1.1V (VRI+-VRI-) RI+, RI- -50 -2 mV Vin = +2.4V, Vcc = 3.6 or 0V -10 +/- 1 +10 uA Vin =0V, Vcc = 3.6 or 0V -10 +/- 1 +10 uA 460 530 mA 0.36 1 mA 62.5 ns 60 % Supply Current ICCR Worst Case Supply Current 3.6V, 40 MHz, Checker Board Pattern, CL=15pF ICCXR Supply Current when Powered Down PWRDN= 0.8V REN = 0.8V Timing Requirements for REFCLK tRFCP REFCLK Period 25 tRFDC REFCLK Duty Cycle 40 tRFCP/tTCP Ratio of REFCLK to TCLK www.national.com 0.95 2 50 1.05 (Continued) Basic functionality and specifications per deserializer channel will be similar to National Semiconductor’s DS92LV1212A. Over recommended operating supply and termperature ranges unless otherwise specified.(Note 2) Symbol tRFTT Parameter Conditions Pin/Freq. Min Typ REFCLK Transition Time Max Units 8 ns 62.5 ns 55 % Deserializer Switching Characteristics tRCP RCLK Period tRDC RCLK Duty Cycle tCHTST Period of Bus LVDS signal when CHTST is selected by MUX tCLH CMOS/TTL Low-to-High Transition Time 1.7 6 ns tCHL CMOS/TTL High-to-Low Transition Time 1.6 6 ns tROS Rout Data Valid before RCLK Figure 2 tROH Rout Data Valid after RCLK Figure 2 tHZR High to TRI-STATE Delay 10 ns tLZR Low to TRI-STATE Delay 10 ns tZHR TRI-STATE to High Delay 12 ns tZLR TRI-STATE to Low Delay RCLK (Note 7) Figure 1 CHTST Rout, LOCK, RCLK RCLK Room Temp 3.3V 40MHz 25 43 50 25 ns 0.4*tRCP ns -0.4*tRCP ns 12 ns 1.75*tRCP+5 1.75*tRCP+7 1.75*tRCP+10 ns 1.75*tRCP+6 1.75*tRCP+7 1.75*tRCP+9 ns tDD Deserializer Delay Deserializer PLL LOCK Time from PWRDN (with SYNCPAT) Figure 3 (Note 5) 40MHz 3 us tDSR1 20MHz 10 us Deserializer PLL Lock Time from SYNCPAT Figure 4 (Note 5) 40MHz 2 us 20MHz 5 us tDSR2 tRNM Deserializer Noise Margin (Note 6) 40MHz 450 920 ps 20MHz 1200 1960 ps Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Typical values are given for Vcc = 3.3V and TA =25˚C Note 3: Current into the device pins is defined as positive. Current out of device pins is defined as negative. Voltage are referenced to ground except VTH and VTL which are differential voltages. Note 4: Only one output should be shorted at a time. Do not exceed maximum package power dissipation capacity. Note 5: For the purpose of specifying deserializer PLL performance tDSR1 and tDSR2 are specified with the REFCLK running and stable, and specific conditions of the incoming data stream (SYNCPATs). tDSR1 is the time required for the deserializer to indicate lock upon power-up or when leaving the power-down mode. tDSR2 is the time required to indicate lock for the powered-up and enabled deserializer when the input (RI+ and RI−) conditions change from not receiving data to receiving synchronization patterns (SYNCPATs). The time to lock to random data is dependent upon the incoming data. Note 6: tRNM is a measure of how much phase noise (jitter)the deserializer can tolerate in the incoming data stream before bit errors occur. The Deserializer Noise Margin is Guaranteed By Design (GBD) using statistical analysis. Note 7: Because the Bus LVDS serial data stream is not decoded, the maximum frequency of the CHTST output driver could be exceeded if the data stream were switched to CHTST. The maximum frequency of the BUS LVDS input should not exceed the parallel clock rate. 3 www.national.com DS92LV1260 Electrical Characteristics DS92LV1260 AC Timing Diagrams and Test Circuits 20000204 FIGURE 1. Deserializer Delay tDD 20000207 FIGURE 2. Output Timing tROS and tROH 20000209 FIGURE 3. Locktime from PWRDN* tDSR1 www.national.com 4 DS92LV1260 AC Timing Diagrams and Test Circuits (Continued) 20000211 FIGURE 4. Locktime to SYNCPAT tDSR2 20000213 FIGURE 5. Unlock 20000231 FIGURE 6. Deserializer Data Valid Out Times 5 www.national.com DS92LV1260 AC Timing Diagrams and Test Circuits (Continued) 20000218 FIGURE 7. Deserializer TRI-STATE Test Circuit and Timing www.national.com 6 DS92LV1260 Block Diagram 20000201 Control Pins Truth Table PWRDN REN SEL2 SEL1 SEL0 Rout CHTST LOCK[0:5] RCLK[0:5] H H L L L Din6 Decoded to Rout 0 (0:9)(Note 11) Din0 (not decoded) Active(Note 9) Active(Notes 10, 11) H H L L H Din6 Decoded to Rout 1 (0:9)(Note 11) Din1 (not decoded) Active(Note 9) Active(Notes 10, 11) H H L H L Din6 Decoded to Rout 2 (0:9)(Note 11) Din2 (not decoded) Active(Note 9) Active(Notes 10, 11) 7 www.national.com DS92LV1260 Control Pins Truth Table (Continued) H H L H H Din6 Decoded to Rout 3 (0:9)(Note 11) Din3 (not decoded) Active(Note 9) Active(Notes 10, 11) H H H L L Din6 Decoded to Rout 4 (0:9)(Note 11) Din4 (not decoded) Active(Note 9) Active(Notes 10, 11) H H H L H Din6 Decoded to Rout 5 (0:9)(Note 11) Din5 (not decoded) Active(Note 9) Active(Notes 10, 11) H H H H L Din6 is not Decoded Z Active(Note 9) Active(Notes 10, 11) H H H H H Din6 is not Decoded Din6 (not decoded) Active(Note 9) Active(Notes 10, 11) L X X X X Z Z Z Z H L X X X Z Z Active(Note 9) Z Note 8: The routing of the Din inputs to the Deserializers and to the CHTST outputs are dependent on the states of SEL [0:2]. Note 9: LOCK Active indicates that the LOCK output will reflect the state of it’s respective Deserializer with regard to the selected data stream. Note 10: RCLK Active indicates that the RCLK will be running if the Deserializer is locked. The timing of RCLK [0:5] with respect to Rout [0:5][0:9] is determined by RCLK_R/FFigure 5 Note 11: Rout n[0:9] and RCLK [0:5] are Tri-Stated when LOCKn[0:5] is High. data sheet for the proper operation during this step of the Initialization State. The Deserializer identifies the rising clock edge in a synchronization pattern or random data and after 80 clock cycles will synchronize to the data stream from the serializer. At the point where the Deserializer’s PLL locks to the embedded clock, the LOCKn pin goes low and valid data appears on the output. Note that this differs from pervious deserializers where the LOCKn signal was not synchronous to valid data appearing on the outputs. Functional Description The DS92LV1260 combines six 1:10 deserializers into a single chip. Each of the six deserializers accepts a BusLVDS data stream from National Semiconductor’s DS92LV1021 or DS92LV1023 Serializer. The deserializers then recover the clock and data to deliver the resulting 10-bit wide words to the outputs. A seventh serial data input provides n+1 redundancy capability. The user can program the seventh input to be an alternative input to any of the six deserializers. Whichever input is replaced by the seventh input is then routed to the CHANNEL TEST (CHTST) pin on receiver output port. Each of the 6 channels acts completely independent of each other. Each independent channel has outputs for a 10-bit wide data word, the recovered clock out, and the lock-detect output. Data Transfer After initialization, the serializer transfers data to the deserializers. The serial data stream includes a start and stop bit appended by the serializer, which frame the ten data bits. The start bit is always high and the stop bit is always low. The start and stop bits also function as clock bits embedded in the serial stream. The Serializer transmits the data and clock bits (10+2 bits) at 12 times the TCLK frequency. For example, if TCLK is 40 MHz, the serial rate is 40 X 12 = 480 Mbps. Since only 10 bits are from input data, the serial ’payload’ rate is 10 times the TCLK frequency. For instance, if TCLK = 40 MHz, the payload data is 40 X 10 = 400 Mbps. TCLK is provided by the data source and must be in the range 20 MHz to 40 MHz nominal. When one of six Deserializer channels synchronizes to the input from a Serializer, it drives its LOCKn pin low and synchronously delivers valid data on the output. The Deserializer locks to the embedded clock, uses it to generate multiple internal data strobes, and drives the embedded clock to the RCLKn pin. The RCLKn is synchronous to the data on the ROUT[n0:n9] pins. While LOCKn is low, data on ROUT [n0:n9] is valid. Otherwise, ROUT[n0:n9] is invalid. All ROUT, LOCK, and RCLK signals will drive a minimum of three CMOS input gates (15pF load) with a 40 MHz clock. This amount of drive allows bussing outputs of two Deserializers and a destination ASIC. REN controls TRI-STATE™ of all the outputs. The DS92LV1260 has three operating states: Initialization, Data Transfer, and Resynchronization. In addition, there are two passive states: Powerdown and TRI-STATE. The following sections describe each operating mode and passive state. Initialization Before the DS92LV1260 receives and deserializes data, it and the transmitting serializer devices must initialize the link. Initialization refers to synchronizing the Serializer’s and the Deserializer’s PLL’s to local clocks. The local clocks must be the same frequency or within a specified range if from different sources. After all devices synchronize to local clocks, the Deserializers synchronize to the Serializers as the second and final initialization step. Step 1: After applying power to the Deserializer, the outputs are held in TRI-STATE and the on-chip power-sequencing circuitry disables the internal circuits. When Vcc reaches VccOK (2.1V), the PLL in each deserializer begins locking to the local clock (REFCLK). A local on-board oscillator or other source provides the specified clock input to the REFCLK pin. Step 2: The Deserializer PLL must synchronize to the Serializer to complete the initialization. Refer to the Serializer www.national.com 8 is transfers. The Deserializer enters Powerdown when PWRDN is driven low. In Powerdown, the PLL stops and the outputs go into TRI-STATE, which reduces supply current to the microamp range. To exit Powerdown, the system drives PWRDN high. Upon exiting Powerdown, the Deserializer enters the Initialization state. The system must then allow time to Initialize before data transfer can begin. (Continued) The Deserializer input pins are high impedance during Powerdown (PWRDN low) and power-off (Vcc = 0V). Resynchronization Whenever one of the six Deserializers loses lock, it will automatically try to resynchronize. For example, if the embedded clock edge is not detected two times in succession, the PLL loses lock and the LOCKn pin is driven high. The system must monitor the LOCKn pin to determine when data is valid. TRI-STATE When the system drives REN pin low, the Deserializer enters TRI-STATE. This will TRI-STATE the receiver output pins (ROUT[00:59]) and RCLK[0:5]. When the system drives REN high, the Deserializer will return to the previous state as long as all other control pins remain static (PWRDN, RCLK_R/F). The user has the choice of allowing the deserializer to resynch to the data stream or to force synchronization by pulsing the Serializer SYNC1 or SYNC2 pin. This scheme is left up to the user discretion. One recommendation is to provide a feedback loop using the LOCKn pin itself to control the sync request of the Serializer (SYNC1 or SYNC2). Dual SYNC pins are given for multiple control in a multi-drop application. Powerdown The Powerdown state is a low power sleep mode that the Serializer and Deserializer typically occupy while waiting for initialization, or to reduce power consumption when no data 9 www.national.com DS92LV1260 Data Transfer DS92LV1260 RECOVERING FROM LOCK LOSS In the case where the Deserializer loses lock during data transmission, up to 1 cycle of data that was previously received can be invalid. This is due to the delay in the lock detection circuit. The lock detect circuit requires that invalid clock information be received 2 times in a row to indicate loss of lock. Since clock information has been lost, it is possible that data was also lost during these cycles. Therefore, after the Deserializer relocks to the incoming data stream and the Deserializer LOCKn pin goes low, at least one previous data cycle should be suspect for bit errors. Application Information USING THE DS92LV1021 AND DS92LV1260 The DS92LV1260 combines six 1:10 deserializers into a single chip. Each of the six deserializers accepts a BusLVDS data stream up to 480 Mbps from National Semiconductor’s DS92LV1021 or DS92LV1023 Serializer. The deserializers then recover the embedded two clock bits and data to deliver the resulting 10-bit wide words to the output. A seventh serial data input provides n+1 redundancy capability. The user can program the seventh input to be an alternative input to any of the six deserializers. Whichever input is replaced by the seventh input is then routed to the CHANNEL TEST (CHTST) pin on receiver output port. The Deserializer uses a separate reference clock (REFCLK) and an onboard PLL to extract the clock information from the incoming data stream and then deserialize the data. The Deserializer monitors the incoming clock information, determines lock status, and asserts the LOCKn output high when loss of lock occurs. The Deserializer can relock to the incoming data stream by making the Serializer resend SYNC patterns, as described above, or by random locking, which can take more time, depending on the data patterns being received. HOT INSERTION All the BusLVDS devices are hot pluggable if you follow a few rules. When inserting, ensure the Ground pin(s) makes contact first, then the VCC pin(s), and then the I/O pins. When removing, the I/O pins should be unplugged first, then the VCC, then the Ground. Random lock hot insertion is illustrated in Figure 11. POWER CONSIDERATIONS An all CMOS design of the Deserializer makes it an inherently low power device. TRANSMISSION MEDIA The Serializer and Deserializer can also be used in point-topoint configurations, through PCB trace, or through twisted pair cable. In point-to-point configurations, the transmission media need only be terminated at the receiver end. Please note that in point-to-point configurations, the potential of offsetting the ground levels of the Serializer vs. the Deserializer must be considered. Also, Bus LVDS provides a +/− 1V common mode range at the receiver inputs. POWERING UP THE DESERIALIZER The DS92LV1260 can be powered up at any time by following the proper sequence. The REFCLK input can be running before the Deserializer powers up, and it must be running in order for the Deserializer to lock to incoming data. The Deserializer outputs will remain in TRI-STATE until the Deserializer detects data transmission at its inputs and locks to the incoming data stream. TRANSMITTING DATA Once you power up the Deserializer, it must be phase locked to the transmitter to transmit data. Phase locking occurs when the Deserializer locks to incoming data or when the Serializer sends sync patterns. The Serializer sends SYNC patterns whenever the SYNC1 or SYNC2 inputs are high. The LOCKn output of the Deserializer remains high until it has locked to the incoming data stream. Connecting the LOCKn output of the Deserializer to one of the SYNC inputs of the Serializer will guarantee that enough SYNC patterns are sent to achieve Deserializer lock. The Deserializer can also lock to incoming data by simply powering up the device and allowing the “random lock” circuitry to find and lock to the data stream. FAILSAFE BIASING FOR THE DS92LV1260 The DS92LV1260 has internal failsafe biasing and an improved input threshold sensitivity of +/− 50mV versus +/− 100mV for the DS92LV1210 or DS92LV1212. This allows for greater differential noise margin in the DS92LV1260. However, in cases where the receiver input is not being actively driven, the increased sensitivity of the DS92LV1260 can pickup noise as a signal and cause unintentional locking . For example, this can occur when the input cable is disconnected. External resistors can be added to the receiver circuit board to prevent noise pick-up. Typically, the non-inverting receiver input is pulled up and the inverting receiver input is pulled down by high value resistors. The pull-up and pull-down resistors (R1 and R2) provide a current path through the termination resistor (RL) which biases the receiver inputs when they are not connected to an active driver. The value of the pull-up and pull-down resistors should be chosen so that enough current is drawn to provide a +15mV drop across the termination resistor. Please see Figure 9 for the Failsafe Biasing Setup. NOISE MARGIN While the Deserializer LOCKn output is low, data at the Deserializer outputs (ROUT0-9) are valid, except for the specific case of loss of lock during transmission which is further discussed in the "Recovering from LOCK Loss" section below. The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still reliably receive data. Various environmental and systematic factors include: Serializer: TCLK jitter, VCC noise (noise bandwidth and out-of-band noise) Media: ISI, Large VCM shifts Deserializer: VCC noise www.national.com PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS Circuit board layout and stack-up for the DS92LV1260 should be designed to provide noise-free power to the device. Good layout practice will separate high frequency or high level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. There are a few common practices which should be followed when designing PCB’s for Bus LVDS Signaling. Recommended layout practices are: 10 tive, these planes must be tied to the ground supply plane at frequent intervals with vias. Frequent via placement improves signal integrity on signal transmission lines by providing short paths for image currents, which reduces signal distortion. Depending on which is greater, the planes should be pulled back from all transmission lines and component mounting pads a distance equal to the width of the widest transmission line or the thickness of the dielectric separating the transmission line from the internal power or ground plane(s). Doing so minimizes effects on transmission line impedances and reduces unwanted parasitic capacitances at component mounting pads. (Continued) • Use at least 4 PCB board layers (Bus LVDS signals, ground, power, and TTL signals). Power system performance may be greatly improved by using thin dielectrics (4 to 10 mils) for power/ground sandwiches. This increases the intrinsic capacitance of the PCB power system which improves power supply filtering, especially at high frequencies, and makes the value and placement of external bypass capacitors less critical. • Keep Serializers and Deserializers as close to the (Bus LVDS port side) connector as possible. Longer stubs lower the impedance of the bus, increase the load on the Serializer, and lower the threshold margin at the Deserializers. Deserializer devices should be placed much less than one inch from slot connectors. Because transition times are very fast on the Serializer Bus LVDS outputs, reducing stub lengths as much as possible is the best method to ensure signal integrity. • Bypass each Bus LVDS device and also use distributed bulk capacitance between power planes. Surface mount capacitors placed close to power and ground pins work best. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range 0.001 µF to 0.1 µF. Tantalum capacitors may be in the range 2.2 µF to 10 µF. Voltage rating for tantalum capacitors should be at least 5X the power supply voltage being used. Randomly distributed by-pass capacitors should also be used. Package and pin layout permitting, it is also recommended to use two vias at each power pin as well as all RF bypass capacitor terminals. Dual vias reduce the interconnect inductance between layers by up to half, thereby reducing interconnect inductance and extending the effective frequency range of the bypass components. The outer layers of the PCB may be flooded with additional ground planes. These planes will improve shielding and isolation as well as increase the intrinsic capacitance of the power supply plane system. Naturally, to be effec- • Use a termination resistor which best matches the differential impedance of your transmission line. • Leave unused Bus LVDS receiver inputs open (floating). Limit traces on unused inputs to < 0.5 inches. • Isolate TTL signals from Bus LVDS signals. • Use controlled impedance media. The backplane and connectors should have a matched differential impedance. For a typical application circuit, please see Figure 8. There are more common practices which should be followed when designing PCBs for LVDS signaling. General application guidelines and hints may be found in the following application notes: AN-808, AN-903, AN-971, AN-977, and AN-1108. For packaging information on BGA’s, please see AN-1126. USING TDJIT AND TRNM TO VALIDATE SIGNAL QUALITY The parameter tRNM is calculated by first measuring how much of the ideal bit the receiver needs to ensure correct sampling. After determining this amount, what remains of the ideal bit that is available for external sources of noise is called tRNM. The vertical limits of the mask are determined by the DS92LV1260 receiver input threshold of +/− 50mV. Please refer to the eye mask pattern of Figure 10 for a graphic representation of tDJIT and tRNM. 11 www.national.com DS92LV1260 Application Information DS92LV1260 20000230 FIGURE 8. Typical Applications Circuit 20000227 FIGURE 9. Failsafe Biasing Setup 20000228 FIGURE 10. Using tDJIT and tRNM to Generate an Eye Pattern Mask and Validate Signal Quality www.national.com 12 DS92LV1260 20000215 FIGURE 11. Random Lock Hot Insertion 13 www.national.com DS92LV1260 Pin Diagram Top View of DS92LV1260 (196 pin LBGA) 20000214 www.national.com 14 DS92LV1260 Pin Descriptions Pins Pin Name Type GND GND C12,C13,B13 SEL (0:2) 3.3V CMOS I These pins control which Bus LVDS input is steered to the CHTST output A4-A3, C6-C5, A7-A6, C9-C8, A10-A9, C11-C10, A13-A12 Rin(n) +/- Bus LVDS I Bus LVDS differential input pins B2,B14 D12 Description GND pins for ESD structures PVdd Supply voltage for PLL circuitry F12 AVdd Supply voltage for input buffer circuitry B12,A14,D10 PGND GND pin for PLL circuitry B11 AGND GND pin for input buffer circuitry C7 AVdd Supply voltage for LVDS REC. B9 AVdd Supply voltage for LVDS REC. A11 AVdd Supply voltage for Band Gap reference. B7 AGND GND pin for AVDD. A8 AGND GND pin for AVDD1. B8 AGND GND pin for BGVDD. A5 AGND GND pin for VDDI. B6 AVdd Supply voltage for input logic circuitry. D7 DGND Tie to digital ground. PWRDN 3.3V CMOS I Controls whether the device is active or in ’sleep’ mode C4 RCLK_R/F 3.3V CMOS I Controls the relation of Rout data to RCLK edge: RCLK_R/F = H setup and hold times are referred to the rising RCLK edge; RCLK_R/F = L setup and hold times are referenced to the falling RCLK edge. A2 REN 3.3V CMOS I Enables the Routn, RCLKn, and SYNCCLK outputs. B4 REFCLK 3.3V CMOS I Frequency reference clock input. D5 DGND A1 DGND B1 N/C D6 DVdd Supply voltage for digital section. B3 DVdd Supply voltage for digital section. C3 CHTST 3.3V CMOS O Allows low speed testing of the Rin inputs under control of the SEL (0:2) pins. LOCK (0:5) 3.3V CMOS O Indicates the status of the PLLs for the individual deserializers: LOCK= L indicates locked, LOCK= H indicates unlicked. B5 F3,P1,N3,P12,P13,D13 E6,J5,K5,K10,J10,E9 GND pin for VDDO GND for digital section. Do not connect. DVdd Supply voltage for the logic circuitry. 15 www.national.com DS92LV1260 Pin Descriptions (Continued) Pins Pin Name Type Description K3, K4, H3, H4, H2, G4, G3, F4, E4, E2, J3, L3, J2 ,L1 ,K2 ,M1 ,N1 ,N2 ,M2 ,M3 ,M7 ,L6 ,N6 ,M6 ,P4, M5, P3, N4, P2, M4, M8, L8, N9, M9, L9, M10, M11, N11, P11, N12, K13, L12, L14, M14, L13, L11, M12, N13, N14, P14, K12, J12, J11, H12, H11, G11, G12, E12, E13, E14 Rout nx 3.3V CMOS O Outputs for the ten bit deserializers, n = deserializer number, x = bit number E5,G5,J6,K8,H9,F8 DGND GND pins for digital section. 3.3V CMOS O F2,L2,N5,N10,M13,F13 RCLK (0:5) D6, F7, E7, G6, H6, K7, K6, J8, J9, G10, H10, F10, E10 DVdd Supply voltage for output buffers. D5, F6, F5, G7, H5, J7, H7, H8, K9, G9, G8, F9, E8 DGND GND pins for output buffers. F1, E1, J1, K1, P6, P5, P9, P10, J14, K14, G14, F14 PVdd Supply voltages for PLL circuitry. G2, G1, H1, J4, N7, P7, P8, N8, J13, H14, H13, G13 PGND GND pins for PLL circuitry. C2,C1,D1,D2,D3, L4, L5, L7, L10, K11, D11, B10, D9, E3, D4, E11, F11, D8, D14, C14 www.national.com Recovered clock for each deserializer’s output data. JTL (1:5) Reserved pins for JTAG access port. N/C Unused solder ball location. Do not connect. 16 DS92LV1260 Six Channel 10 Bit BLVDS Deserializer Physical Dimensions inches (millimeters) unless otherwise noted Order Number DS92LV1260TUJB NS Package Number UJB196A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Americas Customer Support Center Email: [email protected] Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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