LMX2330L/LMX2331L/LMX2332L
PLLatinum™ Low Power Dual Frequency Synthesizer for
RF Personal Communications
LMX2330L
LMX2331L
2.5 GHz/510 MHz
2.0 GHz/510 MHz
LMX2332L
1.2 GHz/510 MHz
Features
General Description
The LMX233XL family of monolithic, integrated dual frequency synthesizers, including prescalers, is to be used as a
local oscillator for RF and first IF of a dual conversion transceiver. It is fabricated using National’s 0.5µ ABiC V silicon
BiCMOS process.
The LMX233XL contains dual modulus prescalers. A 64/65
or a 128/129 prescaler (32/33 or 64/65 in the 2.5 GHz
LMX2330L) can be selected for the RF synthesizer and a 8/9
or a 16/17 prescaler can be selected for the IF synthesizer.
LMX233XL, which employs a digital phase locked loop technique, combined with a high quality reference oscillator, provides the tuning voltages for voltage controlled oscillators to
generate very stable, low noise signals for RF and IF local
oscillators. Serial data is transferred into the LMX233XL via
a three wire interface (Data, Enable, Clock). Supply voltage
can range from 2.7V to 5.5V. The LMX233XL family features
very low current consumption;
LMX2330L — 5.0 mA at 3V, LMX2331L — 4.0 mA at 3V,
LMX2332L — 3.0 mA at 3V.
The LMX233XL are available in a TSSOP 20-pin and CSP
24-pin surface mount plastic package.
n Ultra low current consumption
n 2.7V to 5.5V operation
n Selectable synchronous or asynchronous powerdown
mode:
ICC = 1 µA typical at 3V
n Dual modulus prescaler:
LMX2330L
(RF) 32/33 or 64/65
LMX2331L/32L
(RF) 64/65 or 128/129
LMX2330L/31L/32L (IF) 8/9 or 16/17
n Selectable charge pump TRI-STATE ® mode
n Selectable charge pump current levels
n Selectable Fastlock™ mode
n Upgrade and compatible to LMX233XA family
Applications
n Portable Wireless Communications
(PCS/PCN, cordless)
n Cordless and cellular telephone systems
n Wireless Local Area Networks (WLANs)
n Cable TV tuners (CATV)
n Other wireless communication systems
Functional Block Diagram
DS012806-1
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
Fastlock™, MICROWIRE™ and PLLatinum™ are trademarks of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS012806
www.national.com
LMX2330L/LMX2331L/LMX2332L PLLatinum Low Power Dual Frequency Synthesizer for RF
Personal Communications
June 1999
Connection Diagrams
Chip Scale Package (SLB)
(Top View)
Thin Shrink Small Outline Package (TM)
(Top View)
DS012806-2
Order Number LMX2330LTM, LMX2331LTM or
LMX2332LTM
NS Package Number MTC20
DS012806-39
Order Number LMX2330LSLB, LMX2331LSLB or
LMX2332LSLB
NS Package Number SLB24A
Pin Descriptions
Pin No.
LMX233XLSLB
24-pinCSP
Package
Pin No.
LMX233XLTM
20-pin TSSOP
Package
24
1
VCC1
—
Power supply voltage input for RF analog and RF digital circuits. Input
may range from 2.7V to 5.5V. VCC1 must equal VCC2. Bypass
capacitors should be placed as close as possible to this pin and be
connected directly to the ground plane.
2
2
VP1
—
Power Supply for RF charge pump. Must be ≥ VCC.
3
3
Do RF
O
Internal charge pump output. For connection to a loop filter for driving
the input of an external VCO.
4
4
GND
—
Ground for RF digital circuitry.
5
5
fIN RF
I
RF prescaler input. Small signal input from the VCO.
6
6
fIN RF
I
RF prescaler complementary input. A bypass capacitor should be
placed as close as possible to this pin and be connected directly to the
ground plane. Capacitor is optional with some loss of sensitivity.
7
7
GND
—
8
8
OSCin
I
Oscillator input. The input has a VCC/2 input threshold and can be
driven from an external CMOS or TTL logic gate.
Pin
Name
I/O
Description
Ground for RF analog circuitry.
10
9
GND
—
Ground for IF digital, MICROWIRE™, FoLD, and oscillator circuits.
11
10
FoLD
O
Multiplexed output of the RF/IF programmable or reference dividers,
RF/IF lock detect signals and Fastlock mode. CMOS output (see
Programmable Modes).
12
11
Clock
I
High impedance CMOS Clock input. Data for the various counters is
clocked in on the rising edge, into the 22-bit shift register.
14
12
Data
I
Binary serial data input. Data entered MSB first. The last two bits are
the control bits. High impedance CMOS input.
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2
Pin Descriptions
(Continued)
Pin No.
LMX233XLSLB
24-pinCSP
Package
Pin No.
LMX233XLTM
20-pin TSSOP
Package
15
13
LE
16
14
GND
—
17
15
fIN IF
I
18
16
fIN IF
I
19
17
GND
—
Ground for IF digital, MICROWIRE, FoLD, and oscillator circuits.
20
18
Do IF
O
IF charge pump output. For connection to a loop filter for driving the
input of an external VCO.
Pin
Name
I/O
I
Description
Load enable high impedance CMOS input. When LE goes HIGH, data
stored in the shift registers is loaded into one of the 4 appropriate
latches (control bit dependent).
Ground for IF analog circuitry.
IF prescaler complementary input. A bypass capacitor should be placed
as close as possible to this pin and be connected directly to the ground
plane. Capacitor is optional with some loss of sensitivity.
IF prescaler input. Small signal input from the VCO.
22
19
VP2
—
Power Supply for IF charge pump. Must be ≥ VCC.
23
20
VCC2
—
Power supply voltage input for IF analog, IF digital, MICROWIRE,
FoLD, and oscillator circuits. Input may range from 2.7V to 5.5V. VCC2
must equal VCC1. Bypass capacitors should be placed as close as
possible to this pin and be connected directly to the ground plane.
1, 9, 13, 21
X
NC
—
No connect.
3
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Block Diagram
DS012806-3
Note: The RF prescaler for the LMX2331L/32L is either 64/65 or 128/129, while the prescaler for the LMX2330L is 32/33 or 64/65.
Note: VCC1 supplies power to the RF prescaler, N-counter, R-counter and phase detector. VCC2 supplies power to the IF prescaler, N-counter, phase detector,
R-counter along with the OSCin buffer, MICROWIRE, and FoLD. VCC1 and VCC2 are clamped to each other by diodes and must be run at the same voltage level.
Note: VP1 and VP2 can be run separately as long as VP ≥ VCC.
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4
Absolute Maximum Ratings
Recommended Operating
Conditions
(Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Power Supply Voltage
VCC
VP
Voltage on Any Pin
with GND = 0V (VI)
Storage Temperature Range (TS)
Lead Temperature (solder 4 sec.) (TL)
Power Supply Voltage
VCC
VP
Operating Temperature (TA)
−0.3V to +6.5V
−0.3V to +6.5V
2.7V to 5.5V
VCC to +5.5V
−40˚C to +85˚C
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee
specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply
only for the test conditions listed.
−0.3V to VCC+0.3V
−65˚C to +150˚C
+260˚C
Note 2: This device is a high performance RF integrated circuit with an ESD
rating < 2 keV and is ESD sensitive. Handling and assembly of this device
should only be done at ESD protected work stations.
Electrical Characteristics
VCC = 3.0V, VP = 3.0V; −40˚C < TA < 85˚C, except as specified
Symbol
ICC
Parameter
Conditions
VCC = 2.7V to 5.5V
Max
Power
LMX2330L RF + IF
5.0
6.6
LMX2330L RF Only
4.0
5.2
5.4
LMX2331L RF + IF
4.0
LMX2331L RF Only
3.0
4.0
LMX2332L IF + RF
3.0
4.1
LMX2332L RF Only
2.0
2.7
LMX233xL IF Only
1.0
1.4
ICC-PWDN Powerdown Current
fIN IF
Typ
Supply
Current
fIN RF
Value
Min
(Note 3)
1
10
Units
mA
µA
Operating
LMX2330L
0.5
2.5
Frequency
LMX2331L
0.2
2.0
LMX2332L
0.1
1.2
LMX233xL
45
510
MHz
40
MHz
Operating
GHz
Frequency
fOSC
Oscillator Frequency
5
fφ
Maximum Phase Detector
10
MHz
Frequency
PfIN IF
IF Input Sensitivity
VCC = 3.0V
VCC = 5.0V
VCC = 2.7V to 5.5V
VOSC
Oscillator Sensitivity
OSCin
VIH
High-Level Input Voltage
(Note 4)
VIL
Low-Level Input Voltage
IIH
High-Level Input Current
IIL
Low-Level Input Current
IIH
Oscillator Input Current
(Note 4)
VIH = VCC = 5.5V
(Note 4)
VIL = 0V, VCC = 5.5V
(Note 4)
VIH = VCC = 5.5V
IIL
Oscillator Input Current
VOH
High-Level Output Voltage
(for FoLD, pin number 10)
VOL
Low-Level Output Voltage (for
FoLD, pin number 10)
tCS
Data to Clock Set Up Time
See Data Input Timing
50
ns
tCH
Data to Clock Hold Time
See Data Input Timing
10
ns
tCWH
Clock Pulse Width High
See Data Input Timing
50
ns
tCWL
Clock Pulse Width Low
See Data Input Timing
50
ns
PfIN RF
RF Input Sensitivity
VIL = 0V, VCC = 5.5V
IOH = −500 µA
−15
0
dBm
−10
0
dBm
−10
0
dBm
0.5
V
0.2 VCC
V
−1.0
1.0
µA
−1.0
1.0
µA
100
µA
−100
µA
VCC − 0.4
V
IOL = 500 µA
5
VPP
0.8 VCC
0.4
V
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Electrical Characteristics
(Continued)
VCC = 3.0V, VP = 3.0V; −40˚C < TA < 85˚C, except as specified
Symbol
Parameter
Value
Conditions
Min
Typ
Max
Units
tES
Clock to Load Enable Set Up Time
See Data Input Timing
50
ns
tEW
Load Enable Pulse Width
See Data Input Timing
50
ns
Note 3: Clock, Data and LE = GND or Vcc.
Note 4: Clock, Data and LE does not include fIN RF, fIN IF and OSCIN.
Charge Pump Characteristics
VCC = 3.0V, VP = 3.0V; −40˚C < TA ≤ 85˚C, except as specified
Symbol
Parameter
IDo-SOURCE
Charge Pump Output
IDo-SINK
Current
IDo-SOURCE
IDo-SINK
IDo-TRI
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mA
−1
mA
= LOW (Note 5)
1
mA
CP Current vs
Temperature (Note 8)
−40˚C ≤ TA ≤ 85˚C
Note 5: See PROGRAMMABLE MODES for ICPo description.
6
Units
mA
0.5 ≤ VDo ≤ VP − 0.5V
TA = 25˚C
VDo = VP/2
CP Current vs Voltage
(Note 6)
Max
4.0
0.5V ≤ VDo ≤ VP − 0.5V
CP Sink vs
Typ
−4.0
−40˚C < TA < 85˚C
VDo = VP/2
TA = 25˚C
Source Mismatch (Note 7)
Value
Min
= HIGH (Note 5)
= HIGH (Note 5)
= LOW (Note 5)
Charge Pump
IDo-SOURCE
IDo vs TA
VDo = VP/2, ICPo
VDo = VP/2, ICPo
VDo = VP/2, ICPo
VDo = VP/2, ICPo
TRI-STATE Current
IDo-SINK vs
IDo vs VDo
Conditions
−2.5
2.5
nA
3
10
%
10
15
%
10
%
Charge Pump Current Specification Definitions
DS012806-37
I1 = CP sink current at VDo = VP − ∆V
I2 = CP sink current at VDo = VP/2
I3 = CP sink current at VDo = ∆V
I4 = CP source current at VDo = VP − ∆V
I5 = CP source current at VDo = VP/2
I6 = CP source current at VDo = ∆V
∆V = Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to VCC and ground. Typical values are between 0.5V and 1.0V.
Note 6: IDo vs VDo =
Charge Pump Output Current magnitude variation vs Voltage =
[1⁄2 * {|I1| − |I3|}]/[1⁄2 * {|I1| + |I3|}] * 100%
Note 7: IDo-sink vs IDo-source =
and
[1⁄2 * {|I4| − |I6|}]/[1⁄2 * {|I4| + |I6|}] * 100%
Charge Pump Output Current Sink vs Source Mismatch =
[|I2| − |I5|]/[1⁄2 * {|I2| + |I5|}] * 100%
Note 8: IDo vs TA =
Charge Pump Output Current magnitude variation vs Temperature =
[|I2 @ temp| − |I2 @ 25˚C|]/|I2 @ 25˚C| * 100%
and
[|I5 @ temp| − |I5 @ 25˚C|]/|I5 @ 25˚C| * 100%
7
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RF Sensitivity Test Block Diagram
DS012806-38
Note 1: N = 10,000
R = 50
P = 64
Note 2: Sensitivity limit is reached when the error of the divided RF output, FoLD, is ≥ 1 Hz.
Typical Performance Characteristics
ICC vs VCC
LMX2330L
ICC vs VCC
LMX2331L
DS012806-19
ICC vs VCC
LMX2332L
DS012806-20
IDo TRI-STATE
vs Do Voltage
DS012806-21
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DS012806-22
8
Typical Performance Characteristics
(Continued)
Charge Pump Current vs Do Voltage
ICP = HIGH
Charge Pump Current vs Do Voltage
ICP = LOW
DS012806-23
Charge Pump Current Variation
(See (Note 6) under Charge Pump Current
Specification Definitions)
DS012806-24
Sink vs Source Mismatch
(See (Note 7) under Charge Pump Current
Specification Definitions)
DS012806-25
DS012806-26
9
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Typical Performance Characteristics
(Continued)
RF Input Impedance
VCC = 2.7V to 5.5V, fIN = 50 MHz to 3 GHz
IF Input Impedance
VCC = 2.7V to 5.5V, fIN = 50 MHz to 1000 MHz
DS012806-28
DS012806-27
LMX2330L RF Sensitivity vs Frequency
LMX2331L RF Sensitivity vs Frequency
DS012806-29
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DS012806-30
10
Typical Performance Characteristics
(Continued)
LMX2332L RF Sensitivity vs Frequency
IF Input Sensitivity vs Frequency
DS012806-31
DS012806-32
Oscillator Input Sensitivity vs Frequency
DS012806-33
11
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Functional Description
The simplified block diagram below shows the 22-bit data register, two 15-bit R Counters and the 15- and 18-bit N Counters (intermediate latches are not shown). The data stream is clocked (on the rising edge of Clock) into the DATA register, MSB first. The
data stored in the shift register is loaded into one of 4 appropriate latches on the rising edge of LE. The last two bits are the Control Bits. The DATA is transferred into the counters as follows:
Control Bits
DATA Location
C1
C2
0
0
IF R Counter
0
1
RF R Counter
1
0
IF N Counter
1
1
RF N Counter
DS012806-6
PROGRAMMABLE REFERENCE DIVIDERS (IF AND RF R COUNTERS)
If the Control Bits are 00 or 01 (00 for IF and 01 for RF) data is transferred from the 22-bit shift register into a latch which sets
the 15-bit R Counter. Serial data format is shown below.
DS012806-7
15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)
Divide
Ratio
R
R
R
R
R
R
R
R
R
R
15 14 13 12 11 10
R
R
R
R
R
9
8
7
6
5
4
3
2
1
3
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
•
32767
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
1
Notes:
Divide ratios less than 3 are prohibited.
Divide ratio: 3 to 32767
R1 to R15: These bits select the divide ratio of the programmable reference divider.
Data is shifted in MSB first.
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12
•
Functional Description
(Continued)
PROGRAMMABLE DIVIDER (N COUNTER)
The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control
Bits are 10 or 11 (10 for IF counter and 11 for RF counter) data is transferred from the 22-bit shift register into a 4-bit or 7-bit latch
(which sets the Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter), MSB first. Serial data
format is shown below. For the IF N counter bits 5, 6, and 7 are don’t care bits. The RF N counter does not have don’t care
bits.
DS012806-8
7-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER)
RF
IF
Divide
N
7
N
6
N
5
N
4
N
3
N
2
N
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
•
127
•
1
•
1
•
1
•
1
•
1
•
1
•
1
Ratio
Divide
N
7
N
6
N
5
N
4
N
3
N
2
N
1
0
X
X
X
0
0
0
0
1
X
X
X
0
0
0
1
•
15
•
X
•
X
•
X
•
1
•
1
•
1
1
Ratio
A
A
•
X = DON’T CARE condition
Notes: Divide ratio: 0 to 127
B≥A
11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER)
Divide
N
18
N
17
N
16
N
15
N
14
N
13
N
12
N
11
N
10
N
9
N
8
3
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
1
0
0
•
2047
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
1
Ratio
B
•
Note: Divide ratio: 3 to 2047 (Divide ratios less than 3 are prohibited)
B≥A
PULSE SWALLOW FUNCTION
fVCO = [(P x B) + A] x fOSC/R
fVCO: Output frequency of external voltage controlled oscillator (VCO)
B:
Preset divide ratio of binary 11-bit programmable counter (3 to 2047)
A:
fOSC:
R:
P:
Preset divide ratio of binary 7-bit swallow counter
(0 ≤ A ≤ 127 {RF}, 0 ≤ A ≤ 15 {IF}, A ≤ B)
Output frequency of the external reference frequency oscillator
Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767)
Preset modulus of dual moduIus prescaler (for IF; P = 8 or 16;
for RF; LMX2330L: P = 32 or 64
LMX2331L/32L: P = 64 or 128)
13
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Functional Description
(Continued)
PROGRAMMABLE MODES
Several modes of operation can be programmed with bits R16–R20 including the phase detector polarity, charge pump
TRI-STATE and the output of the FoLD pin. The prescaler and powerdown modes are selected with bits N19 and N20. The programmable modes are shown in Table 1. Truth table for the programmable modes and FoLD output are shown in Table 2 and
Table 3.
TABLE 1. Programmable Modes
C1
C2
R16
R17
R18
R19
R20
0
0
IF Phase
IF ICPo
IF Do
IF LD
IF Fo
0
1
RF LD
RF Fo
Detector Polarity
RF Phase
TRI-STATE
RF ICPo
RF Do
Detector Polarity
TRI-STATE
C1
C2
N19
N20
1
0
IF Prescaler
Pwdn IF
1
1
RF Prescaler
Pwdn RF
TABLE 2. Mode Select Truth Table
Phase Detector Polarity
Do TRI-STATE
ICPo
IF
2330L RF
2331L/32L RF
Pwdn
(Note 11)
(Note 9)
(Note 10)
Prescaler
Prescaler
Prescaler
(Note 9)
0
Negative
Normal Operation
LOW
8/9
32/33
64/65
Pwrd Up
1
Positive
TRI-STATE
HIGH
16/17
64/65
128/129
Pwrd Dn
Note 9: Refer to POWERDOWN OPERATION in Functional Description.
Note 10: The ICPo LOW current state = 1/4 x ICPo HIGH current.
Note 11: PHASE DETECTOR POLARITY
Depending upon VCO characteristics, R16 bit should be set accordingly: (see figure right)
When VCO characteristics are positive like (1), R16 should be set HIGH;
When VCO characteristics are negative like (2), R16 should be set LOW.
VCO Characteristics
DS012806-9
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14
Functional Description
(Continued)
TABLE 3. The FoLD (Pin 10) Output Truth Table
RF R[19]
IF R[19]
RF R[20]
IF R[20]
(RF LD)
(IF LD)
(RF Fo)
(IF Fo)
0
0
0
0
Disabled (Note 12)
0
1
0
0
IF Lock Detect (Note 13)
1
0
0
0
RF Lock Detect (Note 13)
1
1
0
0
RF/IF Lock Detect (Note 13)
X
0
0
1
IF Reference Divider Output
X
0
1
0
RF Reference Divider Output
X
1
0
1
IF Programmable Divider Output
X
1
1
0
RF Programmable Divider Output
0
0
1
1
Fastlock (Note 14)
0
1
1
1
IF Counter Reset (Note 15)
1
0
1
1
RF Counter Reset (Note 15)
1
1
1
1
IF and RF Counter Reset (Note 15)
Fo Output State
X = don’t care condition
Note 12: When the FoLD output is disabled, it is actively pulled to a low logic state.
Note 13: Lock detect output provided to indicate when the VCO frequency is in “lock.” When the loop is locked and a lock detect mode is selected, the pins output
is HIGH, with narrow pulses LOW. In the RF/IF lock detect mode a locked condition is indicated when RF and IF are both locked.
Note 14: The Fastlock mode utilizes the FoLD output pin to switch a second loop filter damping resistor to ground during fastlock operation. Activation of Fastlock
occurs whenever the RF loop’s lcpo magnitude bit #17 is selected HIGH (while the #19 and #20 mode bits are set for Fastlock).
Note 15: The IF Counter Reset mode resets IF PLL’s R and N counters and brings IF charge pump output to a TRI-STATE condition. The RF Counter Reset mode
resets RF PLL’s R and N counters and brings RF charge pump output to a TRI-STATE condition. The IF and RF Counter Reset mode resets all counters and brings
both charge pump outputs to a TRI-STATE condition. Upon removal of the Reset bits then N counter resumes counting in “close” alignment with the R counter. (The
maximum error is one prescaler cycle.)
POWERDOWN OPERATION
Synchronous and asynchronous powerdown modes are
both available by MICROWIRE selection. Synchronously
powerdown occurs if the respective loop’s R18 bit (Do
TRI-STATE) is LOW when its N20 bit (Pwdn) becomes HI.
Asynchronous powerdown occurs if the loop’s R18 bit is HI
when its N20 bit becomes HI.
In the synchronous powerdown mode, the powerdown function is gated by the charge pump to prevent unwanted frequency jumps. Once the powerdown program bit N20 is
loaded, the part will go into powerdown mode when the
charge pump reaches a TRI-STATE condition.
In the asynchronous powerdown mode, the device powers
down immediately after the LE pin latches in a HI condition
on the powerdown bit N20.
Activation of either the IF or RF PLL powerdown conditions
in either synchronous or asynchronous modes forces the respective loop’s R and N dividers to their load state condition
and debiasing of its respective fIN input to a high impedance
state. The oscillator circuitry function does not become disabled until both IF and RF powerdown bits are activated. The
MICROWIRE control register remains active and capable of
loading and latching data during all of the powerdown
modes.
The device returns to an actively powered up condition in either synchronous or asynchronous modes immediately upon
LE latching LOW data into bit N20.
Powerdown Mode Select Table
15
R18
N20
0
0
PLL Active
Powerdown Status
1
0
PLL Active
(Charge Pump Output TRI-STATE)
0
1
Synchronous Powerdown Initiated
1
1
Asynchronous Powerdown Initiated
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Functional Description
(Continued)
SERIAL DATA INPUT TIMING
DS012806-10
Note 1: Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
Note 2: tcs = Data to Clock Set-Up Time
tCH = Data to Clock Hold Time
tCWH = Clock Pulse Width High
tCWL = Clock Pulse Width Low
tES = Clock to Load Enable Set-Up Time
tEW = Load Enable Pulse Width
Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an edge rate of 0.6 V/ns with
amplitudes of 2.2V @ VCC = 2.7V and 2.6V @ VCC = 5.5V.
PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS
DS012806-11
Notes: Phase difference detection range: −2π to +2π
The minimum width pump up and pump down current pulses occur at the Do pin when the loop is locked.
R16 = HIGH
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16
Typical Application Example
DS012806-12
Operational Notes:
* VCO is assumed AC coupled.
** RIN increases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10Ω to 200Ω depending on the VCO
power level. fIN RF impedance ranges from 40Ω to 100Ω. fIN IF impedances are higher.
*** Adding RC filters to the VCC lines is recommended to reduce loop-to-loop noise coupling.
DS012806-13
Application Hints:
Proper use of grounds and bypass capacitors is essential to achieve a high level of performance. Crosstalk between pins can be reduced by careful
board layout.
This is an electrostatic sensitive device. It should be handled only at static free work stations.
17
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Application Information
A block diagram of the basic phase locked loop is shown in Figure 1.
DS012806-14
FIGURE 1. Basic Charge Pump Phase Locked Loop
LOOP GAIN EQUATIONS
A linear control system model of the phase feedback for a
PLL in the locked state is shown in Figure 2. The open loop
gain is the product of the phase comparator gain (Kφ), the
VCO gain (KVCO/s), and the loop filter gain Z(s) divided by
the gain of the feedback counter modulus (N). The passive
loop filter configuration used is displayed in Figure 3, while
the complex impedance of the filter is given in Equation (1).
(4)
From Equations (2), (3) we can see that the phase term will
be dependent on the single pole and zero such that the
phase margin is determined in Equation (5).
(5)
φ(ω) = tan −1 (ω • T2) − tan−1 (ω • T1) + 180˚
A plot of the magnitude and phase of G(s)H(s) for a stable
loop, is shown in Figure 4 with a solid trace. The parameter
φp shows the amount of phase margin that exists at the point
the gain drops below zero (the cutoff frequency wp of the
loop). In a critically damped system, the amount of phase
margin would be approximately 45 degrees.
If we were now to redefine the cut off frequency, wp’, as
double the frequency which gave us our original loop bandwidth, wp, the loop response time would be approximately
halved. Because the filter attenuation at the comparison frequency also diminishes, the spurs would have increased by
approximately 6 dB. In the proposed Fastlock scheme, the
higher spur levels and wider loop filter conditions would exist
only during the initial lock-on phase — just long enough to
reap the benefits of locking faster. The objective would be to
open up the loop bandwidth but not introduce any additional
complications or compromises related to our original design
criteria. We would ideally like to momentarily shift the curve
of Figure 4 over to a different cutoff frequency, illustrated by
the dotted line, without affecting the relative open loop gain
and phase relationships. To maintain the same gain/phase
relationship at twice the original cutoff frequency, other terms
in the gain and phase Equation (4) and Equation (5) will have
to compensate by the corresponding “1/w” or “1/w2” factor.
Examination of equations Equations (2), (3) and Equation (5)
indicates the damping resistor variable R2 could be chosen
to compensate the “w”’ terms for the phase margin. This implies that another resistor of equal value to R2 will need to be
switched in parallel with R2 during the initial lock period. We
must also insure that the magnitude of the open loop gain,
H(s)G(s) is equal to zero at wp’ = 2wp. Kvco, Kφ, N, or the net
product of these terms can be changed by a factor of 4, to
counteract the w2 term present in the denominator of Equation (2) and Equation (3). The Kφ term was chosen to complete the transformation because it can readily be switched
DS012806-15
FIGURE 2. PLL Linear Model
DS012806-16
FIGURE 3. Passive Loop Filter
(1)
The time constants which determine the pole and zero frequencies of the filter transfer function can be defined as
(2)
and
(3)
T2 = R2 • C2
The 3rd order PLL Open Loop Gain can be calculated in
terms of frequency, ω, the filter time constants T1 and T2,
and the design constants Kφ, KVCO, and N.
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18
Application Information
(Continued)
between 1X and 4X values. This is accomplished by increasing the charge pump output current from 1 mA in the standard mode to 4 mA in Fastlock.
DS012806-17
FIGURE 4. Open Loop Response Bode Plot
FASTLOCK CIRCUIT IMPLEMENTATION
tical damping resistor is wired in appropriately, the loop will
lock faster without any additional stability considerations to
account for. Once locked on the correct frequency, the user
can return the PLL to standard low noise operation by sending a MICROWIRE instruction with the RF Icpo bit set low.
This transition does not affect the charge on the loop filter
capacitors and is enacted synchronous with the charge
pump output. This creates a nearly seamless change between Fastlock and standard mode.
A diagram of the Fastlock scheme as implemented in National Semiconductors LMX233XL PLL is shown in Figure 5.
When a new frequency is loaded, and the RF Icpo bit is set
high the charge pump circuit receives an input to deliver 4
times the normal current per unit phase error while an open
drain NMOS on chip device switches in a second R2 resistor
element to ground. The user calculates the loop filter component values for the normal steady state considerations. The
device configuration ensures that as long as a second iden-
DS012806-18
FIGURE 5. Fastlock PLL Architecture
19
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Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead (0.173" Wide) Thin Shrink Small Outline Package (TM)
Order Number LMX2330LTM, LMX2331LTM or LMX2332LTM
*For Tape and Reel (2500 units per reel)
Order Number LMX2330LTMX, LMX2331LTMX or LMX2332LTMX
NS Package Number MTC20
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20
inches (millimeters) unless otherwise noted (Continued)
24-Pin Chip Scale Package
Order Number LMX2330LSLB, LMX2331LSLB or LMX2332LSLB
*For Tape and Reel (2500 Units per Reel)
Order Number LMX2330LSLBX, LMX2331LSLBX or LMX2332LSLBX
NS Package Number SLB24A
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LMX2330L/LMX2331L/LMX2332L PLLatinum Low Power Dual Frequency Synthesizer for RF
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Physical Dimensions