February 1990 MM54HCT573/MM74HCT573 TRI-STATEÉ Octal D-Type Latch MM54HCT574/MM74HCT574 TRI-STATE Octal D-Type Flip-Flop General Description The MM54HCT573/MM74HCT573 octal D-type latches and MM54HCT574/MM74HCT574 Octal D-type flip flops advanced silicon-gate CMOS technology, which provides the inherent benefits of low power consumption and wide power supply range, but are LS-TTL input and output characteristic & pin-out compatible. The TRI-STATE outputs are capable of driving 15 LS-TTL loads. All inputs are protected from damage due to static discharge by internal diodes to VCC and ground. When the MM54HCT573/MM74HCT573 LATCH ENABLE input is high, the Q outputs will follow the D inputs. When the LATCH ENABLE goes low, data at the D inputs will be retained at the outputs until LATCH ENABLE returns high again. When a high logic level is applied to the OUTPUT CONTROL input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The MM54HCT574/MM74HCT574 are positive edge triggered flip-flops. Data at the D inputs, meeting the setup and hold time requirements, are transferred to the Q outputs on positive going transitions of the CLOCK (CK) input. When a high logic level is applied to the OUTPUT CONTROL (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. MM54HCT/MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug in replacements for LSTTL devices and can be used to reduce power consumption in existing designs. Features Y Y Y Y Y Y TTL input characteristic compatible Typical propagation delay: 18 ns Low input current: 1 mA maximum Low quiescent current: 80 mA maximum Compatible with bus-oriented systems Output drive capability: 15 LS-TTL loads Connection Diagram Dual-In-Line Package TL/F/10627 – 1 Top View Order Number MM54HCT573* or MM74HCT573* TL/F/10627 – 2 Top View Order Number MM54HCT574* or MM74HCT574* *Please look into Section 8, Appendix D for availability of various package types. TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/10627 RRD-B30M105/Printed in U. S. A. MM54HCT573/MM74HCT573 TRI-STATE Octal D-Type Latch MM54HCT574/MM74HCT574 TRI-STATE Octal D-Type Flip-Flop PRELIMINARY Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) b 0.5 to a 7.0V Supply Voltage (VCC) b 1.5 to VCC a 1.5V DC Input Voltage (VIN) b 0.5 to VCC a 0.5V DC Output Voltage (VOUT) g 20 mA Clamp Diode Current (IIK, IOK) g 35 mA DC Output Current, per pin (IOUT) g 70 mA DC VCC or GND Current, per pin (ICC) b 65§ C to a 150§ C Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Lead Temp. (TL) (Soldering 10 seconds) 260§ C Operating Temp. Range (TA) MM74HCT MM54HCT Min 4.5 Max 5.5 0 VCC Units V V b 40 b 55 a 85 a 125 §C §C 500 ns Input Rise or Fall Times (tr, tf) DC Electrical Characteristics VCC e 5V g 10% (unless otherwise specified) Symbol Parameter TA e 25§ C Conditions 74HCT TA eb40 to 85§ C Typ 54HCT TA eb55 to 125§ C Units Guaranteed Limits VIH Minimum High Level Input Voltage 2.0 2.0 2.0 V VIL Maximum Low Level Input Voltage 0.8 0.8 0.8 V VOH Minimum High Level Output Voltage VIN e VIH or VIL lIOUTl e 20 mA lIOUTl e 6.0 mA, VCC e 4.5V lIOUTl e 7.2 mA, VCC e 5.5V VCC 4.2 5.7 VCCb0.1 3.98 4.98 VCCb0.1 3.84 4.84 VCCb0.1 3.7 4.7 V V V Maximum Low Level Voltage VIN e VIH or VIL lIOUTl e 20 mA lIOUTl e 6.0 mA, VCC e 4.5V lIOUTl e 7.2 mA, VCC e 5.5V 0 0.2 0.2 0.1 0.26 0.26 0.1 0.33 0.33 0.1 0.4 0.4 V V V IIN Maximum Input Current VIN e VCC or GND, VIH or VIL g 0.1 g 1.0 g 1.0 mA IOZ Maximum TRI-STATE Output Leakage Current VOUT e VCC or GND Enable e VIH or VIL g 0.5 g 5.0 g 10 mA ICC Maximum Quiescent Supply Current VIN e VCC or GND IOUT e 0 mA 8.0 80 160 mA VIN e 2.4V or 0.5V (Note 4) 1.5 1.8 2.0 mA VOL Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C. Note 4: Measured per pin. All others tied to VCC or ground. 2 AC Electrical Characteristics MM54HCT573/MM74HCT573 VCC e 5.0V, tr e tf e 6 ns TA e 25§ C (unless otherwise specified) Symbol Parameter Conditions Typ Guaranteed Limit Units 17 27 ns tPHL, tPLH Maximum Propagation Delay Data to Output CL e 45 pF tPHL, tPLH Maximum Propagation Delay Latch Enable to Output CL e 45 pF 16 27 ns tPZH, tPZL Maximum Enable Propagation Delay Control to Output CL e 45 pF RL e 1 kX 21 30 ns tPHZ, tPLZ Maximum Disable Propagation Delay Control to Output CL e 5 pF RL e 1 kX 14 23 ns tW Minimum Clock Pulse Width 15 ns tS Minimum Setup Time Data to Clock 5 ns tH Minimum Hold Time Clock to Data 12 ns AC Electrical Characteristics MM54HCT573/MM74HCT573 VCC e 5.0V g 10%, tr e tf e 6 ns (unless otherwise specified) Symbol Parameter Conditions TA e 25§ C 74HCT TA eb40 to 85§ C Typ 54HCT TA eb55 to 125§ C Units Guaranteed Limits tPHL, tPLH Maximum Propagation Delay Data to Output CL e 50 pF 18 30 38 45 ns tPHL, tPLH Maximum Propagation Delay Latch Enable to Output CL e 50 pF 17 30 44 53 ns tPZH, tPZL Maximum Enable Propagation Delay Control to Output CL e 50 pF RL e 1 kX 22 30 38 45 ns tPHZ, tPLZ Maximum Disable Propagation Delay Control to Output CL e 50 pF RL e 1 kX 15 30 38 45 ns tTHL, tTLH Maximum Output Rise and Fall Time CL e 50 pF 6 12 15 18 ns tW Minimum Clock Pulse Width 15 20 24 ns tS Minimum Setup Time Data to Clock b3 5 6 8 ns tH Minimum Hold Time Clock to Data 4 CIN Maximum Input Capacitance COUT Maximum Output Capacitance CPD Power Dissipation Capacitance (Note 5) OC e VCC OC e GND 12 15 18 ns 10 10 10 pF 20 20 20 pF 5 52 pF pF Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC. Truth Table ’HCT573 ’HCT574 Output Control LE Data Output Output Control L L L H H H L X H L X X H L Q0 Z L L L H H e high level, L e low level Clock Data Output u u H L X X H L Q0 Z L X H e High Level, L e Low Level Q0 e level of output before steady-state input conditions were established. X e Don’t Care u e Transition from low-to-high Z e high impedance Z e High impedance state Q0 e The level of the output before steady state input conditions were established. 3 AC Electrical Characteristics MM54HCT574/MM74HCT574 VCC e 5.0V, tr e tf e 6 ns TA e 25§ C (unless otherwise specified) Symbol Parameter Conditions Typ Guaranteed Limit Units fMAX Maximum Clock Frequency 60 33 MHz tPHL, tPLH Maximum Propagation Delay to Output CL e 45 pF 17 27 ns tPZH, tPZL Maximum Enable Propagation Delay Control to Output CL e 45 pF RL e 1 kX 19 28 ns tPHZ, tPLZ Maximum Disable Propagation Delay Control to Output CL e 5 pF RL e 1 kX 14 25 ns tW Minimum Clock Pulse Width 15 ns tS Minimum Setup Time Data to Clock 12 ns tH Minimum Hold Time Clock to Data 5 ns AC Electrical Characteristics MM54HCT574/MM74HCT574 VCC e 5.0V g 10%, tr e tf e 6 ns (unless otherwise specified) Symbol Parameter Conditions TA e 25§ C Typ fMAX Maximum Clock Frequency 74HCT 54HCT TA eb40 to 85§ C TA eb55 to 125§ C Units Guaranteed Limits 33 28 23 MHz 18 30 38 45 ns tPHL, tPLH Maximum Propagation Delay Clock to Output CL e 50 pF tPZH, tPZL Maximum Enable Propagation Delay Control to Output CL e 50 pF RL e 1 kX 22 30 38 45 ns tPHZ, tPLZ Maximum Disable Propagation Delay Control to Output CL e 50 pF RL e 1 kX 15 30 38 45 ns tTHL, tTLH Maximum Output Rise and Fall Time CL e 50 pF 6 12 15 18 ns ns tW Minimum Clock Pulse Width 15 20 24 tS Minimum Setup Time Data to Clock 6 12 15 18 ns tH Minimum Hold Time Clock to Data b1 5 6 8 ns CIN Maximum Input Capacitance 10 10 10 pF COUT Maximum Output Capacitance 20 20 20 CPD Power Dissipation Capacitance (Note 5) OC e VCC OC e GND 5 58 pF pF pF Note 5: CPD determines the no load power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC. 4 Physical Dimensions inches (millimeters) Order Number MM74HCT573/HCT574 (WM) NS Package Number M20B 5 MM54HCT573/MM74HCT573 TRI-STATE Octal D-Type Latch MM54HCT574/MM74HCT574 TRI-STATE Octal D-Type Flip-Flop Physical Dimensions inches (millimeters) (Continued) Lit. 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