Si52146 PCI-EXPRESS GEN 1, GEN 2, & GEN 3 SIX OUTPUT CLOCK GENERATOR Features Ordering Information: See page 18 The Si52146 is a spread-controlled PCIe clock generator that can source six PCIe clocks simultaneously. The device has six hardware inputs for enabling the respective outputs on the fly while powered on along with the spread control hardware pin to enable Spread for EMI reduction. Functional Block Diagram 29 28 27 26 25 1 24 VDD OE21 2 23 DIFF5 SSON 2 3 22 DIFF5 OE31 4 OE41 5 OE51 6 19 DIFF4 NC 7 18 VDD 8 17 DIFF3 21 VDD 33 GND 20 9 10 11 12 13 14 15 16 Notes: 1. Internal 100 kohm pull-up. 2. Internal 100 kohm pull-down. DIFF0 30 SCLK 31 CKPWRGD_PDB1 32 VDD VDD Description SDATA Wireless access point Routers DIFF2 VDD DIFF2 Network attached storage Multi-function printer XOUT VDD XIN Pin Assignments Applications DIFF1 OE01 DIFF1 I2C support with readback capabilities Triangular spread spectrum profile for maximum electromagnetic interference (EMI) reduction Industrial temperature: –40 to 85 oC 3.3 V Power supply 32-pin QFN package DIFF0 25 MHz crystal input or clock input OE11 PCI-Express Gen 1, Gen 2, & Gen 3 compliant Low power push-pull type differential output buffers Integrated resistors on differential clocks Dedicated output enable pin for each clock Hardware selectable spread control Six PCI-Express clocks DIFF0 DIFF4 DIFF3 Patents pending XIN/CLKIN DIFF1 XOUT PLL1 (SSC) Divider DIFF2 DIFF3 DIFF4 SCLK SDATA CKPWRGD/PDB OE [5:0] DIFF5 Control & Memory Control RAM SSON Preliminary Rev. 0.1 12/11 Copyright © 2011 by Silicon Laboratories Si52146 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Si52146 2 Preliminary Rev. 0.1 Si52146 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1. Crystal Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2. CKPWRGD_PDB (Power down) Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.3. PDB (Power down) Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.4. PDB Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.5. OE Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.6. OE Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.7. OE Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.8. SSON Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.1. Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5. Pin Descriptions: 32-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Preliminary Rev. 0.1 3 Si52146 1. Electrical Specifications Table 1. DC Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit 3.3 V Operating Voltage VDD core 3.3 ±5% 3.135 3.3 3.465 V 3.3 V Input High Voltage VIH Control input pins 2.0 — VDD + 0.3 V 3.3 V Input Low Voltage VIL Control input pins VSS – 0.3 — 0.8 V Input High Voltage VIHI2C SDATA, SCLK 2.2 — — V Input Low Voltage VILI2C SDATA, SCLK — — 1.0 V Input High Leakage Current IIH Except internal pull-down resistors, 0 < VIN < VDD — — 5 A Input Low Leakage Current IIL Except internal pull-up resistors, 0 < VIN < VDD –5 — — A 3.3 V Output High Voltage (SE) VOH IOH = –1 mA 2.4 — — V 3.3 V Output Low Voltage (SE) VOL IOL = 1 mA — — 0.4 V High-impedance Output Current IOZ –10 — 10 A Input Pin Capacitance CIN 1.5 — 5 pF COUT — — 6 pF LIN — — 7 nH Power Down Current IDD_PD — — 1 mA Dynamic Supply Current IDD_3.3V — — 60 mA Output Pin Capacitance Pin Inductance 4 All outputs enabled. Differential clocks with 5” traces and 2 pF load. Preliminary Rev. 0.1 Si52146 Table 2. AC Electrical Specifications Parameter Symbol Condition Min Typ Max Unit LACC Measured at VDD/2 differential — — 250 ppm TDC Measured at VDD/2 47 — 53 % CLKIN Rise and Fall Times TR/TF Measured between 0.2 VDD and 0.8 VDD 0.5 — 4.0 V/ns CLKIN Cycle to Cycle Jitter TCCJ Measured at VDD/2 — — 250 ps CLKIN Long Term Jitter TLTJ Measured at VDD/2 — — 350 ps Input High Voltage VIH XIN/CLKIN pin 2 — VDD+0.3 V Input Low Voltage VIL XIN/CLKIN pin — — 0.8 V Input High Current IIH XIN/CLKIN pin, VIN = VDD — — 35 uA Input Low Current IIL XIN/CLKIN pin, 0 < VIN <0.8 –35 — — uA TDC Measured at 0 V differential 45 — 55 % Any DIFF Clock Skew from the TSKEW(win Earliest Bank to the Latest dow) Bank Measured at 0 V differential — — 50 ps DIFF Cycle to Cycle Jitter TCCJ Measured at 0 V differential — 35 50 ps Output PCIe Gen1 REFCLK Phase Jitter RMSGEN1 Includes PLL BW 1.5–22 MHz, ζ = 0.54, Td=10 ns, Ftrk=1.5 MHz with BER = 1E-12 0 40 108 ps Output PCIe Gen2 REFCLK Phase Jitter RMSGEN2 Includes PLL BW 8–16 MHz, Jitter Peaking = 3 dB, ζ = 0.54, Td=12 ns), Low Band, F < 1.5 MHz 0 2 3.0 ps Output PCIe Gen2 REFCLK Phase Jitter RMSGEN2 Includes PLL BW 8–16 MHz, Jitter Peaking = 3 dB, ζ = 0.54, Td=12 ns), High Band, 1.5 MHz < F < Nyquist 0 2 3.1 ps Output Phase Jitter Impact— PCIe Gen3 RMSGEN3 Includes PLL BW 2–4 MHz, CDR = 10 MHz) 0 0.5 1.0 ps DIFF Long Term Accuracy LACC Measured at 0 V differential — — 100 ppm DIFF Rising/Falling Slew Rate TR/TF Measured differentially from ±150 mV 1 — 8 V/ns Voltage High VHIGH — — 1.15 V Voltage Low VLOW –0.3 — — V VOX 300 — 550 mV Clock Stabilization from Power-up TSTABLE — — 1.8 ms Stopclock Set-up Time TSS 10.0 — — ns Crystal Long-term Accuracy Clock Input CLKIN Duty Cycle DIFF at 0.7 V DIFF Duty Cycle Crossing Point Voltage at 0.7 V Swing Enable/Disable and Setup Preliminary Rev. 0.1 5 Si52146 Table 3. Absolute Maximum Conditions Parameter Symbol Condition Min Typ Max Unit VDD_3.3V Functional — — 4.6 V Input Voltage VIN Relative to VSS –0.5 — 4.6 VDC Temperature, Storage TS Non-functional –65 — 150 °C Temperature, Operating Ambient TA Functional –40 — 85 °C Temperature, Junction TJ Functional — — 150 °C Dissipation, Junction to Case ØJC JEDEC (JESD 51) — — 17 °C/W Dissipation, Junction to Ambient ØJA JEDEC (JESD 51) — — 35 °C/W ESDHBM JEDEC (JESD 22-A114) 2000 — — V UL-94 UL (Class) V–0 MSL JEDEC (J-STD-020) 2 Main Supply Voltage ESD Protection (Human Body Model) Flammability Rating Moisture Sensitivity Level Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required. 6 Preliminary Rev. 0.1 Si52146 2. Functional Description 2.1. Crystal Recommendations The clock device requires a parallel resonance crystal. Substituting a series resonance crystal causes the clock device to operate at the wrong frequency and violates the ppm specification. For most applications there is a 300 ppm frequency shift between series and parallel crystals due to incorrect loading. Table 4. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap 25 MHz AT Parallel 12–15 pF Shunt Cap (max) Motional (max) Tolerance (max) Stability (max) Aging (max) 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm 2.1.1. Crystal Loading Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, use the total capacitance the crystal sees to calculate the appropriate capacitive loading (CL). Figure 1 shows a typical crystal configuration using the two trim capacitors. It is important that the trim capacitors are in series with the crystal. It is not true that load capacitors are in parallel with the crystal and are approximately equal to the load capacitance of the crystal. Figure 1. Crystal Capacitive Clarification 2.1.2. Calculating Load Capacitors In addition to the standard external trim capacitors, consider the trace capacitance and pin capacitance to calculate the crystal loading correctly. Again, the capacitance on each side is in series with the crystal. The total capacitance on both side is twice the specified crystal load capacitance (CL). Trim capacitors are calculated to provide equal capacitive loading on both sides. Figure 2. Crystal Loading Example Preliminary Rev. 0.1 7 Si52146 Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 x CL – (Cs + Ci) Total Capacitance (as seen by the crystal) CLe = 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 ) CL: Crystal load capacitance Actual loading seen by crystal using standard value trim capacitors Ce: External trim capacitors Cs: Stray capacitance (terraced) Ci : Internal capacitance (lead frame, bond wires, etc.) CLe: 2.2. CKPWRGD_PDB (Power down) Clarification The CKPWRGD_PDB pin is a dual-function pin. During initial power up, the pin functions as CKPWRGD. Upon the first powerup if the CKPWRGD is low, the device outputs will be disabled, but the crystal oscillator and I2C logics are active. Once CKPWRGD has been sampled high by the clock chip, the pin assumes a PDB functionality. When the pin has assumed a PDB functionality and the pin is pull low, the device will be placed in standby mode. 2.3. PDB (Power down) Assertion The PDB pin is an asynchronous active low input used to disable all clocks in a glitch free manner. All outputs will be driven low in power down mode. In power down mode, all outputs, the crystal oscillator and the I2C logic are disabled. 2.4. PDB Deassertion When a valid rising edge on CKPWRGD/PDB pin is applied, all outputs are enabled in a glitch free manner within two to six output clock cycle. 2.5. OE Clarification The OE pins are active high inputs used to enable and disable the output clocks. To enable the output clock, the OE pin needs to be logic high and the I2C output enable bit needs to be logic high. There are two methods to disable the output clocks: the OE is pulled to a logic low, or the I2C enable bit is set to a logic low. The OE pins is required to be driven at all time and even though it has an internally 100 k resistor. 2.6. OE Assertion The OE signals are active high input used for synchronous stopping and starting the DIFF output clocks respectively while the rest of the clock generator continues to function. The assertion of the OE signal by making it logic high causes stopped respective DIFF output to resume normal operation. No short or stretched clock pulses are produced when the clock resumes. The maximum latency from the assertion to active outputs is no more than two to six output clock cycles. 2.7. OE Deassertion When the OE pin is deasserted by making its logic low, the corresponding DIFF output is stopped cleanly, and the final output state is driven low. 2.8. SSON Clarification SSON is an active input used to enable –0.5% spread on all DIFF outputs. When sampled high, –0.5% spread is enabled on all DIFF outputs. When sampled low, the DIFF output frequencies are non-spread. 8 Preliminary Rev. 0.1 Si52146 3. Test and Measurement Setup This diagram shows the test load configuration for the differential clock signals. M e a s u re m e n t P o in t L1 O U T+ 5 0 2 pF L1 = 5" O U T- M e a s u re m e n t P o in t L1 5 0 2 pF Figure 3. 0.7 V Differential Load Configuration Figure 4. Differential Output Signals (for AC Parameters Measurement) Preliminary Rev. 0.1 9 Si52146 VMIN = –0.30V VMIN = –0.30V Figure 5. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement) 10 Preliminary Rev. 0.1 Si52146 4. Control Registers 4.1. Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers are individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting at power-up. The use of this interface is optional. Clock device register changes are normally made at system initialization, if any are required. The interface cannot be used during system operation for power management functions. 4.2. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, access the bytes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any complete byte is transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code described in Table 1 on page 4. The block write and block read protocol is outlined in Table 5 while Table 6 outlines byte write and byte read protocol. The slave receiver address is 11010110 (D6h). Table 5. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 Description Start Slave address—7 bits Block Read Protocol Bit 1 8:2 Description Start Slave address—7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code—8 bits 18:11 19 Acknowledge from slave 19 Acknowledge from slave Byte Count—8 bits 20 Repeat start 27:20 28 36:29 37 45:38 Acknowledge from slave 27:21 Command Code–8 bits Slave address—7 bits Data byte 1–8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave Data byte 2–8 bits 46 Acknowledge from slave .... Data Byte/Slave Acknowledges .... Data Byte N–8 bits .... Acknowledge from slave .... Stop 37:30 38 46:39 47 55:48 Byte Count from slave—8 bits Acknowledge Data byte 1 from slave—8 bits Acknowledge Data byte 2 from slave—8 bits 56 Acknowledge .... Data bytes from slave/Acknowledge .... Data Byte N from slave—8 bits .... NOT Acknowledge .... Stop Preliminary Rev. 0.1 11 Si52146 Table 6. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 Description Start Slave address–7 bits Byte Read Protocol Bit 1 8:2 Start Slave address–7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 19 27:20 Command Code–8 bits 18:11 Command Code–8 bits Acknowledge from slave 19 Acknowledge from slave Data byte–8 bits 20 Repeated start 28 Acknowledge from slave 29 Stop 27:21 Slave address–7 bits 28 Read 29 Acknowledge from slave 37:30 12 Description Data from slave–8 bits 38 NOT Acknowledge 39 Stop Preliminary Rev. 0.1 Si52146 Control Register 0. Byte 0 Bit D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W D2 D1 D0 Name Type Reset settings = 00000000 Bit Name 7:0 Reserved Function Control Register 1. Byte 1 Bit D7 D6 D5 D3 DIFF1_OE DIFF0_OE Name Type D4 R/W R/W R/W R/W R/W R/W DIFF2_OE R/W R/W Reset settings = 00010101 Bit Name 7:5 Reserved 4 DIFF0_OE Function Output Enable for DIFF0. 0: Output disabled. 1: Output Enabled. 3 Reserved 2 DIFF1_OE Output Enable for DIFF1. 0: Output disabled. 1: Output enabled. 1 Reserved 0 DIFF2_OE Output Enable for DIFF2. 0: Output disabled. 1: Output enabled. Preliminary Rev. 0.1 13 Si52146 Control Register 2. Byte 2 Bit D7 D6 D5 Name DIFF3_OE DIFF4_OE DIFF5_OE Type R/W R/W R/W D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W D2 D1 D0 Reset settings = 11100000 Bit Name Function 7 DIFF3_OE Output Enable for DIFF3. 0: Output disabled. 1: Output enabled. 6 DIFF4_OE Output Enable for DIFF4. 0: Output disabled. 1: Output enabled. 5 DIFF5_OE Output Enable for DIFF5. 0: Output disabled. 1: Output enabled. 4:0 Reserved Control Register 3. Byte 3 Bit D7 D6 D4 D3 Rev Code[3:0] Name Type D5 R/W R/W R/W Vendor ID[3:0] R/W R/W Reset settings = 00001000 14 Bit Name Function 7:4 Rev Code[3:0] Program Revision Code. 3:0 Vendor ID[3:0] Vendor Identification Code. Preliminary Rev. 0.1 R/W R/W R/W Si52146 Control Register 4. Byte 4 Bit D7 D6 D5 D4 D2 D1 D0 R/W R/W R/W R/W BC[7:0] Name Type D3 R/W R/W R/W R/W Reset settings = 00000110 Bit Name 7:0 BC[7:0] Function Byte Count Register. Control Register 5. Byte 5 Bit D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W Name DIFF_Amp_Sel DIFF_Amp_Cntl[2] DIFF_Amp_Cntl[1] DIFF_Amp_Cntl[0] Type R/W R/W R/W R/W Reset settings = 11011000 Bit Name 7 DIFF_Amp_Sel Function Amplitude Control for DIFF Differential Outputs. 0: Differential outputs with Default amplitude. 1: Differential outputs amplitude is set by Byte 5[6:4]. 6 DIFF_Amp_Cntl[2] 5 DIFF_Amp_Cntl[1] 4 DIFF_Amp_Cntl[0] 3:0 Reserved DIFF Differential Outputs Amplitude Adjustment. 000: 300 mV 001: 400 mV 010: 500 mV 100: 700 mV 101: 800 mV 110: 900 mV Preliminary Rev. 0.1 011: 600 mV 111: 1000 mV 15 Si52146 SDATA SCLK 29 CKPWRGD_PDB1 30 VDD 31 XOUT OE01 32 XIN OE11 5. Pin Descriptions: 32-Pin QFN 28 27 26 25 VDD 1 24 VDD OE21 2 23 DIFF5 SSON 2 3 22 DIFF5 OE31 4 OE41 5 OE51 6 19 DIFF4 NC 7 18 VDD 8 17 DIFF3 21 VDD 33 GND 9 10 11 12 13 14 15 16 DIFF0 DIFF0 DIFF1 DIFF1 VDD DIFF2 DIFF2 VDD 20 Notes: 1. Internal 100 kohm pull-up. 2. Internal 100 kohm pull-down. DIFF4 DIFF3 Table 7. Si52146 32-Pin QFN Descriptions Pin # Name 1 VDD PWR 3.3 V power supply 2 OE2 I,PU 3.3 V input to disable DIFF2 (internal 100 k pull-up). Refer to Table 1 on page 4 for OE specifications. 3 SSON I, PD 3.3 V-tolerant input for enabling –0.5% spread on DIFF clocks (internal 100 k pull-down) 4 OE3 I,PU 3.3 V input to disable DIFF3 (internal 100 k pull-up). Refer to Table 1 on page 4 for OE specifications. 5 OE4 I,PU 3.3 V input to disable DIFF4 (internal 100 k pull-up). Refer to Table 1 on page 4 for OE specifications. 6 OE5 I,PU 3.3 V input to disable DIFF5 (internal 100 k pull-up). Refer to Table 1 on page 4 for OE specifications. 7 NC NC No connect 8 VDD 9 DIFF0 O, DIF 0.7 V, 100 MHz differential clock 10 DIFF0 O, DIF 0.7 V, 100 MHz differential clock 11 DIFF1 O, DIF 0.7 V, 100 MHz differential clock 16 Type Description PWR 3.3 V power supply Preliminary Rev. 0.1 Si52146 Table 7. Si52146 32-Pin QFN Descriptions Pin # Name Type Description 12 DIFF1 13 VDD 14 DIFF2 O, DIF 0.7 V, 100 MHz differential clock 15 DIFF2 O, DIF 0.7 V, 100 MHz differential clock 16 VDD 17 DIFF3 O, DIF 0.7 V, 100 MHz differential clock 18 DIFF3 O, DIF 0.7 V, 100 MHz differential clock 19 DIFF4 O, DIF 0.7 V, 100 MHz differential clock 20 DIFF4 O, DIF 0.7 V, 100 MHz differential clock 21 VDD 22 DIFF5 O, DIF 0.7 V, 100 MHz differential clock 23 DIFF5 O, DIF 0.7 V, 100 MHz differential clock 24 VDD 25 SCLK I 26 SDATA I/O 27 CKPWRGD_PDB I, PU 28 VDD 29 XOUT O 25.00 MHz crystal output, Float XOUT if using only CLKIN (clock input) 30 XIN/CLKIN I 25.00 MHz crystal input or 3.3 V, 25 MHz clock input 31 OE0 I,PU 3.3 V input to disable DIFF0 (internal 100 k pull-up). Refer to Table 1 on page 4 for OE specifications. 32 OE1 I,PU 3.3 V input to disable DIFF1 (internal 100 k pull-up). Refer to Table 1 on page 4 for OE specifications. 33 GND GND Ground for bottom pad of the IC. O, DIF 0.7 V, 100 MHz differential clock PWR 3.3 V power supply PWR 3.3 V power supply PWR 3.3 V power supply PWR 3.3 V power supply SMBus compatible SCLOCK SMBus compatible SDATA 3.3 V CMOS input. A real-time active low input for asserting power down (PDB) and disabling all outputs (internal 100 k pull-up). PWR 3.3 V power supply Preliminary Rev. 0.1 17 Si52146 6. Ordering Guide Part Number Package Type Temperature Si52146-A01AGM 32-pin QFN Industrial, –40 to 85 C Si52146-A01AGMR 32-pin QFN—Tape and Reel Industrial, –40 to 85 C Lead-free 18 Preliminary Rev. 0.1 Si52146 7. Package Outline Figure 6 illustrates the package details for the Si52146. Table 8 lists the values for the dimensions shown in the illustration. Figure 6. 32-Pin Quad Flat No Lead (QFN) Package Table 8. Package Diagram Dimensions Symbol A A1 A3 b D D2 e E E2 L Min 0.70 0.00 0.175 0.20 4.90 3.15 4.90 3.15 0.30 Millimeters Nom 0.75 0.02 0.20 0.25 5.00 3.20 0.50 BSC 5.00 3.20 0.40 Max 0.80 0.05 0.225 0.30 5.10 3.25 5.10 3.25 0.50 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 4. Coplanarity less than 0.08 mm. 5. Terminal #1 identifier and terminal numbering convention conform to JESD 95-1 SPP-012. Preliminary Rev. 0.1 19 Si52146 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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