NSC LP3936SLX

LP3936
Lighting Management System for Six White LEDs and
One RGB or FLASH LED
General Description
Features
LP3936 is a complete lighting management system designed for portable wireless applications. It contains a boost
DC/DC converter, 4 white LED drivers to drive the main LCD
panel backlight, 2 white LED drivers for sub-LCD panel and
1 set of RGB LED drivers.
Both WLED groups have 8-bit programmable constant current drivers that are separately adjustable and matched to
1% (typ.). For efficient backlighting the backlight intensity
can be adjusted using the 8-bit ADC with ambient light
detection circuit.
n High Efficiency 250 mA Magnetic Boost DC-DC
Converter with Programmable Output Voltage
n PWM controlled RGB LED drivers with programmable
color, brightness, turn on/off slopes and blinking
n FLASH function with 3 drivers, each up to 120 mA
current
n 4 constant current White LED drivers with
programmable 8-bit adjustment (0 … 25 mA/LED)
n 2 constant current White LED drivers with
programmable 8-bit adjustment (0 … 25 mA/LED)
n 8-bit ADC for ambient light sensor with averaging
n Combined MicroWire/SPI and I2C compatible serial
interface
n Low current Standby mode (software controlled)
n Low voltage digital interface down to 1.8V
n Space efficient 32-pin thin CSP laminate package
The RGB LED drivers are PWM-driven with programmable
color, intensity and blinking patterns. In addition, they feature
a FLASH function to support picture taking with cameraenabled cellular phones.
An efficient magnetic boost converter provides the required
bias operating from a single Li-Ion battery. The DC/DC converter output voltage is user programmable for adapting to
different LED types and for efficiency optimization. All functions are software controllable through an I2C and
MicroWire/SPI compatible interface and 16 internal registers.
Applications
n Cellular Phones
n PDAs
Typical Application
20081401
© 2004 National Semiconductor Corporation
DS200814
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LP3936 Lighting Management System for Six White LEDs and One RGB or FLASH LED
June 2004
LP3936
Connection Diagrams and Package Mark Information
32-Lead Thin CSP Package, 4.5 x 5.5 x 0.8 mm, 0.5 mm pitch
See NS Package Number SLD32A
20081403
20081402
Bottom View
Top View
20081404
Note: The actual physical placement of the package marking will vary from part to part. The package marking “XY” designates the date code. “UZ” and “TT” are NSC
internal codes for die manufacturing and assembly traceability. Both will vary considerably.
Package Mark — Top View
Ordering Information
Order Number
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Package Marking
Supplied As
LP3936SL
LP3936SL
1000 units, Tape-and-Reel
LP3936SLX
LP3936SL
2500 units, Tape-and-Reel
2
LP3936
Pin Description
Pin
Name
Type
1
GND_BOOST
Ground
2
FB
Input
3
VDD2
Power
Description
Power Switch Ground
Boost Converter Feedback
Supply Voltage for Internal Digital Circuits
4
GND2
Ground
5
WLED1
LED Output
Open Drain, White LED1 Output
Ground Return for VDD2 (Internal Digital)
6
WLED2
LED Output
Open Drain, White LED2 Output
7
WLED3
LED Output
Open Drain, White LED3 Output
8
WLED4
LED Output
Open Drain, White LED4 Output
9
GND_WLED
Ground
10
WLED5
LED Output
Open Drain, White LED5 Output
11
WLED6
LED Output
Open Drain, White LED6 Output
12
VDDA
Output
Internal LDO Output, 2.8V
13
GND1
Ground
Ground Return for VDD1 (Internal Analog)
14
VDD1
Power
Supply Voltage for Internal Analog Circuits
15
AIN
Input
16
AREF
Output
Reference Voltage for Ambient Light Sensor, 1.23V
17
GND_T
Ground
Ground
Internal Reference Bypass Capacitor
4+2 White LED Driver Ground
Ambient Light Sensor Input
18
VREF
Output
19
RT
Input
20
MW_SEL
Logic Input
MicroWire — I2C select (MW_SEL=1 in MicroWire Mode)
21
NRST
Logic Input
Low Active Reset Input
22
CS
Logic
Input/Output
MicroWire Chip-Select (in) / I2C SDA (in/out)
23
DO
Logic Output
MicroWire Data Output
24
DI
Logic Input
MicroWire Data Input
25
SCL
Logic Input
MicroWire Clock / I2C SCL Input
26
RGB_EN
Logic Input
LED Control for On/Off or PWM Dimming
27
VDD_IO
Power
28
ROUT
LED Output
Open Drain Output, Red LED
29
GOUT
LED Output
Open Drain Output, Green LED
30
BOUT
LED Output
Open Drain Output, Blue LED
31
GND_RGB
Ground
Ground for RGB Drivers
32
OUT
Output
Open Drain, Boost Converter Power Switch
Oscillator Resistor
Supply Voltage for Logic IO signals
3
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LP3936
Absolute Maximum Ratings
Maximum Lead Temperature
(Notes 1,
260˚C
2)
(Reflow soldering, 3 times) (Note 4)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Rating (Note 5)
VDD1, VDD2, VDD_IO, V(OUT, FB)
Human Body Model:
2 kV
Machine Model:
200V
-0.3V to 6.0V
Voltage on Logic Pins
-0.3V to VDD_IO +
0.3V, with 6.0V max
Voltage on LED Output Pins
-0.3V to V(FB) +
0.3V, with 6.0V max
Voltage on All Other Pins
-0.3V to VDD1,2 +
0.3V, with 6.0V max
I (ROUT, GOUT, BOUT)
Operating Ratings (Notes 1, 2)
VDD1, VDD2
150 mA
I (VREF)
10 µA
Continuous Power Dissipation
(Note 3)
1.8V – VDD1,2
Recommended Load Current
0 mA to 250 mA
Junction Temperature (TJ) Range
−40˚C to +125˚C
Ambient Temperature (TA) Range
(Note 6)
−40˚C to +85˚C
Thermal Properties
Internally Limited
Junction Temperature (TJ-MAX)
Storage Temperature Range
3.0V to 6.0V
VDD_IO
125˚C
Junction-to-Ambient Thermal Resistance (θJA),
−65˚C to +150˚C
SLD32A Package (Note 7)
72˚C/W
Electrical Characteristics (Notes 2, 8)
Limits in standard typeface are for TJ = 25˚C. Limits in boldface type apply over the operating ambient temperature range
(−40˚C ≤ TA ≤ +85˚C). Unless otherwise noted, specifications apply to the Section Block Diagram with: VDD1 = VDD2 = VDD_IO
= 3.6V, CVDD1, CVDD2, CVDDIO = 1 µF, CIN, COUT = 10 µF, CVDDA = 1 µF, CVREF = 0.1 µF, LBOOST = 10 µH (Note 9).
Symbol
Parameter
Min
Typ
Max
3.0
3.6
6.0
V
NSTBY = L (register)
CS, SCL, DI, NRST = H
VDD1, VDD2 = 3.6V
1
7
µA
No-Load Supply Current
(VDD1 and VDD2 current, boost off)
NSTBY = H (reg.)
EN_BOOST = L (reg.)
SCL, CS, DI, NRST = H
170
300
µA
Full Load Supply Current
(VDD1 and VDD2 current, boost on)
NSTBY = H (register)
NRST, CS, SCL, DI = H
RGB_EN = L
WLED1 … 6 = L
EN_AMBADC = L
1
mA
VDD_IO Standby Supply Current
NSTBY = L (register)
CS, SCL, DI, NRST = H
1
µA
VDD_IO Operating Supply Current
1 MHz Clock Frequency
CL = 50 pF at DO pin
20
µA
VREF
Reference Voltage (Note 10)
IREF ≤ 1 nA,
Test Purposes Only
1.205
−2
1.23
1.255
+2
V
%
VDDA
LDO Output Voltage
IVDDA < 1 µA
2.688
–4
2.8
2.912
+4
%V
VDD1,2
Supply Voltage
IDD
Standby Supply Current
(VDD1 and VDD2 current)
IDD_IO
Condition
Units
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of
the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pins (GND1, GND2, GND_T, GND_BOOST, GND_WLED, GND_RGB).
Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 160˚C (typ.) and disengages at TJ =
140˚C (typ.).
Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note 1125: Laminate CSP/FBGA
Package (AN-1125).
Note 5: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged
directly into each pin. MIL-STD-883 3015.7
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4
(Continued)
Note 6: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125˚C), the maximum power
dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the
following equation: TA-MAX = TJ-MAX-OP − (θJA x PD-MAX).
Note 7: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists,
special care must be paid to thermal dissipation issues in board design.
Note 8: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 9: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
Note 10: VREF pin (Bandgap reference output) is for internal use only. A capacitor should always be placed between VREF and GND1.
Block Diagram
20081405
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LP3936
Electrical Characteristics (Notes 2, 8)
LP3936
Modes of Operation
RESET:
In the RESET mode all the internal registers are reset to the default values. Boost output register is set to
4.55V (register 0Dh = 07h), ext_pwm is enabled for color outputs (register 2Bh = 1Ch), EN_BOOST bit is
high (register 0Bh bit 5) and all other registers are set to 00h. Reset is entered always if input NRST is LOW
or internal Power On Reset is active.
STANDBY:
The STANDBY mode is entered if the register bit NSTBY is LOW and Reset is not active. This is the low
power consumption mode, when all circuit functions are disabled. Registers can be written in this mode and
the control bits are effective immediately after start up.
STARTUP:
INTERNAL STARTUP SEQUENCE powers up all the needed internal blocks (VREF, Bias, Oscillator, etc.).
To ensure the correct oscillator initialization, a 10 ms delay is generated by the internal state-machine.
Thermal shutdown (THSD) disables the chip operation and Startup mode is entered until no thermal
shutdown event is present.
BOOST STARTUP: Soft start for boost output is generated in the BOOST STARTUP mode. In this mode the boost output is
raised in PFM mode during the 10 ms delay generated by the state-machine. The Boost startup is entered
from Internal Startup Sequence if EN_BOOST is HIGH or from Normal mode when EN_BOOST is written
HIGH.
NORMAL:
During NORMAL mode the user controls the chip using the Control Registers. The registers can be written
in any sequence and any number of bits can be altered in a register in one write.
20081406
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LP3936
Logic Interface Characteristics
(1.8V ≤ VDD_IO ≤ VDD1,2) (Note 11)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LOGIC INPUTS DI, SCL, NRST, RGB_EN, CS, MW_SEL
VIL
Input Low Level
VIH
Input High Level
II
Logic Input Current
fSCL
Clock Frequency
0.5
V
VDD_IO − 0.5
V
−1.0
I2C Mode
MicroWire Mode
1.0
µA
400
kHz
8
MHz
0.6
V
1.0
µA
LOGIC OUTPUTS DO, CS
VOL
Output Low Level
IDO,
VOH
Output High Level
IDO = − 3 mA
IL
Output Leakage Current VDO = 2.8V
CS
= 3 mA
0.3
VDD_IO − 0.6
VDD_IO − 0.3
V
Note 11: In I2C mode operating ratings are limited to 3.0V ≤ VDD1,2 ≤ 4.5V and –20˚C ≤ TA ≤ +85˚C.
Control Interface
The LP3936 supports two different interfaces modes:
1) MicroWire/SPI interface
2) I2C compatible interface
is selected. The following table shows the selections for both
interface modes.
User can define the interface by MW_SEL pin. The pin
configuration will also change depending on which interface
MW_SEL
Interface
Pin Configuration
1
MicroWire/SPI
SCL
DI
DO
CS
(clock)
(data in)
(data out)
(chip select)
0
I2C Compatible
SCL
CS = SDA
(clock)
(data in/out)
Comment
Use pull up resistor for SCL
Use pull up resistor for SDA
The Address and Data are transmitted MSB first. The Chip
Select signal CS must be low during the Cycle transmission.
CS resets the interface when high and it has to be taken high
between successive Cycles. Data is clocked in on the rising
edge of the SCL clock signal, while data is clocked out on the
falling edge of SCL.
The MicroWire interface mode can also support SPI interface. The difference with normal SPI interface is that in
LP3936 the Read operation from a new address needs two
read cycles. If repetitive reads are made from the same
address, a correct value is obtained on every read cycle.
MicroWire/SPI Interface
The Microwire transmission consists of 16-bit Write and
Read Cycles. One cycle consists of 7 Address bits, 1 Read/
Write (R/W) bit and 8 Data bits. Read is done in two cycles:
address is provided in the first cycle and the data is sent out
on the next cycle. R/W bit high state defines a Write Cycle
and low defines a Read Cycle. DO output is normally in
high-impedance state and it is active only during Write and
Read Cycles. A pull-up or pull-down resistor may be needed
in DO line if a floating logic signal can cause unintended
current consumption in other circuits where DO is connected.
MicroWire Write Cycle
20081407
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LP3936
MicroWire/SPI Interface
(Continued)
MicroWire Read Cycle 1
20081408
MicroWire Read Cycle 2
20081409
MicroWire Timing Diagram
20081410
MicroWire Timing Parameters
VDD1,2 = 3.0V – 6V, VDD_IO = 1.8V – VDD1,2
Symbol
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Limit
Parameter
Min
Max
Units
1
Cycle Time
120
2
Enable Lead Time
60
ns
3
Enable Lag Time
60
ns
4
Clock Low Time
60
ns
5
Clock High Time
60
ns
6
Data Setup Time
0
ns
7
Data Hold Time
10
ns
8
Data Access Time
35
ns
9
Disable Time
30
ns
8
ns
Symbol
LP3936
MicroWire Timing Parameters
(Continued)
Limit
Parameter
Min
Max
55
Units
10
Output Data Valid
11
Output Data Hold Time
15
ns
ns
12
CS Inactive Time
10
ns
Note: Data guaranteed by design.
I2C Compatible Interface
I2C SIGNALS
In I2C mode the LP3936 pin SCL is used for the I2C clock and the pin CS is used for the I2C data signal SDA. Both these signals
need a pull-up resistor according to I2C specification. Unused pin DO can be left unconnected and pin DI must be connected to
VDD_IO or GND.
I2C DATA VALIDITY
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can
only be changed when CLK is LOW.
20081411
I2C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH
while SCL is HIGH. The I2C master always generates START and STOP bits. The I2C bus is considered to be busy after START
condition and free after STOP condition. During data transmission, I2C master can generate repeated START conditions. First
START and repeated START conditions are equivalent, function-wise.
20081412
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data
has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter
releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9th clock
pulse, signifying an acknowledge. A receiver which has been addressed must generate an acknowledge after each byte has been
received.
After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an eighth bit which
is a data direction bit (R/W). The LP3936 address is 36h. For the eighth bit, a “0” indicates a WRITE and a “1” indicates a READ.
The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register.
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LP3936
I2C Compatible Interface
(Continued)
I2C Chip Address
20081413
I2C Write Cycle
20081414
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = chip address, 36h for LP3936
When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle
waveform.
I2C Read Cycle
20081415
I2C Timing Diagram
20081432
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10
LP3936
I2C Compatible Interface
(Continued)
I2C Timing Parameters
VDD1,
2
= 3.0V to 4.5V, VDD_IO = 1.8V to VDD1,
Symbol
2
Limits
Parameter
Min
Units
Max
1
Hold Time (repeated) START Condition
0.6
µs
2
Clock Low Time
1.3
µs
3
Clock High Time
600
ns
4
Setup Time for a Repeated START Condition
600
ns
5
Data Hold Time
300
6
Data Setup Time
100
7
Rise Time of SDA and SCL
20 + 0.1Cb
300
8
Fall Time of SDA and SCL
15 + 0.1Cb
300
9
Set-Up Time for STOP Condition
600
ns
10
Bus Free Time between a STOP and a START Condition
1.3
µs
Cb
Capacitive Load for Each Bus Line
10
900
ns
ns
ns
ns
200
pF
Note: Data guaranteed by design.
A/D Converter for Ambient Light Measurement
Electrical Characteristics
Symbol
Parameter
VIN RANGE
Input Voltage
DNL
Differential Non-Linearity
GE
Gain Error
Conditions
Min
AD Output: 00h
Typ
Max
1.23
AD Output: FFh
V
2.46
–1.5
±1
−5
Units
V
+1.5
LSB
+5
LSB
PSS
Power Supply Sensitivity
3.1V ≤ VDD ≤ 4.2V
± 1/2
f(conv)
Conversion Rate
Without Averaging
217
Hz
With Averaging
(64 samples)
3.4
Hz
100
ms
tSTARTUP
Startup Time
LSB
IAIN
Input Current
1.23 < AIN < 2.6V
± 0.1
µA
IAREF
Maximum Output Current
AREF Output Current Sink
200
µA
RAREF
AREF Output Resistance
110
Ω
ADC output AIN[7:0] can be read from address 0CH after startup time. Overflow bit can be read from bit D7 in address 0BH. The
overflow bit indicates that input voltage exceeds the input voltage range of the ADC. The ADC output value in this case is FFH.
When averaging is on, the overflow is high, if any of the 64 conversion results in the averaging period overflows. Thus the
averaged result may be considerably below maximum and the overflow can still be high, if the input signal is noisy.
Examples for optical sensor are photodiode SHF2400 and phototransistor SFH3410 from Osram or BSC 3216 G1 optical sensor
from TDK.
ADC can be used for temperature measurement with a thermistor. It enables temperature compensated LED driving.
If ADC is not used, it should be disabled by writing en_ambadc bit low. AIN and AREF pins can be left unconnected
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LP3936
A/D Converter for Ambient Light Measurement
(Continued)
20081416
Magnetic Boost DC/DC Converter
The LP3936 Boost DC/DC Converter generates a 4.1V–5.3V supply voltage for the LEDs from single Li-Ion battery (3V … 4.5V).
The output voltage is controlled with an 8-bit register in 9 steps. The converter is a magnetic switching PFM/PWM mode DC/DC
converter with a current limit. The converter has a 1 MHz switching frequency when timing resistor RT is 82 kΩ.
The topology of the magnetic boost converter is called CPM control, current programmed mode, where the inductor current is
measured and controlled with the feedback. The user can program the output voltage of the boost converter. The control changes
the resistor divider in the feedback loop.
The following figure shows the boost topology with the protection circuitry. Three different protection schemes are implemented:
1) Over voltage protection, limits the maximum output voltage
a. Keeps the output below breakdown voltage.
b. Prevents boost operation if battery voltage is much higher than desired output.
2) Over current protection, limits the maximum inductor current
a. Voltage over switching NMOS is monitored; too high voltages turn the switch off.
3) Duty cycle limiting, done with digital control.
20081417
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12
LP3936
Boost Output Voltage Control
User can control the boost output voltage by boost output 8-bit register.
Boost[7:0]
Register 0Dh
Binary
Hex
BOOST Output
Voltage
(typical)
0000 0000
00
4.10
0000 0001
01
4.25
0000 0011
03
4.40
0000 0111
07
4.55 Default
0000 1111
0F
4.70
0001 1111
1F
4.85
0011 1111
3F
5.00
0111 1111
7F
5.15
1111 1111
FF
5.30
Boost Output Voltage Control
20081418
Magnetic Boost DC/DC Converter Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
ILOAD
Load Current
3.0V ≤ VIN ≤ 4.5V
VOUT = 4.55V
0
250
mA
VOUT
Output Voltage Accuracy (FB Pin)
1 mA ≤ ILOAD ≤ 225 mA
3.0V ≤ VIN ≤ V (FB)−0.5V
VOUT = 4.55V
−5
+5
%
Output Voltage (FB Pin)
1 mA ≤ ILOAD ≤ 250 mA
3.0V < VIN < 4.55V +
V(SCHOTTKY)
4.55
V
1 mA ≤ ILOAD ≤ 250 mA
VIN > 4.55V + V(SCHOTTKY)
VIN–V(SCHOTTKY)
V
0.4
RDSON
Switch ON Resistance
VDD1,2 = 3.6V, ISW = 0.5A
fPWF
PWM Mode Switching Frequency
RT = 82 kΩ
Frequency Accuracy
RT = 82 kΩ
−6
±3
−10
tSTARTUP Startup Time
ICL_OUT
OUT Pin Current Limit
0.5
1
+6
+10
25
VDD = 3.6V
600
400
750
Ω
MHz
%
ms
1050
1200
mA
PFM/PWM Mode
User can change the Boost converters mode between PWM (Pulse Width Modulation) and PFM (Pulse Frequency Modulation).
The startup is done on PFM mode and then the device runs on PWM mode (as a default). User can set PFM mode by turning
“pfm_mode” register bit HIGH. PFM is recommended to use with light loads and PWM with high loads.
Boost Standby Mode
User can set boost converter to STANDBY mode by writing register bit EN_BOOST low. This mode can be useful when driving
LEDs directly from battery voltage. This may be possible if LED forward voltage is low, battery voltage is high and LED current
is low.
When EN_BOOST is written high, the converter starts for 10 ms in PFM mode and then goes to PWM mode if PWM mode has
been selected (default).
Unused Boost Converter
If the boost converter is not used, it should be disabled by writing bit en_boost low. OUT pin should be connected to GND and
FB pin to the LED supply voltage.
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LP3936
Boost Converter Typical Performance Characteristics
VIN = 3.6V, VOUT = 4.55V if not
otherwise stated.
Boost Converter Efficiency
Boost Frequency vs RT Resistor
20081420
20081419
Battery Current vs Voltage
Battery Current vs Voltage
20081421
20081422
Boost Typical Waveforms at 100 mA Load
Boost Startup with No Load
20081424
20081423
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Boost Line Regulation
Boost Load Regulation, 50 mA–100 mA
20081426
20081425
(PWM brightness control)
• DUTY
(dimming slope)
• SLOPE
(direct enable control)
• ENABLE
The main blinking cycle is controlled with 2-bit CYCLE control (0.25 / 0.5 / 1.0 / 2.0s).
RGB LED Driver
The RGB driver has three outputs that can independently
drive one RGB LED or three LEDs of any kind. User has
control over the following parameters separately for each
LED:
• ON and OFF (start and stop time in blinking cycle)
20081427
RGB PWM Operating Principle
RGB_START is the master enable control for the whole RGB
function. The internal PWM and blinking control can be
disabled by setting the RGB_PWM control LOW. In this case
the individual enable controls can be used to switch outputs
on and off. RGB_EN input can be used for external hardware
PWM control. RGB_EN input can be used as direct on/off or
brightness (PWM) control. If RGB_EN input is not used, it
must be tied to VDD_IO. Recommended maximum frequency
of RGB LED external PWM control is 1 MHz.
In the normal PWM mode the R, G and B switches are
controlled in 3 phases (one phase per driver). During each
phase the peak current set by external resistor is driven
through the LED for the time defined by DUTY setting
(0 µs–50 µs). As a time averaged current this means
0%–33% of the peak current. The PWM period is 150 µs and
the pulse frequency is 6.67 kHz in normal mode.
20081428
Normal Mode PWM Waveforms at different duty
settings
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LP3936
Boost Converter Typical Performance Characteristics VIN = 3.6V, VOUT = 4.55V if not
otherwise stated. (Continued)
LP3936
RGB LED Driver
(Continued)
In the FLASH mode all the outputs are controlled in one
phase and the PWM period is 50 µs. The time averaged
FLASH mode current is three times the normal mode current
at the same DUTY value.
Blinking can be controlled separately for each output. On
and OFF times determine, when a LED turns on and off
within the blinking cycle. When both ON and OFF are 0, the
LED is on and doesn’t blink. If ON equals OFF but is not 0,
the LED is permanently off.
20081429
Example Blinking Waveforms
RGB Driver Electrical Characteristics
(ROUT, GOUT, BOUT outputs)
Symbol
Parameter
RDS-ON
ON Resistance
Conditions
ILEAKAGE
Off State Leakage Current
VFB = 5.3V
IMAX
Maximum Sink Current
(Note 12)
Min
Typ
Max
Units
2
4.5
Ω
0.04
1
µA
120
mA
TSMAX
Maximum Slope Period
Maximum Duty Setting
0.93
s
TSMIN
Minimum Slope Period
Maximum Duty Setting
31
ms
TSRES
Slope Resolution
Maximum Duty Setting
62
ms
TSTART/STOP
Start/Stop Resolution
Cycle 1s
1/16
s
Duty
Duty Step Size
TBLINK
Blinking Cycle Accuracy
DCYCF
Duty Cycle Range
EN_FLASH = 1
0
DCYC
Duty Cycle Range
EN_FLASH = 0
0
DRESF
Duty Resolution
EN_FLASH = 1 (4-bit)
6.27
DRES
Duty Resolution
EN_FLASH = 0 (4-bit)
2.09
%
FPWMF
PWM Frequency
EN_FLASH = 1
20
kHz
FPWM
PWM Frequency
EN_FLASH = 0
6.67
kHz
1/16
−6
±3
+6
%
94
%
31
%
%
Note 12: The total load current of the boost converter should be limited to 250 mA.
RGB LED PWM Control
(Note 13)
RDUTY[3:0]
GDUTY[3:0]
BDUTY[3:0]
DUTY sets the brightness of the LED by adjusting the duty cycle of the PWM driver. The minimum DUTY
cycle [0000] is 0% and the maximum [1111] in the Flash mode is A 94% and in the normal mode 31% of
the peak pulse current. The peak pulse current is determined by the external resistor, LED forward
voltage drop and the boost voltage.
RSLOPE[3:0]
GSLOPE[3:0]
BSLOPE[3:0]
SLOPE sets the turn-on and turn-off slopes. Fastest slope is set by [0000] and slowest by [1111]. SLOPE
changes the duty cycle at constant, programmable rate. For each slope setting the maximum slope time
appears at maximum DUTY setting. When DUTY is reduced, the slope time decreases proportionally. For
example, in case of maximum DUTY, the sloping time can be adjusted from 31 ms [0000] to 930 ms
[1111]. For 50% DUTY [1000] the sloping time is 17 ms [0000] to 496 ms [1111]. The blinking cycle has
no effect on SLOPE.
RON[6:0]
GON[6:0]
BON[6:0]
ON sets the beginning time of the turn-on slope. The on-time is relative to the selected blinking cycle
length. On-setting N (N = 0–127) sets the on-time to N/128 * cycle length.
ROFF[6:0]
GOFF[6:0]
BOFF[6:0]
OFF sets the beginning time of the turn-off slope. Off-time is relative to blinking cycle length in the same
way as on-time.
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16
(Note 13) (Continued)
If ON = 0, OFF = 0 and RGB_PWM = 1, then RGB outputs are continuously on (no blinking), DUTY
controls the brightness and SLOPE is ignored.
If ON and OFF are the same, but not 0, RGB outputs are turned off.
CYCLE[1:0]
CYCLE sets the blinking cycle: [00] for 0.25s, [01] for 0.5s, [10] for 1s and [11] for 2s. CYCLE setting is
common to all R, G and B drivers.
RSW
GSW
BSW
Enable for R switch
Enable for G switch
Enable for B switch
RGB_START
Master Switch:
RGB_START = 0 → RGB OFF
RGB_START = 1 → RGB ON, starts the new cycle from t = 0
RGB_PWM = 0 → RSW, GWS and BSW control directly the RGB outputs (on/off control only)
RGB_PWM = 1 → Normal PWM RGB functionality (duty, slope, on/off times, cycle)
RGB_PWM
EN_FLASH
EN_RED_PWM
EN_GREEN_PWM
EN_BLUE_PWM
Flash Mode enable control for RGB. In Flash mode (EN_FLASH = 1) RGB outputs are PWM controlled
simultaneously, not in 3-phase system as in the Normal Mode.
EN_X_PWM = 0 → External PWM control from RGB_EN pin is disabled
EN_X_PWM = 1 → External PWM control from RGB_EN pin is enabled
Internal PWM control (DUTY) can be used independently of external PWM control. External PWM has
the same effect on all enabled colors.
Note 13: Application Note AN-1293, “Driving RGB LEDs Using LP3936 Lighting Management System” contains a thorough description of the RGB driver
functionality including programming examples.
Main and sub display outputs have separate enable control
bits, EN_4LED and EN_2LED.
PWM control of WLED outputs for dimming or on/off control
is possible using RGB_EN pin together with
EN_4LED_PWM and EN_2LED_PWM enable control bits
from the user register. Recommended maximum frequency
of WLED external PWM control is 1 kHz.
WLED Drivers
White LED drivers drive each white LED with a regulated
constant current. The outputs are combined in two groups,
four outputs for the main display backlight and two outputs
for the sub display backlight. The current is controlled between 0 and 25.5 mA using the 8-bit current mode DAconverters. WLED outputs can be used to drive any kind of
LED.
20081430
17
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LP3936
RGB LED PWM Control
LP3936
WLED and CLED Driver Electrical Characteristics
Symbol
Parameter
Conditions
IRANGE
Sink Current Range
VFB = 4.55V, Control 00h–FFh
IMAX
Maximum Sink Current
(Note 14)
Min
Typ
Max
Units
27
mA
28
mA
0–25.5
24
25.5
22
mA
ILEAKAGE
Leakage Current
VFB = 5V
0.04
1
µA
IMATCH
Sink Current Matching
(Note 15)
ISINK = 13 mA, between
WLED1 … 4 or WLED5 … 6
1.0
4
%
Note 14: A minimum voltage, Dropout Voltage, is required on the WLED outputs for maintaining the LED current. The current reduction at lower voltages is shown
in the graph WLED Output Current vs. Voltage.
Note 15: Match % = 100% * (Max – Min)/Min
lighter loads, the low ESR ceramics offer a much lower VOUT
ripple than the higher ESR tantalums of the same value. At
the higher loads, the ceramics offer a slightly lower VOUT
ripple magnitude than the tantalums of the same value.
However, the dv/dt of the VOUT ripple with the ceramics is
much lower than the tantalums under all load conditions.
Capacitor voltage rating must be sufficient, 10V is recommended. It should be noted that with some capacitor types
the actual capacitance depends heavily on the capacitor DC
voltage bias.
WLED Current Adjustment
WLED[7:0]
WLED Current
(Typical)
Units
0000 0000
0
mA
0000 0001
0.1
mA
0000 0010
0.2
mA
0000 0011
0.3
mA
•
•
1111 1101
1111 1110
1111 1111
•
•
25.3
25.4
25.5
•
•
mA
mA
mA
INPUT CAPACITOR, CIN
The input capacitor CIN directly affects the magnitude of the
input ripple voltage and to a lesser degree the VOUT ripple. A
higher value CIN will give a lower VIN ripple. Capacitor voltage rating must be sufficient, 10V is recommended.
WLED Output Current vs Voltage
Temperatures −40˚C, +25˚C, +85˚C
OUTPUT DIODE, DOUT
A Schottky diode should be used for the output diode. To
maintain high efficiency the average current rating of the
schottky diode should be larger than the peak inductor current (1A). Schottky diodes with a low forward drop and fast
switching speeds are ideal for increasing efficiency in portable applications. Choose a reverse breakdown of the
schottky diode larger than the output voltage. Do not use
ordinary rectifier diodes, since slow switching speeds and
long recovery times cause the efficiency and the load regulation to suffer.
INDUCTOR, L
The high switching frequency enables the use of the small
surface mount inductor. A 10 µH shielded inductor is suggested. Values below 4.7 µH should not be used. The inductor should have a saturation current rating higher than the
peak current it will experience during circuit operation (A1A).
Less than 300 mΩ ESR is suggested for high efficiency.
Open core inductors cause flux linkage with circuit components and interfere with the normal operation of the circuit.
This should be avoided. For high efficiency, choose an inductor with a high frequency core material such as ferrite to
reduce the core losses. To minimize radiated noise, use a
toroid, pot core or shielded core inductor. The inductor
should be connected to the OUT pin as close to the IC as
possible. Examples of suitable inductors are TDK types
LLF4017T-100MR90C and VLF4012AT-100MR79 and Coilcraft type DO3314T-103 (unshielded).
20081431
Recommended External
Components
OUTPUT CAPACITOR, COUT
The output capacitor COUT directly affects the magnitude of
the output ripple voltage. In general, the higher the value of
COUT, the lower the output ripple magnitude. Multilayer ceramic capacitors with low ESR are the best choice. At the
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18
LP3936
Recommended External Components
(Continued)
List of Recommended External Components
Symbol
Value
Unit
CVDD1
VDD1 bypass capacitor
Symbol Explanation
1
µF
Ceramic, X7R
Type
CVDD2
VDD2 bypass capacitor
1
µF
Ceramic, X7R
COUT
Output capacitor from FB to GND
10
µF
Ceramic, X7R/Y5V
CIN
Input capacitor from Battery Voltage to GND
10
µF
Ceramic, X7R/Y5V
CVDDIO
VDDIO bypass capacitor
1
µF
Ceramic, X7R
CVDDA
Internal LDO output capacitor, between VDDA and GND
1
µF
Ceramic, X7R
RT
Oscillator Frequency Bias Resistor
82
kΩ
1% (Note 16)
RDO
DO output pull-up resistor
100
kΩ
CVREF
Reference Voltage Capacitor, between VREF and GND
100
nF
Ceramic, X7R
LBOOST
Boost converter inductor
10
µH
Shielded, Low ESR, ISAT A1A
DOUT
Rectifying Diode, VF @ Maxload
0.3
V
RGB
RGB LED
User Defined
(See Application Note AN-1293 for resistor size calculation)
RR, RG, RB Current Limit Resistors
LEDs
Schottky Diode
White LEDs
Note 16: Resistor RT tolerance change will change the timing accuracy of the RGB block. Also the boost converter switching frequency will be affected.
Control Registers
All user accessible control registers and register bits are shown in the following table.
ADDR
00H
SETUP
D7
D6
Control register rgb_pwm rgb_start
D5
D4
D3
D2
D1
D0
cycle[1]
cycle[0]
rsw
gsw
bsw
pfm_mode
ron[0]
01H
ron
ron[6]
ron[5]
ron[4]
ron[3]
ron[2]
ron[1]
02H
roff
roff[6]
roff[5]
roff[4]
roff[3]
roff[2]
roff[1]
roff[0]
03H
gon
gon[6]
gon[5]
gon[4]
gon[3]
gon[2]
gon[1]
gon[0]
04H
goff
goff[6]
goff[5]
goff[4]
goff[3]
goff[2]
goff[1]
goff[0]
05H
bon
bon[6]
bon[5]
bon[4]
bon[3]
bon[2]
bon[1]
bon[0]
06H
boff
boff[6]
boff[5]
boff[4]
boff[3]
boff[2]
boff[1]
boff[0]
rslope[2]
07H
rslope, rduty
rslope[3]
rslope[1]
rslope[0]
rduty[3]
rduty[2]
rduty[1]
rduty[0]
08H
gslope, gduty
gslope[3] gslope[2] gslope[1]
gslope[0]
gduty[3]
gduty[2]
gduty[1]
gduty[0]
09H
bslope, bduty
bslope[3] bslope[2] bslope[1]
0AH
wled current 1
wled1[7]
0BH
enables
0CH
Amb. Light data
0DH
bslope[0]
bduty[3]
bduty[2]
bduty[1]
bduty[0]]
wled1[6]
wled1[5]
wled1[4]
wled1[3]
wled1[2]
wled1[1]
wled1[0]
overflow
nstby
en_boost
en_flash
en_ambave
en_ambadc
en_4led
en_2led
ain[7]
ain[6]
ain[5]
ain[4]
ain[3]
ain[2]
ain[1]
ain[0]
boost output
boost[7]
boost[6]
boost[5]
boost[4]
boost[3]
boost[2]
boost[1]
boost[0]
2AH
wled current 2
wled2[7]
wled2[6]
wled2[5]
wled2[4]
wled2[3]
wled2[2]
wled2[1]
wled2[0]
2BH
ext pwm enable
en_redpwm en_greenpwm en_bluepwm en_4ledpwm en_2ledpwm
Default value of each register is 0000 0000 except the following
— boost output default is 0000 0111 = 07h (4.55V).
— enables default is x010 0000 = 20h (boost enabled)
— ext_pwm_enable default is 0001 1100 = 1Ch (RGB_EN control enabled for color outputs)
Register 0Ch all bits (ain[7:0]) and bit D7 in register 0Bh (overflow) are read only. All other bits are read-write.
19
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LP3936 Lighting Management System for Six White LEDs and One RGB or FLASH LED
Physical Dimensions
inches (millimeters) unless otherwise noted
32-Lead Thin CSP Package, 4.5 x 5.5 x 0.8 mm, 0.5 mm Pitch
NS Package Number SLD32A
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