High Power DP3T Switch with Logic Control CXG1215UR Description The CXG1215UR can be used in wireless communication systems, for example, dual-band CDMA handsets. This IC has on-chip logic for operation with 3 COMS control inputs. The Sony JPHEMT process is used for low insertion loss and on-chip logic circuit. (Applications: Antenna switch for cellular handsets, dual-band CDMA) Features Low insertion loss: 0.35dB@900MHz, 0.5dB@2GHz 3 CMOS compatible control line Package Small package size: 16-pin UQFN Structure GaAs JPHEMT MMIC Absolute Maximum Ratings (Ta = 25°C) Input power max (RF port) Pin 37 dBm Bias voltage VDD 7 V Control voltage Vctl 5 V Operating temperature Topr –35 to +85 °C Storage temperature Tstg –65 to +150 °C This IC is ESD sensitive device. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E06233B74 CXG1215UR 16 15 CRF GND GND GND RF2(2GHz) Block Diagram and Recommended Circuit 14 13 F8 RF5(Ext) RF1 (800MHz) F4 1 CRF 12 F3 F11 GND F2 2 CRF F7 11 F1 RF3 (GPS) F6 RF4(Ant) GND 10 3 F5 CRF CRF F9 F10 GND 9 4 8 CTLC 7 Cbypass (100pF) CTLA CTLB 6 VDD 5 GND When using this IC, the following external components should be used: CRF: This capacitor is used for RF decoupling and must be used for all applications. Cbypass: This capacitor is used for DC line filtering. Truth Table State CTLA CTLB CTLC 1 ON state F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 RF4 – 1 (Ant-800MHz) ON OFF OFF OFF OFF OFF OFF ON ON OFF ON L L H 2 L H H RF4 – 2 (Ant-2GHz) OFF OFF ON OFF OFF OFF ON OFF ON OFF ON 3 H L H RF4 – 3 (Ant-GPS) OFF OFF OFF OFF ON OFF ON ON OFF OFF ON 4 L L L 5 L H L RF5 – 2 (EXT-2GHz) OFF OFF OFF ON OFF OFF ON OFF ON ON OFF 6 H L L RF5 – 3 (EXT-GPS) OFF OFF OFF OFF OFF ON ON ON OFF ON OFF RF5 – 1 (EXT-800MHz) OFF ON OFF OFF OFF OFF OFF ON ON ON OFF DC Bias Conditions (Ta = 25°C) Item Min. Typ. Max. Unit Vctl (H) 2.0 2.6 3.2 V Vctl (L) 0 — 0.5 V 2.6 2.85 3.2 V VDD -2- CXG1215UR Electrical Characteristics (Ta = 25°C) Item Insertion loss Isolation Symbol IL ISO Condition Min. Typ. Max. Unit 830 to 930MHz 0.35 0.50 dB 1575.42MHz 0.40 0.55 dB 1.92 to 2.17GHz 0.50 0.65 dB 830 to 930MHz 25 30 dB 1575.42MHz 23 30 dB 1.92 to 2.17GHz 20 30 dB VSWR VSWR Switching speed TSW 1dB compression input power P1dB VDD = 2.85V 2fo *1 –70 –65 dBc 3fo *1 –70 –65 dBc 2fo *2 –65 –60 dBc 3fo *2 –65 –60 dBc Harmonics 50Ω 1.2 1.4 — 5 10 μs 32 dBm *3 55 60 dBm *4 55 60 dBm Input IP3 IP3 Bias current Idd VDD = 2.85V 150 190 μA Control current Ictl Vctl(H) = 2.6V 15 20 μA *1 *2 *3 *4 Pin = 25dBm, 0/2.6V control, VDD = 2.85V, 890 to 930MHz Pin = 25dBm, 0/2.6V control, VDD = 2.85V, 1.92 to 1.98GHz Pin = 25dBm (900MHz) + 25dBm (901MHz), 0/2.6V control, VDD = 2.85V Pin = 25dBm (1.9GHz) + 25dBm (1.901GHz), 0/2.6V control, VDD = 2.85V -3- CXG1215UR Package Outline (Unit: mm) 16PIN UQFN㧔PLASTIC㧕 x4 0.1 S 0.4 ± 0.1 2.3 12 0.55 ± 0.05 C A-B غ0.9 9 C 4-R0.2 A B 8 26 1 0. 5 16 0.14 2.3 13 4 0.4 0.18 PIN 1 INDEX Thermal Die Pad 0.07 0.25 0.05 M S C A-B 0.05 S Solder Plating + 0.09 0.14 – 0.03 + 0.09 0.25 – 0.03 MAX0.02 S S TERMINAL SECTION PACKAGE STRUCTURE Note:Cutting burr of lead are 0.05mm MAX. PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING EIAJ CODE LEAD MATERIAL COPPER ALLOY JEDEC CODE PACKAGE MASS 0.01g SONY CODE UQFN-16P-01 LEAD PLATING SPECIFICATIONS ITEM -4- SPEC. LEAD MATERIAL COPPER ALLOY SOLDER COMPOSITION Sn-Bi Bi:1-4wt% PLATING THICKNESS 5-18µm Sony Corporation