October 2003 FPD87346 Low EMI, Low Dynamic Power (SVGA) XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling (RSDS™) Outputs General Description Features The FPD87346 is a timing controller that combines an LVDS single pixel input interface with National’s Reduced Swing Differential Signaling (RSDS™) output driver interface for (SVGA) XGA and Wide XGA resolutions. It resides on the TFT-LCD panel and provides the data buffering and control signal generation for (SVGA) XGA, and Wide XGA graphic modes. The RSDS™ path to the column driver contributes toward lowering radiated EMI and reducing system dynamic power consumption. This single RSDS™ bus conveys the 8-bit color data for (SVGA) XGA, and Wide XGA panels at 170 Mb/s when using VESA 60 Hz standard timing. n Reduced Swing Differential Signalling (RSDS™) digital bus reduces dynamic power, EMI and bus width from the timing controller n LVDS single pixel input interface system n Input clock range from 40 MHz to 85 MHz n Drives RSDS™ Column Drivers at 170 Mb/s with an 85 MHz clock (Max.) n Virtual 8 bit color depth in FRC/Dithering mode n Single narrow 9-bit differential Source Driver bus minimizes width of Source PCB n Ability to drive (SVGA) XGA and Wide XGA TFT-LCD Systems n Failure detect function in DE mode n CMOS circuitry operates from a 3.0V–3.6V supply System Diagram 20061501 FIGURE 1. Block Diagram of the LCD Module RSDS™ is a trademark of National Semiconductor Corporation © 2003 National Semiconductor Corporation DS200615 www.national.com FPD87346 PRS Low EMI, Low Dynamic Power (SVGA) XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling (RSDS™) Outputs PRELIMINARY FPD87346 Block Diagram 20061519 FIGURE 2. Block Diagram Functional Description FPD-LINK RECEIVER The LVDS based FPD-Link Receiver inputs video data and control timing through 4-LVDS channels plus clock to provide 24-bit color or 3-LVDS channels can be used for 18-bit color. The video data is converted to a parallel data stream and routed to the 8-6 bit translator. ential pair. The RSDS Column Drivers latch data on both positive and negative edges of the clock. The RSDS output setup/hold timings are also adjustable through the RSDS[2:0] input pins. TIMING CONTROL FUNCTION The Timing Control function generates control to Column Drivers, Row Drivers, and power supply. The GPOs (General Purpose Outputs) provide for CD latch pulse, REV, and Row Driver control generation. The General Purpose Outputs allow the user to generate control anywhere within the frame data. Standard Row Driver interface or Custom Row Driver interfaces can be implemented with the GPOs (General Purpose Outputs). SPREAD SPECTRUM SUPPORT The FPD-Link receiver supports graphics controllers with Spread Spectrum interfaces for reducing EMI. The Spread Spectrum methods supported are Center and Down Spread. A maximum of 2% total is supported at a frequency modulation of 100kHz maximum. 8-6 BIT TRANSLATOR 8-bit data is reduced to a 6-bit data path via a time multiplexed dithering technique or simple truncation of the LSBs. This function is enabled via the input control pins. RSDS OUTPUT VOLTAGE CONTROL The RSDS output voltage swing is controlled through an external load resistor connected to the RPI pin. The RSDS output signal levels can be adjusted to suit the particular application. This is dependent on overall LCD module design characteristics such as trace impedance, termination, etc. The RSDS output voltage is inversely related to the RPI value. Lower RPI values will increase the RSDS output voltage swing and consequently overall power consumption will also increase. DATAPATH BLOCK AND RSDS TRANSMITTER 6(8)-bit video data (RGB) is input to the Datapath Block supports up to an 85 MHz pixel rate. The data is delayed to align the Column Driver Start Pulse (STH) with the Column Driver data. The data bus (RSR[2:0]P/N, RSG[2:0]P/N, RSB[2:0]P/N) outputs at a 170 MHz rate on 9 differential output channels. The clock is output on the RSCKP/N differ- www.national.com 2 inches (millimeters) unless otherwise noted 64-pin TQFP Package Order Number FPD87346VS NS Package Number VEC-64A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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National Semiconductor Americas Customer Support Center Email: [email protected] Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: [email protected] National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: [email protected] Tel: 81-3-5639-7560 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. FPD87346 PRS Low EMI, Low Dynamic Power (SVGA) XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling (RSDS™) Outputs Physical Dimensions