ADC1251 Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold General Description The ADC1251 is a CMOS 12-bit plus sign successive approximation analog-to-digital converter. On request, the ADC1251 goes through a self-calibration cycle that adjusts for any zero, full scale, or linearity errors. The ADC1251 also has the ability to go through an Auto-Zero cycle that corrects the zero error during every conversion. The analog input to the ADC1251 is tracked and held by the internal circuitry, so an external sample-and-hold is not required. The ADC1251 has an S/H control input which directly controls the track-and-hold state of the A/D. A unipolar analog input voltage range (0 to a 5V) or a bipolar range (b5V to a 5V) can be accommodated with g 5V supplies. The 13-bit data result is available on the eight outputs of the ADC1251 in two bytes, high-byte first and sign extended. The digital inputs and outputs are compatible with TTL or CMOS logic levels. Y Y Y Y 8-bit mP/DSP interface Bipolar input range with a single a 5V reference No missing codes over temperature TTL/MOS input/output compatible Key Specifications Y Y Y Y Y Y Y Resolution Conversion Time Sampling Rate Linearity Error Zero Error Full Scale Error Power Consumption 12 bits plus sign 8 ms (max) 83 kHz (max) g 0.6 LSB ( g 0.0146%) (max) g 1 LSB (max) g 1.5 LSB (max) @ g 5V 113 mW (max) Applications Y Y Y Features Y Y Digital signal processing High resolution process control Instrumentation Self-calibration provides excellent temperature stability Internal sample-and-hold Simplified Block Diagram Connection Diagram Dual-In-Line Package TL/H/11024 – 2 Top View Ordering Information Industrial (b40§ C s TA s a 85§ C) ADC1251BIJ, ADC1251CIJ TL/H/11024 – 1 Package J24A Military Package (b55§ C s TA s a 125§ C) ADC1251CMJ, ADC1251CMJ/883 J24A TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/H/11024 RRD-B30M115/Printed in U. S. A. ADC1251 Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold December 1994 Absolute Maximum Ratings (Notes 1 & 2) Operating Ratings (Notes 1 & 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Temperature Range ADC1251BIJ, ADC1251CIJ ADC1251CMJ ADC1251CMJ/883 b 40§ C s TA s a 85§ C b 55§ C s TA s a 125§ C b 55§ C s TA s a 125§ C DVCC and AVCC Voltage (Notes 6 & 7) Negative Supply Voltage (Vb) b 4.5V to b 5.5V Supply Voltage (VCC e DVCC e AVCC) 6.5V b 6.5V Negative Supply Voltage (Vb) b 0.3V to (VCC a 0.3V) Voltage at Logic Control Inputs Voltage at Analog Inputs (VREF, VIN) (Vb b0.3V) to (VCC a 0.3V) 0.3V AVCC-DVCC (Note 7) g 5 mA Input Current at Any Pin (Note 3) g 20 mA Package Input Current (Note 3) 875 mW Power Dissipation at 25§ C (Note 4) b 65§ C to a 150§ C Storage Temperature Range ESD Susceptability (Note 5) Soldering Information J Package (10 sec.) TMIN s TA s TMAX Reference Voltage (VREF, Notes 6 & 7) 4.5V to 5.5V 3.5V to AVCC a 50 mV 2000V 300§ C Converter Electrical Characteristics The following specifications apply for VCC e DVCC e AVCC e a 5.0V, Vb e b5.0V, VREF e a 5.0V, AZ e ‘‘1’’, fCLK e 3.5 MHz and tested using WR control unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits TA e TJ e 25§ C. (Notes 6, 7 and 8) Symbol Parameter Conditions Typical Limit (Note 9) (Notes 10, 19) Units (Limit) STATIC CHARACTERISTICS Positive Integral Linearity Error ADC1251BIJ ADC1251CIJ After Auto-Cal (Notes 11 & 12) ADC1251CMJ Negative Integral Linearity Error ADC1251BIJ ADC1251CIJ After Auto-Cal (Notes 11 and 12) ADC1251CMJ Missing Codes After Auto-Cal (Notes 11 and 12) Zero Error (Notes 12 and 13) AZ e ‘‘0’’ and fCLK e 1.75 MHz AZ e ‘‘0’’ and fCLK e 1.75 MHz After Auto-Cal Only Negative Full-Scale Error (Note 12) LSB(max) g1 LSB(max) g1 LSB(max) g 0.6 LSB(max) g1 LSB(max) g1 LSB(max) 0 After Auto-Cal Only Positive Full-Scale Error (Note 12) g 0.6 AZ e ‘‘0’’ and fCLK e 1.75 MHz After Auto-Cal Only g2 LSB(max) g 2.0/ g 3.0 LSB(max) g 1.5 LSB(max) g 1.5/ g 2.0 LSB(max) g 1.5 LSB(max) g 1.5/ g 2.0 LSB(max) CREF VREF Input Capacitance (Note 18) 80 pF CIN Analog Input Capacitance 65 pF VIN Analog Input Voltage Power Supply Sensitivity Vb b 0.05 VCC a 0.05 Zero Error (Note 14) AVCC e DVCC e 5V g 5%, e 4.75V, V b e b 5V g 5% V Full-Scale Error REF Linearity Error 2 V(min) V(max) g (/8 LSB g (/8 LSB g (/8 LSB Converter Electrical Characteristics (Continued) The following specifications apply for VCC e DVCC e AVCC e a 5.0V, Vb e b5.0V, VREF e a 5.0V, AZ e ‘‘1’’ and fCLK e 3.5 MHz unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits TA e TJ e 25§ C. (Notes 6, 7 and 8) Conditions Typical (Note 9) Unipolar Signal-to-Noise a Distortion Ratio (Note 17) fIN e 1 kHz, VIN e 4.85 Vp-p 72 dB fIN e 20 kHz, VIN e 4.85 Vp-p 72 dB Bipolar Signal-to-Noise a Distortion Ratio (Note 17) fIN e 1 kHz, VIN e g 4.85V 76 dB fIN e 20 kHz, VIN e g 4.85V 76 dB b 3 dB Unipolar Full Power Bandwidth VIN e 4.85V, (Note 17) 32 kHz b 3 dB Bipolar Full Power Bandwidth VIN e g 4.85V, (Note 17) 25 kHz Symbol Parameter Limit (Notes 10, 19) Units (Limit) DYNAMIC CHARACTERISTICS S/(N a D) S/(N a D) tAp Aperture Time 100 ns Aperture Jitter 100 psrms Digital and DC Electrical Characteristics The following specifications apply for DVCC e AVCC e a 5.0V, Vb e b5.0V, VREF e a 5.0V, and fCLK e 3.5 MHz unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits TA e TJ e 25§ C. (Notes 6 and 7) Symbol Parameter Conditions Typical (Note 9) Limit (Notes 10, 19) Units (Limit) VIN(1) Logical ‘‘1’’ Input Voltage for All Inputs except CLK IN VCC e 5.25V 2.0 V(min) VIN(0) Logical ‘‘0’’ Input Voltage for All Inputs except CLK IN VCC e 4.75V 0.8 V(max) IIN(1) Logical ‘‘1’’ Input Current VIN e 5V 0.005 1 mA(max) IIN(0) Logical ‘‘0’’ Input Current VIN e 0V b 0.005 b1 mA(max) VT a CLK IN Positive-Going Threshold Voltage 2.8 2.7 V(min) VTb CLK IN Negative-Going Threshold Voltage 2.1 2.3 V(max) VH CLK IN Hysteresis [VT a (min) b VTb(max)] 0.7 0.4 V(min) VOUT(1) Logical ‘‘1’’ Output Voltage 2.4 4.5 V(min) V(min) 0.4 V(max) VOUT(0) Logical ‘‘0’’ Output Voltage IOUT TRI-STATEÉ Output Leakage Current VCC e 4.75V: IOUT e b360 mA IOUT e b10 mA VCC e 4.75V, IOUT e 1.6 mA VOUT e 0V b 0.01 b3 mA(max) VOUT e 5V 0.01 3 mA(max) Output Source Current VOUT e 0V b 20 b 6.0 mA(min) ISINK Output Sink Current VOUT e 5V 20 8.0 mA(min) DICC DVCC Supply Current CS e ‘‘1’’ 1 2.5 mA(max) AICC AVCC Supply Current CS e ‘‘1’’ 4 10 mA(max) Ib Vb Supply Current CS e ‘‘1’’ 2.8 10 mA(max) ISOURCE 3 AC Electrical Characteristics The following specifications apply for DVCC e AVCC e a 5.0V, Vb e b5.0V, tr e tf e 20 ns unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits TA e TJ e 25§ C. (Notes 6 and 7) Symbol fCLK Parameter Conditions Typical (Note 9) Clock Duty Cycle Conversion Time Using WR to Start a Conversion tC Units (Limit) 3.5 MHz MHz(min) MHz(max) 40 60 % %(min) %(max) 27(1/fCLK) a 250 ns (max) Clock Frequency 0.5 6.0 tC Limit (Notes 10, 19) 50 27(1/fCLK) fCLK e 3.5 MHz, AZ e ‘‘1’’ 7.7 7.95 ms(max) fCLK e 1.75 MHz, AZ e ‘‘0’’ 15.4 15.65 ms(max) 34(1/fCLK) 34(1/fCLK) a 250 ns (max) Conversion Time Using S/H to Start a Conversion AZ e ‘‘1’’ fCLK e 3.5 MHz, AZ e ‘‘1’’ 9.7 9.95 ms(max) tA Acquisition Time (Note 15) RSOURCE e 50X 3.5 3.5 ms(min) tIA Internal Acquisition Time (When Using WR Control Only) 7(1/fCLK) 7(1/fCLK) (max) tZA Auto Zero Time a Acquisition Time tD(EOC)L Delay from Hold Command to Falling Edge of EOC tCAL 33(1/fCLK) 33(1/fCLK) a 250 ns (max) fCLK e 1.75 MHz 18.8 19.05 ms(max) Using WR Control 200 350 ns(max) Using S/H Control 100 150 ns(max) 1399(1/fCLK) 1399 (1/fCLK) (max) Calibration Time tW(CAL)L Calibration Pulse Width fCLK e 3.5 MHz 399 400 ms(max) (Note 16) 60 200 ns(min) 60 200 ns(min) 50 95 ns(max) 30 70 ns(max) tW(WR)L Minimum WR Pulse Width tACC t0H, t1H Maximum Access Time (Delay from Falling Edge of RD to Output Data Valid) CL e 100 pF TRI-STATE Control (Delay from Rising Edge of RD to Hi-Z State) RL e 1 kX, CL e 100 pF tPD(INT) Maximum Delay from Falling Edge of RD or WR to Reset of INT 100 175 ns(max) tRR Delay between Successive RD Pulses 30 60 ns(min) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to AGND and DGND, unless otherwise specified. Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN k Vb or VIN l (AVCC or DVCC), the current at that pin should be limited to 5 mA. The 20 mA maximum package input current rating allows the voltage at any four pins, with an input current limit of 5 mA, to simultaneously exceed the power supply voltages. Note 4: The power dissipation of this device under normal operation should never exceed 191 mW (Quiescent Power Dissipation a 1 TTL Load on each digital output). Caution should be taken not to exceed absolute maximum power rating when the device is operating in severe fault condition (ex. when any inputs or outputs exceed the power supply). The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), iJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax e (TJmax b TA)/iJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJmax e 150§ C, and the typical thermal resistance (iJA) of the ADC1251 with CMJ, BIJ, and CIJ suffixes when board mounted is 51§ C/W. Note 5: Human body model, 100 pF discharged through a 1.5 kX resistor. 4 Electrical Characteristics (Continued) Note 6: Two on-chip diodes are tied to the analog input as shown below. Errors in the A/D conversion can occur if these diodes are forward biased more than b 50 mV. This means that if AVCC and DVCC are minimum (4.75 VDC) and V is maximum ( b 4.75 VDC), the analog input full-scale voltage must be s g 4.8 VDC. TL/H/11024 – 4 Note 7: A diode exists between AVCC and DVCC as shown below. TL/H/11024 – 5 To guarantee accuracy, it is required that the AVCC and DVCC be connected together to a power supply with separate bypass filters at each VCC pin. Note 8: Accuracy is guaranteed at fCLK e 3.5 MHz. At higher or lower clock frequencies accuracy may degrade. See the Typical Performance Characteristics curves. Note 9: Typicals are at TJ e 25§ C and represent most likely parametric norm. Note 10: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 11: Positive linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full scale and zero. For negative linearity error the straight line passes through negative full scale and zero. (See Figures 1b and 1c ). Note 12: The ADC1251’s self-calibration technique ensures linearity, full scale, and offset errors as specified, but noise inherent in the self-calibration process will result in a repeatability uncertainty of g 0.20 LSB. Note 13: If TA changes then an Auto-Zero or Auto-Cal cycle will have to be re-started. See the typical performance characteristic curves. Note 14: After an Auto-Zero or Auto-Cal cycle at the specified power supply extremes. Note 15: When using the WR control to start a conversion if the clock is asynchronous to the rising edge of WR an uncertainty of one clock period will exist in the end of the interval tA, therefore making tA end a minimum 6 clock periods or a maximum 7 clock periods after the rising edge of WR. If the falling edge of the clock is synchronous to the rising edge of WR then tA will end exactly 6.5 clock periods after the rising edge of WR. This does not occur when S/H control is used. Note 16: The CAL line must be high before a conversion is started. Note 17: The specifications for these parameters are valid after an Auto-Cal cycle has been completed. Note 18: The ADC1251 reference ladder is composed solely of capacitors. Note 19: A Military RETS Electrical Test Specification is available on request. At time of printing the ADC1251CMJ/883 RETS specification complies fully with the boldface limits in this column. FIGURE 1a. Transfer Characteristic 5 TL/H/11024 – 6 Electrical Characteristics (Continued) TL/H/11024 – 7 FIGURE 1b. Simplified Error Curve vs Output Code without Auto-Cal or Auto-Zero Cycles TL/H/11024 – 8 FIGURE 1c. Simplified Error Curve vs Output Code after Auto-Cal Cycle Typical Performance Characteristics Zero Error Change vs Ambient Temperature Zero Error vs VREF Linearity Error vs VREF TL/H/11024 – 9 6 Typical Performance Characteristics (Continued) Linearity Error vs Clock Frequency Full Scale Error Change vs Ambient Temperature Bipolar Signal-toNoise a Distortion Ratio vs Input Source Impedance Bipolar Signal-toNoise a Distortion Ratio vs Input Frequency Unipolar Signal-toNoise a Distortion Ratio vs Input Frequency Unipolar Signal-toNoise a Distortion Ratio vs Input Signal Level Bipolar Signal-toNoise a Distortion Ratio vs Input Signal Level Bipolar Spectral Response with 1 kHz Sine Wave Input Bipolar Spectral Response with 10 kHz Sine Wave Input Bipolar Spectral Response with 20 kHz Sine Wave Input Bipolar Spectral Response with 40 kHz Sine Wave Input Unipolar Spectral Response with 1 kHz Sine Wave Input TL/H/11024 – 10 7 Typical Performance Characteristics Unipolar Spectral Response with 10 kHz Sine Wave Input (Continued) Unipolar Spectral Response with 20 kHz Sine Wave Input Unipolar Spectral Response with 40 kHz Sine Wave Input TL/H/11024 – 11 Test Circuits TL/H/11024 – 13 TL/H/11024–12 TL/H/11024 – 15 TL/H/11024–14 FIGURE 2. TRI-STATE Test Circuits and Waveforms 8 Timing Diagrams Auto-Cal Cycle TL/H/11024 – 16 Using WR Control to Start a Conversion with Auto-Zero (CAL e 1, AZ e 0) TL/H/11024 – 17 9 Timing Diagrams (Continued) Using WR Control to Start a Conversion without Auto-Zero (CAL e 1, AZ e 1) TL/H/11024 – 18 Using S/H Control to Start a Conversion without Auto-Zero (AZ e 1, CAL e 1) TL/H/11024 – 19 10 1.0 Pin Descriptions DVCC (24), AVCC (4) V b (5) DGND (12), AGND (3) VREF (2) VIN (1) CS (10) The digital and analog positive power supply pins. The digital and analog power supply voltage range of the ADC1251 is a 4.5V to a 5.5V. To guarantee accuracy, it is required that the AVCC and DVCC be connected together to the same power supply with separate bypass capacitors (10 mF tantalum in parallel with a 0.1 mF ceramic) at each VCC pin. The analog negative supply voltage pin. Vb has a range of b4.5V to b5.5V and needs bypass capacitors of 10 mF tantalum in parallel with a 0.1 mF ceramic. The digital and analog ground pins. AGND and DGND must be connected together externally to guarantee accuracy. The Read control input. With both CS and RD low the TRI-STATE output buffers are enabled and the INT output is reset high. WR (7) The Write control input. The conversion is started on the rising edge of the WR pulse when CS is low. When this control line is used the end of the analog input voltage acquisition window is internally controlled by the ADC1251. S/H (11) CLKIN (8) The Auto-Calibration control input. When CAL is low the ADC1251 is reset and a calibration cycle is initiated. During the calibration cycle the values of the comparator offset voltage and the mismatch errors in the capacitor reference ladder are determined and stored in RAM. These values are used to correct the errors during a normal cycle of A/D conversion. AZ (6) The Auto-Zero control input. With the AZ pin held low during a conversion, the ADC1251 goes into an auto-zero cycle before the actual A/D conversion is started. This Auto-Zero cycle corrects for the comparator offset voltage. The total conversion time (tC) is increased by 26 clock periods when Auto-Zero is used. INT (21) The Interrupt control output. This output goes low when a conversion has been completed and indicates that the conversion result is available in the output latches. Reading the result or starting a conversion or calibration cycle will reset this output high. The TRI-STATE output pins. Twelve bit plus sign output data access is accomplished using two successive RDs of one byte each, high byte first (DB8 – DB12). The data format used is two’s complement sign bit extended with DB12 the sign bit, DB11 the MSB and DB0 the LSB. 2.0 Functional Description The ADC1251 is a 12-bit plus sign A/D converter with the capability of doing Auto-Zero or Auto-Cal routines to minimize zero, full-scale and linearity errors. It is a successiveapproximation A/D converter consisting of a DAC, comparator and a successive-approximation register (SAR). AutoZero is an internal calibration sequence that corrects for the A/D’s zero error caused by the comparator’s offset voltage. Auto-Cal is a calibration cycle that not only corrects zero error but also corrects for full-scale and linearity errors caused by DAC inaccuracies. Auto-Cal minimizes the errors of the ADC1251 without the need for trimming during its fabrication. An Auto-Cal cycle can restore the accuracy of the ADC1251 at any time, which ensures accuracy over temperature and time. 2.1 DIGITAL INTERFACE On power up, a calibration sequence should be initiated by pulsing CAL low with CS and S/H high. To acknowledge the CAL signal, EOC goes low after the falling edge of CAL, and remains low during the calibration cycle of 1399 clock periods. During the calibration sequence, first the comparator’s offset is determined, then the capacitive DAC’s mismatch errors are found. Correction factors for these errors are then stored in internal RAM. A conversion can be initiated by taking CS and WR low. If AZ is low an Auto-Zero cycle, which takes approximately 26 clock periods, is inserted before the analog input is sampled and the actual conversion is started. AZ must remain low during the complete conversion sequence. After Auto-Zero the acquisition opens and the analog input is sampled for approximately 7 clock periods. If AZ is high, the Auto-Zero cycle is not inserted after the rising edge of WR. In this case the acquisition window opens when the ADC1251 completes a conversion, signaled by the rising edge of EOC. At the end of the acquisition window EOC goes low, signaling that the analog input is no longer being sampled and that the A/D successive approximation conversion has started. The sample and hold control input. This control input can also be used to start a conversion. With CS low the falling edge of S/H starts the analog input acquisition window. The rising edge of S/H ends the acquisition window and starts a conversion. The external clock input pin. The typical clock frequency range is 500 kHz to 6.0 MHz. CAL (9) The End-of-Conversion control output. This output is low during a conversion or a calibration cycle. DB0/DB8 – DB7/DB12 (13 – 20) The reference input voltage pin. To maintain accuracy the voltage at this pin should not exceed the AVCC or DVCC by more than 50 mV or go below a 3.5 VDC. The analog input voltage pin. To guarantee accuracy the voltage at this pin should not exceed VCC by more than 50 mV or go below Vb by more than 50 mV. The Chip Select control input. This input is active low and enables the WR, RD and S/H functions. RD (23) EOC (22) 11 2.0 Functional Description (Continued) Mode, where RD and S/H are high and CS and CAL are low, is used during manufacture to thoroughly check out the operation of the ADC1251. Care should be taken not to inadvertently be in this mode, since DB2, DB3, DB5, and DB6 become active outputs, which may cause data bus contention. A conversion sequence can also be controlled by the S/H and CS inputs. Taking CS and S/H low starts the acquisition window for the analog input voltage. The rising edge of S/H immediately puts the A/D in the hold mode and starts the conversion. Using S/H will simplify synchronizing the end of the acquisition window to other signals, which may be necessary in a DSP environment. During a conversion, the sampled input voltage is successively compared to the output of the DAC. First, the acquired input voltage is compared to analog ground to determine its polarity. The sign bit is set low for positive input voltages and high for negative. Next the MSB of the DAC is set high with the rest of the bits low. If the input voltage is greater than the output of the DAC, then the MSB is left high; otherwise it is set low. The next bit is set high, making the output of the DAC three quarters or one quarter of full scale. A comparison is done and if the input is greater than the new DAC value this bit remains high; if the input is less than the new DAC value the bit is set low. This process continues until each bit has been tested. The result is then stored in the output latch of the ADC1251. Next INT goes low and EOC goes high to signal the end of the conversion. The result can now be read by taking CS and RD low to enable the DB0/DB8–DB7/DB12 output buffers. The high byte of data is relayed first on the data bus outputs as shown below: DB0/ DB1/ DB2/ DB3/ DB8 DB9 DB10 DB11 Bit 8 Bit 9 Bit 10 MSB DB4/ DB12 DB5/ DB12 DB6/ DB12 2.2 RESETTING THE A/D The ADC1251 is reset whenever a new conversion is started by taking CS and WR or S/H low. If this is done when the analog input is being sampled or when EOC is low, the Auto-Cal correction factors may be corrupted, therefore requiring an Auto-Cal cycle before the next conversion. When using WR or S/H without Auto-Zero (AZ e 1) to start a conversion, a new conversion can be restarted only after EOC has gone high, signaling the end of the current conversion. When using WR with Auto-Zero (AZ e 0) a new conversion can be restarted during the first 26 clock periods after the rising edge of WR (tZ) or after EOC has returned high without corrupting the Auto-Cal correction factors. The Calibration Cycle cannot be reset once started. On power-up the ADC1251 automatically goes through a Calibration Cycle that takes typically 1399 clock cycles. For reasons that will be discussed in Section 3.8, a new calibration cycle needs to be started after the completion of the automatic one. 3.0 Analog Considerations DB7/ DB12 3.1 REFERENCE VOLTAGE The voltage applied to the reference input of the converter defines the voltage span of the analog input (the difference between VIN and AGND), over which 4095 positive output codes and 4096 negative output codes exist. The A-to-D can be used in either ratiometric or absolute reference applications. The voltage source driving VREF must have a very low output impedance and very low noise. The circuit in Figure 4 is an example of a very stable reference that is appropriate for use with the ADC1251. Sign Bit Sign Bit Sign Bit Sign Bit Taking CS and RD low a second time will relay the low byte of data on the data bus outputs as shown below: DB0/ DB8 DB1/ DB9 DB2/ DB10 DB3/ DB11 DB4/ DB12 DB5/ DB12 DB6/ DB12 DB7/ DB12 LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 The table in Figure 3 summarizes the effect of the digital control inputs on the function of the ADC1251. The Test Digital Control Inputs A/D Function CS WR S/H RD CAL AZ ß ß 1 1 1 ß 1 ß 1 1 ß 1 1 ß 1 ß ß 1 1 1 ß 1 1 ß 1 1 X 1 X ß 0 X X 1 0 1 1 1 0 0 X X Start Conversion without Auto-Zero Start Conversion synchronous with rising edge of S/H without Auto-Zero Read Conversion Result without Auto-Zero Start Conversion with Auto-Zero Read Conversion Result with Auto-Zero Start Calibration Cycle Test Mode (DB2, DB3, DB5, and DB6 become active) FIGURE 3. Function of the A/D Control Inputs 12 3.0 Analog Considerations (Continued) *Tantalum **Ceramic TL/H/11024 – 20 FIGURE 4. Low Drift Extremely Stable Reference Circuit this method the acquisition window is internally controlled by the ADC1251 and lasts for approximately 7 clock periods. Since the acquisition window needs to be at least 3.5 ms at all times, when using Auto-Zero the maximum clock frequency is limited to 2 MHz. The zero error with the Auto-Zero cycle is production tested at a clock frequency of 1.75 MHz. This accommodates easy switching between a conversion with the Auto-Zero cycle (fCLK e 1.75 MHz) and without (fCLK e 3.5 MHz) as shown in Figure 5 . In a ratiometric system, the analog input voltage is proportional to the voltage used for the A/D reference. When this voltage is the system power supply, the VREF pin can be tied to VCC. This technique relaxes the stability requirement of the system reference as the analog input and A/D reference move together maintaining the same output code for a given input condition. For absolute accuracy, where the analog input varies between very specific voltage limits, the reference pin can be biased with a time and temperature stable voltage source. In general, the magnitude of the reference voltage will require an initial adjustment to null out full-scale errors. 3.2 ACQUISITION WINDOW As shown in the timing diagrams there are three different methods of starting a conversion, each of which affects the acquisition window and timing. With Auto-Zero high a conversion can be started with the WR or S/H controls. In either method of starting a conversion the rising edge of EOC signals the actual beginning of the acquisition window. At this time a voltage spike may be noticed on the analog input of the ADC1251 whose amplitude is dependent on the input voltage and the source resistance. The timing diagrams for these two methods of starting a conversion do not show the acquisition window starting at this time because the acquisition time (tA) must start after the conversion result high and low bytes have been read. This is necessary since activating and deactivating the digital outputs (DB0/DB7–DB8/DB12) causes current fluctuations in the ADC1251’s internal DVCC lines. This generates digital noise which couples into the capacitive ladder that stores the analog input voltage. Therefore, the time interval between the rising edge of EOC and the second read is inappropriate for analog input voltage acquisition. When WR is used to start a conversion with AZ low the Auto-Zero cycle is inserted before the acquisition window. In TL/H/11024 – 21 FIGURE 5. Switching between a Conversion with and without Auto-Zero when Using WR Control 3.3 INPUT CURRENT Because the input network of the ADC1251 is made up of a switch and a network of capacitors a charging current will flow into or out of (depending on the input voltage polarity) the analog input pin (VIN) on the start of the analog input sampling period. The peak value of this current will depend on the actual input voltage applied and the source resistance. 3.4 NOISE The leads to the analog input pin should be kept as short as possible to minimize input noise coupling. Both noise and undesired digital clock coupling to this input can cause errors. Input filtering can be used to reduce the effects of these noise sources. 13 3.0 Analog Considerations (Continued) change. Since Auto-Zero cannot be activated with S/H conversion method it may be necessary to do a calibration cycle more than once. 3.5 INPUT BYPASS CAPACITORS An external capacitor can be used to filter out any noise due to inductive pickup by a long input lead and will not degrade the accuracy of the conversion result. 3.9 THE AUTO-ZERO CYCLE To correct for any change in the zero (offset) error of the A/D, the Auto-Zero cycle can be used. It may be necessary to do an Auto-Zero cycle whenever the ambient temperature changes significantly. (See the curve titled ‘‘Zero Error Change vs Ambient Temperature’’ in the Typical Performance Characteristics.) A change in the ambient temperature will cause the VOS of the sampled data comparator to change, which may cause the zero error of the A/D to be greater than g 1 LSB. An Auto-Zero cycle will maintain the zero error to g 1 LSB or less. 3.6 INPUT SOURCE RESISTANCE The analog input can be modeled as shown in Figure 6 . External RS will lengthen the time period necessary for the voltage on CREF to settle to within (/2 LSB of the analog input voltage. With tA e 3.5 ms, RS s 1 kX will allow a 5V analog input voltage to settle properly. 3.7 POWER SUPPLIES b Noise spikes on the VCC and V supply lines can cause conversion errors as the comparator will respond to this noise. The A/D is especially sensitive during the Auto-Zero or -Cal procedures to any power supply spikes. Low inductance tantalum capacitors of 10 mF or greater paralleled with 0.1 mF ceramic capacitors are recommended for supply bypassing. Separate bypass capacitors should be placed b close to the DVCC, AVCC and V pins. If an unregulated voltage source is available in the system, a separate LM340LAZ-5.0 voltage regulator for the A-to-D’s VCC (and other analog circuitry) will greatly reduce digital noise on the supply line. 4.0 Dynamic Performance Many applications require the A/D converter to digitize AC signals, but the standard DC integral and differential nonlinearity specifications will not accurately predict the A/D converter’s performance with AC input signals. The important specifications for AC applications reflect the converter’s ability to digitize AC signals without significant spectral errors and without adding noise to the digitized signal. Dynamic characteristics such as signal-to-noise a distortion ratio (S/(N a D)), effective bits, full power bandwidth, aperture time and aperture jitter are quantitative measures of the A/D converter’s capability. An A/D converter’s AC performance can be measured using Fast Fourier Transform (FFT) methods. A sinusoidal waveform is applied to the A/D converter’s input, and the transform is then performed on the digitized waveform. S/ (N a D) is calculated from the resulting FFT data, and a spectral plot may also be obtained. Typical values for S/ (N a D) are shown in the table of Electrical Characteristics, and spectral plots are included in the typical performance curves. The A/D converter’s noise and distortion levels will change with the frequency of the input signal, with more distortion and noise occurring at higher signal frequencies. This can be seen in the S/(N a D) versus frequency curves. These curves will also give an indication of the full power bandwidth (the frequency at which the S/(N a D) drops 3 dB). 3.8 THE CALIBRATION CYCLE On power up the ADC1251 goes through an Auto-Cal cycle which cannot be interrupted. Since the power supply, reference, and clock will not be stable at power up, this first calibration cycle will not result in an accurate calibration of the A/D. A new calibration cycle needs to be started after the power supplies, reference, and clock have been given enough time to stabilize. During the calibration cycle, correction values are determined for the offset voltage of the sampled data comparator and any linearity and gain errors. These values are stored in internal RAM and used during an analog-to-digital conversion to bring the overall full scale, offset, and linearity errors down to the specified limits. Full scale error typically changes g 0.2 LSB over temperature and linearity error changes even less; therefore it should be necessary to go through the calibration cycle only once after power up if Auto-Zero is used to correct the zero error TL/H/11024 – 22 FIGURE 6. Analog Input Equivalent Circuit 14 4.0 Dynamic Performance (Continued) the ADC1251 actually holds the input signal is the aperture time. For the ADC1251, this time is typically 100 ns. Aperture jitter is the change in the aperture time from sample to sample. Aperture jitter is useful in determining the maximum slew rate of the input signal for a given accuracy. For example, an ADC1251 with 100 ps of aperture jitter operating with a 5V reference can have an effective gain variation of about 1 LSB with an input signal whose slew rate is 12 V/ms. Two sample/hold specifications, aperture time and aperture jitter, are included in the Dynamic Characteristics table since the ADC1251 has the ability to track and hold the analog input voltage. Aperture time is the delay for the A/D to respond to the hold command. In the case of the ADC1251 when using the S/H control to start a conversion, the hold command is generated by the rising edge of S/H. The delay between the rising edge of S/H and the time that 5.0 Typical Applications Power Supply Bypassing TL/H/11024 – 23 Protecting the Analog Inputs TL/H/11024 – 24 Note: External protection diodes should be able to withstand the op amp current limit. 15 ADC1251 Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold Physical Dimensions inches (millimeters) Order Number ADC1251CMJ, ADC1251CMJ/883, ADC1251BIJ or ADC1251CIJ NS Package Number J24A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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