August 26, 2009 ADC1005 10-Bit μP Compatible A/D Converter General Description Features NOTE: This device is obsolete. This data sheet is provided for information only. The ADC1005 is a CMOS 10-bit successive approximation A/ D converter. The 20-pin ADC1005 outputs 10-bit data in a two-byte format for interface with 8-bit microprocessors. The ADC1005 has differential inputs to permit rejection of common-mode signals, allow the analog input range to be offset, and also to permit the conversion of signals not referred to ground. In addition, the reference voltage can be adjusted, allowing smaller voltage spans to be measured with 10-bit resolution. ■ Easy interface to all microprocessors ■ Differential analog voltage inputs ■ Operates ratiometrically or with 5 VDC voltage reference or ■ ■ ■ ■ analog span adjusted voltage reference 0V to 5V analog input voltage range with single 5V supply On-chip clock generator TLL/MOS input/output compatible 0.3″ standard width 20-pin DIP Key Specifications ■ Resolution ■ Linearity Error ■ Conversion Time 10 bits ±½ LSB and ±1 LSB 50 μs Connection Diagram ADC 1005 (for an 8–bit data bus) Dual-In-Line Package 526101 Top View Ordering Information Part Number Package Outline Temperature Range Linearity Error NOTE: All versions of this device are obsolete ADC1005BCJ-1 J20A 0°C to +70°C ADC1005BCJ J20A −40°C to +85°C ADC1005CCJ-1 J20A 0°C to +70°C ±½ LSB ±1 LSB TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2009 National Semiconductor Corporation 5261 5261 Version 8 Revision 2 www.national.com Print Date/Time: 2009/08/26 22:47:16 ADC1005 10-Bit μP Compatible A/D Converter OBSOLETE ADC1005 Absolute Maximum Ratings (Notes 1, 2) Operating Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. (Notes 1, 2) Supply Voltage (VCC) Logic Control Inputs Voltage at Other Inputs and Outputs Input Current Per Pin Input Current Per Package Storage Temperature Range Package Dissipation at TA=25°C Lead Temperature (Soldering, 10 seconds) Dual-In-Line Package (Ceramic) ESD Susceptibility (Note 8) Supply Voltage (VCC) Temperature Range 6.5V −0.3V to +15V −0.3V to VCC +0.3V ±5 mA ±20 mA −65°C to +150°C 875 mW 4.5V to 6.0V TMN≤TA≤TMAX ADC1005BCJ, ADC1005BCJ-1, ADC1005CCJ-1 −40°C≤TA≤+85°C 300°C 800V Electrical Characteristics The following specifications apply for VCC = 5V, VREF = 5V, fCLK = 1.8 MHz unless otherwise specified. Boldface limits apply from TMIN to TMAX; All other limits TA = Tj = 25°C. ADC1005BCJ Parameter Conditions Typ (Note 5) Tested Limit (Note 6) ADC1005BCJ-1, ADC1005CCJ-1 Design Limit (Note 7) Typ (Note 5) Limit Units Tested Limit (Note 6) Design Limit (Note 7) ±0.5 ±1 ±0.5 ±1 LSB LSB LSB ±0.5 ±1 ±0.5 ±1 LSB LSB LSB ±0.5 ±1 ±0.5 ±1 LSB LSB LSB Converter Characteristics Linearity Error (Note 3) ADC1005BCJ ADC1005BCJ-1 ADC1005CCJ-1 ±0.5 Zero Error ADC1005BCJ ADC1005BCJ-1 ADC1005CCJ-1 ±0.5 Fullscale Error ADC1005BCJ ADC1005BCJ-1 ADC1005CCJ-1 ±0.5 Reference MIN 4.8 2.2 4.8 2.4 2.2 kΩ Input MAX 4.8 8.3 4.8 7.6 8.3 kΩ Resistance Common-Mode MIN Input (Note 4) MAX VIN(+) or VIN(−) VCC+0.05 VCC+0.05 VCC+0.05 V GND−0.05 GND−0.05 GND−0.05 V DC Common-Mode Error Over CommonMode Input Range ±⅛ ±¼ ±⅛ ±¼ ±¼ LSB Power Supply Sensitivity VCC=5 VDC±5% ±⅛ ±¼ ±⅛ ±¼ ±¼ LSB VREF = 4.75V www.national.com 2 5261 Version 8 Revision 2 Print Date/Time: 2009/08/26 22:47:16 Parameter Conditions Typ (Note 5) Tested Limit (Note 6) ADC1005BCJ-1, ADC1005CCJ-1 Design Limit (Note 7) Typ (Note 5) Limit Units Tested Limit (Note 6) Design Limit (Note 7) 2.0 2.0 2.0 V 0.8 0.8 0.8 V DC Characteristics VIN(1) Logical “1” Input Voltage VCC=5.25V MIN VIN(0), Logical “0” Input Voltage (except CLKIN ) VCC=4.75V MAX (Except CLKIN ) VIN=5.0V 0.005 1 0.005 1 1 μA VIN=0V −0.005 −1 −0.005 −1 −1 μA 3.1 2.7 3.1 2.7 2.7 V 3.1 3.5 3.1 3.5 3.5 V 1.8 1.5 1.8 1.5 1.5 V Negative going Threshold Voltage 1.8 2.1 1.8 2.1 2.1 V VH(MIN), Minimum CLKIN 1.3 0.6 1.3 0.6 0.6 V 1.3 2.0 1.3 2.0 2.0 V IIN, Logical “1” Input Current MAX IIN, Logical “0” Input Current MAX VT+(MIN), Minimum CLKIN Positive going Threshold Voltage VT(MAX), Maximum CLKIN Positive going Threshold Voltage VT−(MIN), Minimum CLKIN Negative going Threshold Voltage VT−(MAX), Maximum CLKIN Hysteresis (VT+-VT−) VH(MAX), Maximum CLKIN Hysteresis (VT+-VT−) VOUT(1), Logical “1” Output Voltage VCC=4.75V MIN VOUT(0), Logical “0” Output Voltage 2.8 2.4 V IOUT=−10 μA 4.5 4.6 4.5 V VCC=4.75V 0.4 0.34 0.4 V −0.3 −3 μA VOUT = 0V −0.01 MAX VOUT = 5V ISOURCE, Output Source Current 2.4 MAX IOUT=1.6 mA IOUT, TRI-STATE® Output Current IOUT=−360 μA −3 −0.01 0.01 3 0.01 0.3 3 μA VOUT=0V −14 −6.5 −14 −7.5 −6.5 mA VOUT=5V 16 8.0 16 9.0 8.0 mA 1.5 3 1.5 2.5 3 mA MIN ISINK, Output Sink Current MIN ICC, Supply Current MAX fCLK=1.8 MHz CS =“1” 3 5261 Version 8 Revision 2 Print Date/Time: 2009/08/26 22:47:16 www.national.com ADC1005 ADC1005BCJ ADC1005 AC Electrical Characteristics The following specifications apply for VCC = 5V, VREF = 5V,VREF = 5V, tr= tf= 20 ns unless otherwise specified. Boldface limits apply from TMIN to TMAX; All other limits TA = Tj = 25°C. Tested Limit (Note 6) Design Limit (Note 7) Limit Units MIN 0.2 0.2 MHz Parameter fCLK, Clock Frequency Conditions Typ (Note 5) MAX 2.6 2.6 MHz Clock Duty Cycle MIN MAX 40 60 40 60 % % tC, Conversion Time MIN 80 80 1/fCLK MAX 90 90 1/fCLK MIN fCLK=1.8 MHz 45 45 μs MAX fCLK=1.8 MHz 50 50 μs 100 150 150 ns tACC, Access Time (Delay from CS =0 falling edge of RD to Output Data CL=100 pF, RL = 2k Valid) 170 300 300 ns t1H, t0H, TRI-STATE Control RL=10k, CL=10 pF (Delay from Rising Edge of RD to RL=2k, CL=100 pF Hi-Z State) 125 tW(WR)L, Minimum WR Pulse Width CS =0 tWI, tRI, Delay from Falling Edge of WR or RD to Reset of INTR tIRS, INTR to 1st Read Set-up Time 200 ns 145 230 230 ns 300 450 450 ns 400 550 550 ns CIN, Capacitance of Logic Inputs 5 7.5 pF COUT, Capacitance of Logic Outputs 5 7.5 pF Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: All voltages are measured with respect to ground. Note 3: Linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line which passes through the end points of the transfer characteristic. Note 4: For VIN(−)≥VIN(+) the digital output code will be 00 0000 0000. Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct, especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading. Note 5: Typicals are at 25°C and represent most likely parametric norm. Note 6: Tested and guaranteed to National's AOQL (Average Outgoing Quality Level). Note 7: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels. Note 8: Human body model, 100 pF discharged through a 1.5 kΩ resistor. www.national.com 4 5261 Version 8 Revision 2 Print Date/Time: 2009/08/26 22:47:16 ADC1005 Functional Diagram 526103 Typical Performance Characteristics Logic Input Threshold Voltage vs Supply Voltage Delay from Falling Edge of RD to Output data Valid vs Load Capacitance 526121 526122 5 5261 Version 8 Revision 2 Print Date/Time: 2009/08/26 22:47:16 www.national.com ADC1005 CLK IN Schmitt Trip Levels vs Supply Voltage Output Current vs Temperature 526124 526123 Typical Linearity Error vs Clock Frequency 526125 Timing Diagrams Start Conversion 526105 www.national.com 6 5261 Version 8 Revision 2 Print Date/Time: 2009/08/26 22:47:16 ADC1005 Output Enable and Reset INTR 526106 Note: All timing is measured from the 50% voltage points. Byte Sequencing for ADC1005 Byte 8-Bit Data Bus Connection Order DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1st MSB Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 2nd Bit 1 LSB Bit 0 0 0 0 0 0 0 7 5261 Version 8 Revision 2 Print Date/Time: 2009/08/26 22:47:16 www.national.com ADC1005 Block Diagram 526111 Note 9: CS shown twice for clarity. Note 10: SAR=Successive Approximation Register. FIGURE 1. 1.2 Starting a Conversion The conversion is initialized by taking CS and WR simultaneously low. This sets the start flip-flop (F/F) and the resulting “1” level resets the 10-bit shift register, resets the interrupt (INTR) F/F and inputs a “1” to the D flop, F/F1, which is at the input end of the 10-bit shift register. Internal clock signals then transfer this “1” to the Q output of F/F1. The AND gate, G1, combines this “1” output with a clock signal to provide a reset signal to the start F/F. If the set signal is no longer present (either WR or CS is a “1”) the start F/F is reset and the 10-bit shift register then can have the “1” clocked in, allowing the conversion process to continue. If the set signal were still present, this reset pulse would have no effect and the 10-bit shift register would continue to be held in the reset mode. This logic therefore allows for wide CS and WR signals. The converter will start after at least one of these signals returns high and the internal clocks again provide a reset signal for the start F/F. To summarize, on the high-to-low transition of the WR input the internal SAR latches and the shift register stages are re- Functional Description 1.0 GENERAL OPERATION A block diagram of the A/D converter is shown in Figure 1. All of the inputs and outputs are shown and the major logic control paths are drawn in heavier weight lines. 1.1 Converter Operation The ADC1005 uses an advanced potentiometric resistive ladder network. The analog inputs, as well as the taps of this ladder network are switched into a weighted capacitor array. The output of this capacitor array is the input to a sampled data comparator. This comparator allows the successive approximation logic to match the analog input voltage [VIN(+) – VIN(−)] to taps on the R network. The most significant bit is tested first and after 10 comparisons (80 clock cycles) a digital 10-bit binary code (all “1”s = full-scale) is transferred to an output latch. www.national.com 8 5261 Version 8 Revision 2 Print Date/Time: 2009/08/26 22:47:16 voltage is typically the system power supply, so the VREF pin can be tied to VCC. This technique relaxes the stability requirements of the system references as the analog input and A/D reference move together maintaining the same output code for a given input condition. For absolute accuracy (Figure 4), where the analog input varies between very specific voltage limits, the reference pin can be biased with a time and temperature stable voltage source. The LM385 and LM336 reference diodes are good low current devices to use with these converters. The maximum value of the reference is limited to the VCC supply voltage. The minimum value, however, can be small to allow direct conversions of transducer outputs providing less than a 5V output span. Particular care must be taken with regard to noise pickup, circuit layout, and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1 LSB equals VREF/ 1024). 1.3 Output Control After the “1” is clocked through the 10-bit shift register (which completes the SAR search) it causes the new digital word to transfer to the TRI-STATE output latches. When the XFER signal makes a high-to-low transition the one shot fires, setting the INTR F/F. An inverting buffer then supplies the INTR output signal. Note that this SET control of the INTR F/F remains low for approximately 400 ns. If the data output is continuously enabled (CS and RD both held low) the INTR output will still signal the end of the conversion (by a high-to-low transition). This is because the SET input can control the Q output of the INTR F/F even though the RESET input is constantly at a “1” level. This INTR output will therefore stay low for the duration of the SET signal. When data is to be read, the combination of both CS and RD being low will cause the INTR F/F to be reset and the TRISTATE output latches will be enabled. 1.4 Free-Running and Self-Clocking Modes For operation in the free-running mode an initializing pulse should be used, following power-up, to ensure circuit operation. In this application, the CS input is grounded and the WR input is tied to the INTR output. This WR and INTR node should be momentarily forced to logic low following a powerup cycle to ensure start up. The clock for the A/D can be derived from the CPU clock or an external RC can be added to provide self-clocking. The CLK IN makes use of a Schmitt trigger as shown in Figure 2. 526117 FIGURE 3. Ratiometric 526112 FIGURE 2. Self-Clocking the A/D 2.0 REFERENCE VOLTAGE The voltage applied to the reference input of these converters defines the voltage span of the analog input (the difference between V IN(MAX) and VIN(MIN)) over which the 1024 possible output codes apply. The devices can be used in either ratiometric applications or in systems requiring absolute accuracy. The reference pin must be connected to a voltage source capable of driving the reference input resistance of typically 4.8 kΩ. This pin is the top of a resistor divider string used for the successive approximation conversion. In a ratiometric system (Figure 3) the analog input voltage is proportional to the voltage used for the A/D reference. This 526118 FIGURE 4. Absolute with a Reduced Span 9 5261 Version 8 Revision 2 Print Date/Time: 2009/08/26 22:47:16 www.national.com ADC1005 set. As long as the CS input and WR input remain low, the A/ D will remain in a reset state. Conversion will start after at least one of these inputs makes a low-to-high transition. ADC1005 3.5 Noise The leads to the analog inputs (pins 6 and 7) should be kept as short as possible to minimize input noise coupling. Both noise and undesired digital clock coupling to these inputs can cause system errors. The source resistance for these inputs should, in general, be kept below 1 kΩ. Larger values of source resistance can cause undesired system noise pickup. Input bypass capacitors, placed from the analog inputs to ground, can reduce system noise pickup but can create analog scale errors. See section 3.2, 3.3, and 3.4 if input filtering is to be used. 3.0 THE ANALOG INPUTS 3.1 Analog Differential Voltage Inputs and Common-Mode Rejection The differential inputs of these converters reduce the effects of common-mode input noise, which is defined as noise common to both selected “+” and “−” inputs (60 Hz is most typical). The time interval between sampling the “+” input and the “−” input is half of an internal clock period. The change in the common-mode voltage during this short time interval can cause conversion errors. For a sinusoidal common-mode signal, this error is: 4.0 OFFSET AND REFERENCE ADJUSTMENT 4.1 Zero Offset The zero error of the A/D converter relates to the location of the first riser of the transfer function and can be measured by grounding the V(−) input and applying a small magnitude positive voltage to the V(+) input. Zero error is the difference between the actual DC input voltage that is necessary to just cause an output digital code transition from 00 0000 0000 to 00 0000 0001 and the ideal ½ LSB value (½ LSB = 2.45 mV for VREF = 5.0 VDC). The zero of the A/D normally does not require adjustment. However, for cases where VIN(MIN) is not ground and in reduced span applications (VREF < 5V), an offset adjustment may be desired. The converter can be made to output an all zero digital code for an arbitrary input by biasing the A/D's VIN(−) input at that voltage. This utilizes the differential input operation of the A/D. where fCM is the frequency of the common-mode signal, VPEAK is its peak voltage value and fCLK is the clock frequency at the CLK IN pin. For a 60 Hz common-mode signal to generate a ¼ LSB error (1.2 mV) with the converter running at 1.8 MHz, its peak value would have to be 1.46V. A common-mode signal this large is much greater than that generally found in data acquisition systems. 3.2 Input Current Due to the sampling nature of the analog inputs, short duration spikes of current enter the “+” input and exit the “−” input at the clock rising edges during the conversion. These currents decay rapidly and do not cause errors as the internal comparator is strobed at the end of a clock period. 4.2 Full Scale The full-scale adjustment can be made by applying a differential input voltage that is 1½ LSB down from the desired analog full-scale voltage range and then adjusting the magnitude of the VREF input for a digital output code that is just changing from 11 1111 1110 to 11 1111 1111. 3.3 Input Bypass Capacitors Bypass capacitors at the inputs will average the current spikes noted in 3.2 and cause a DC current to flow through the output resistances of the analog signal sources. This charge pumping action is worse for continuous conversions with the VIN(+) input voltage at full scale. For continuous conversions with a 1.8 MHz clock frequency with the VIN(+) input at 5V, this DC current is at a maximum of approximately 5 μA. Therefore, bypass capacitors should not be used at the analog inputs or the VREF pin for high resistance sources (>1 kΩ). If input bypass capacitors are necessary for noise filtering and high source resistance is desirable to minimize capacitor size, the detrimental effects of the voltage drop across this input resistance, which is due to the average value of the input current, can be eliminated with a full-scale adjustment while the given source resistor and input bypass capacitor are both in place. This is possible because the average value of the input current is a linear function of the differential input voltage. 4.3 Adjusting for an Arbitrary Analog Input Voltage Range If the analog zero voltage of the A/D is shifted away from ground (for example, to accommodate an analog input signal that does not go to ground), this new zero reference should be properly adjusted first. A VIN(+) voltage that equals this desired zero reference plus ½ LSB (where the LSB is calculated for the desired analog span, 1 LSB = analog span/1024) is applied to selected “+” input and the zero reference voltage at the corresponding “−” input should then be adjusted to just obtain the 000HEX 001HEX code transition. The full-scale adjustment should be made [with the proper VIN(−) voltage applied] by forcing a voltage to the VIN(+) input given by: 3.4 Input Source Resistance Large values of source resistance where an input bypass capacitor is not used, will not cause errors if the input currents settle out prior to the comparison time. If a low pass filter is required in the system, use a low valued series resistor (≤1 kΩ) for a passive RC section or add an op amp RC active low pass filter. For low source resistance applications (≤0.1 kΩ) a 4700 pF bypass capacitor at the inputs will prevent pickup due to series lead induction of a long wire. A 100Ω series resistor can be used to isolate this capacitor – both the R and the C are placed outside the feedback loop – from the output of an op amp, if used. where VMAX = the high end of the analog input range and VMIN = the low end (the offset zero) of the analog range. (Both are ground referenced). The VREF (or VCC) voltage is then adjusted to provide a code change from 3FFHEX to 3FEHEX. This completes the adjustment procedure. For an example see the Zero-Shift and Span-Adjust circuit below. www.national.com 10 5261 Version 8 Revision 2 Print Date/Time: 2009/08/26 22:47:16 526116 FIGURE 5. Zero-Shift and Span-Adjust (2V ≤ VIN ≤ 5V) 11 5261 Version 8 Revision 2 Print Date/Time: 2009/08/26 22:47:16 www.national.com ADC1005 A single point analog ground that is separate from the logic ground points should be used. The power supply bypass capacitor and the self-clocking capacitor (if used) should both be returned to the digital ground. Any VREF bypass capacitors, analog input filters capacitors, or input signal shielding should be returned to the analog ground point. 5.0 POWER SUPPLIES Noise spikes on the VCC supply line can cause conversion errors as the comparator will respond to this noise. A low inductance tantalum filter capacitor should be used close to the converter VCC pin and values of 1 μF or greater are recommended. If an unregulated voltage is available in the system, a separate LM340LAZ-5.0, TO-92, 5V voltage regulator for the converter (and the other analog circuitry) will greatly reduce digital noise on the VCC supply. ADC1005 Typical Applications 526113 Operating with Ratiometric Transducers 526114 VIN(−) = 0.15 VCC 15% of VCC ≤ VXDR ≤ 85% of VCC Handling ±5V Analog Inputs 526115 www.national.com 12 5261 Version 8 Revision 2 Print Date/Time: 2009/08/26 22:47:16 ADC1005 TRI-STATE Test Circuits and Waveforms t1H tIH, CL=10 pF 526107 526109 tr=20 ns t0H tIH, CL=10 pF 526110 526108 tr=20 ns 13 5261 Version 8 Revision 2 Print Date/Time: 2009/08/26 22:47:16 www.national.com ADC1005 Physical Dimensions inches (millimeters) unless otherwise noted Hermetic Dual-In-Line Package (J) Order Number ADC1005BCJ, ADC1005BCJ-1 or ADC1005CCJ-1 NS Package Number J20A www.national.com 14 5261 Version 8 Revision 2 Print Date/Time: 2009/08/26 22:47:16 ADC1005 Notes 15 5261 Version 8 Revision 2 Print Date/Time: 2009/08/26 22:47:16 www.national.com ADC1005 10-Bit μP Compatible A/D Converter Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage Reference www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Solutions www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise® Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic Wireless (PLL/VCO) www.national.com/wireless www.national.com/training PowerWise® Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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