STA516B 65-volt, 7.5-amp, quad power half bridge Features ! Low input/output pulse-width distortion ! 200 mΩ RdsON complementary DMOS output stage ! CMOS-compatible logic inputs ! Thermal protection ! Thermal warning output ! Undervoltage protection PowerSO36 package with exposed pad up Description STA516B is a monolithic quad half-bridge stage in Multipower BCD Technology. The device can be used as dual bridge or reconfigured, by connecting pin CONFIG to pins VDD, as a single bridge with double-current capability or as a half bridge (binary mode) with half-current capability. The device is intended for the output stage of a stereo all-digital high-efficiency amplifier. It is capable of delivering 200 W + 200 W into 6-Ω loads with THD = 10% at VCC = 51 V or, in single BTL configuration, 400 W into a 3-Ω load with THD = 10% at VCC = 52 V. Table 1. The input pins have a threshold proportional to the voltage on pin VL. The STA516B is aimed at audio amplifiers in Hi-Fi applications, such as home theatre systems, active speakers and docking stations. It comes in a 36-pin PowerSO package with exposed pad up (EPU). Device summary Order code Temperature range Package Packaging STA516B 0 to 90 °C PowerSO36 EPU Tube STA516B13TR 0 to 90 °C PowerSO36 EPU Tape and reel November 2010 Doc ID 13183 Rev 4 1/17 www.st.com 17 Introduction 1 STA516B Introduction The STA516B is a high performance quad half-bridge amplifier with the capability to drive up to 220 W (a) stereo into 3- to 8-ohm speakers from a single 50 V supply. It offers the highest flexibility since it can be configured as a stereo-BTL, as a mono-BTL or as four channels of single-ended outputs to fit different application requirements. It provides remarkably high levels of efficiency when driven by the FFX-patented 3-state pulse-width modulator embedded in STMs digital audio processors . The device is self-protected by design. Overcurrent, overtemperature, under- and overvoltage protection are provided with an automatic recovery feature to safeguard the device and speakers against fault conditions that could damage the overall system. a. The achievable output power depends on the thermal configuration of the final application. A high performance thermal interface material between the package exposed pad and the heat sink should be used in order to maximize output power levels 2/17 Doc ID 13183 Rev 4 STA516B 2 Pin description Pin description Figure 1. Pin out VCC_SIGN VCC_SIGN VSS VSS IN2B IN2A IN1B IN1A TH_WARN FAULT TRISTATE PWRDN CONFIG VL VDD VDD GND_REG GND_CLEAN Table 2. 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 STA516B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SUB_GND OUT2B OUT2B VCC2B GND2B GND2A VCC2A OUT2A OUT2A OUT1B OUT1B VCC1B GND1B GND1A VCC1A OUT1A OUT1A N.C. Pin function Pin Name Type Description 1 GND_SUB PWR Substrate ground 2, 3 OUT2B O Output half bridge 2B 4 VCC2B PWR Positive supply 5 GND2B PWR Negative supply 6 GND2A PWR Negative supply 7 VCC2A PWR Positive supply 8, 9 OUT2A O Output half bridge 2A 10, 11 OUT1B O Output half bridge 1B 12 VCC1B PWR Positive supply 13 GND1B PWR Negative supply 14 GND1A PWR Negative supply 15 VCC1A PWR Positive supply 16, 17 OUT1A O Output half bridge 1A 18 N.C. - No internal connection 19 GND_CLEAN PWR Logical ground 20 GND_REG PWR Ground for regulator VDD 21, 22 VDD PWR 5-V regulator referred to ground 23 VL PWR High logical state setting voltage, VL Doc ID 13183 Rev 4 3/17 Pin description Table 2. STA516B Pin function (continued) Pin 4/17 Name Type Description 24 CONFIG I Configuration pin: 0: normal operation 1: bridges in parallel (OUT1A = OUT1B, OUT2A = OUT2B (If IN1A = IN1B, IN2A = IN2B)) 25 PWRDN I Standby pin: 0: low-power mode 1: normal operation 26 TRISTATE I Hi-Z pin: 0: all power amplifier outputs in high impedance state 1: normal operation 27 FAULT O Fault pin advisor (open-drain device, needs pull-up resistor): 0: fault detected (short circuit or thermal, for example) 1: normal operation 28 TH_WARN O Thermal warning advisor (open-drain device, needs pull-up resistor): 0: temperature of the IC >130 °C 1: normal operation 29 IN1A I Input of half bridge 1A 30 IN1B I Input of half bridge 1B 31 IN2A I Input of half bridge 2A 32 IN2B I Input of half bridge 2B 33, 34 VSS PWR 5-V regulator referred to +VCC 35, 36 VCC_SIGN PWR Signal positive supply Doc ID 13183 Rev 4 STA516B 3 Electrical specifications Electrical specifications Table 3. Absolute maximum ratings Symbol Parameter Value Unit VCC_MAX DC supply voltage (pins 4, 7, 12, 15) 65 V Vmax Maximum voltage on pins 23 to 32 5.5 V Tj_MAX Operating junction temperature 0 to 150 °C Tstg Storage temperature -40 to 150 °C Warning: Table 4. Symbol Stresses beyond those listed under “Absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended operating condition” are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. In the real application, power supplies with nominal values rated within the recommended operating conditions, may experience some rising beyond the maximum operating conditions for a short time when no or very low current is being drawn (amplifier in mute state, for instance). In this case the reliability of the device is guaranteed, provided that the absolute maximum rating is not exceeded. Thermal data Parameter Min Typ Max Unit Tj-case Thermal resistance junction to case (thermal pad) - 1 2.5 °C/W Twarn Thermal warning temperature - 130 - °C TjSD Thermal shut-down junction temperature - 150 - °C thSD Thermal shut-down hysteresis - 25 - °C Table 5. Symbol Recommended operating conditions Parameter Min Typ Max Unit VCC Supply voltage for pins PVCCA, PVCCB 10 - 58 V Tamb Ambient operating temperature 0 - 90 °C Doc ID 13183 Rev 4 5/17 Electrical specifications STA516B Unless otherwise stated, the test conditions for Table 6 below are VL = 3.3 V, VCC = 50 V and Tamb = 25 °C Table 6. Electrical characteristics Symbol Test conditions Min Typ Max Unit RdsON Power P-channel/N-channel MOSFET RdsON Idd = 1 A - 200 240 mΩ Idss Power P-channel/N-channel leakage Idss - - - 50 µA gN Power P-channel RdsON matching Idd = 1 A 95 - - % gP Power N-channel RdsON matching Idd = 1 A 95 - - % Dt_s Low current dead time (static) see Figure 2 - 10 20 ns Dt_d High current dead time (dynamic) L = 22 µH, C = 470 nF RL = 8 Ω, Idd = 4.5 A see Figure 3 - 50 ns td ON Turn-on delay time Resistive load - - 100 ns td OFF Turn-off delay time Resistive load - - 100 ns tr Rise time Resistive load see Figure 2 - - 25 ns tf Fall time Resistive load see Figure 2 - - 25 ns VIN-High High level input voltage - - - VL / 2 + V 300 mV VIN-Low Low level input voltage - VL / 2 300 mV - V IIN-H High level input current VIN = VL - 1 - µA IIN-L Low level input current VIN = 0.3 V - 1 - µA IPWRDN-H High level PWRDN pin input current VL = 3.3 V - 35 - µA VLow Low logical state voltage (pins PWRDN, TRISTATE) (seeTable 7) VL = 3.3 V 0.8 - VHigh High logical state voltage (pins PWRDN, TRISTATE) (seeTable 7) VL = 3.3 V Supply current from VCC in power down VPWRDN = 0 V IFAULT Output current on pins FAULT, TH_WARN with fault condition IVCC-HiZ Supply current from VCC in 3-state IVCCPWRDN 6/17 Parameter V - 1.7 V - - 2.4 mA Vpin = 3.3 V - 1 - mA VTRISTATE = 0 V - 22 - mA Doc ID 13183 Rev 4 STA516B Electrical specifications Table 6. Electrical characteristics (continued) Symbol Parameter Test conditions Min Typ Max Unit IVCC Supply current from VCC in operation, both channels switching) Input pulse width = 50% duty, switching frequency = 384 kHz, no LC filters IOCP Overcurrent protection threshold Isc (short-circuit current limit) (1) - 7.5 8.5 10 A VUVP Undervoltage protection threshold - - 7 - V VOVP Overvoltage protection threshold - 61 62.5 tpw_min Output minimum pulse width No load 50 - - 70 - mA V 110 ns 1. See application note AN1994 Table 7. Threshold switching voltage variation with voltage on pin VL Voltage on pin VL, VL VLOW max VHIGH min Unit 2.7 1.05 1.65 V 3.3 1.4 1.95 V 5.0 2.2 2.8 V Table 8. Pin TRISTATE Logic truth table Inputs as per Figure 3 Transistors as per Figure 3 Output mode INxA INxB Q1 Q2 Q3 Q4 0 x x Off Off Off Off Hi Z 1 0 0 Off Off On On Dump 1 0 1 Off On On Off Negative 1 1 0 On Off Off On Positive 1 1 1 On On Off Off Not used Doc ID 13183 Rev 4 7/17 Electrical specifications 3.1 STA516B Test circuits Figure 2. Test circuit OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t DTr Duty cycle = 50% DTf M58 OUTxY INxY R 8Ω M57 V67 = vdc = Vcc/2 + - gnd Figure 3. D03AU1458 Current dead-time test circuit High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B DTout(A) M58 DTin(A) Q1 Q2 INxA Iout=4.5A M57 Q3 DTout(B) Rload=8Ω OUTxA L67 22µ C69 470nF L68 22µ C71 470nF C70 470nF Doc ID 13183 Rev 4 DTin(B) INxB Iout=4.5A Q4 Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure 8/17 M64 OUTxB M63 D00AU1162 STA516B 4 Power supply and control sequencing Power supply and control sequencing To guarantee correct operation and reliability, the recommended power-on/off sequence as shown in Figure 4 should be followed Figure 4. Suggested power-on/off sequence V Vcc VL Vcc > VL t PWRDN t IN t VCC should be turned on before VL. This prevents uncontrolled current flowing through the internal protection diode connected between VL (logic supply) and VCC (high power supply). which could result in damage to the device. PWRDN must be released after VL is switched on. An input signal can then be sent to the power stage. Doc ID 13183 Rev 4 9/17 Applications information 5 STA516B Applications information The STA516B is a dual channel H-bridge that is able to deliver 200 W per channel (into RL = 6 Ω with THD = 10% and VCC = 51V) of audio output power very efficiently. It operates in conjunction with a pulse-width modulator driver such as the STA321 or STA309A. The STA516B converts ternary, phase-shift or binary-controlled PWM signals into audio power at the load. It includes a logic interface, integrated bridge drivers, high efficiency MOSFET outputs and thermal and short-circuit protection circuitry. In differential mode (ternary, phase-shift or binary differential), two logic level signals per channel are used to control high-speed MOSFET switches to connect the speaker load to the input supply or to ground in a bridge configuration, according to the damped ternary modulation operation. In binary mode, both full bridge and half bridge modes are supported. The STA516B includes overcurrent and thermal protection as well as an undervoltage lockout with automatic recovery. A thermal warning status is also provided. Figure 5. Block diagram of full-bridge FFX® or binary mode INL[1,2] INR[1,2] VL PWRDN TRISTATE FAULT Logic interface and decode Protection THWARN OUTPL Left H-bridge Right H-bridge OUTNL OUTPR OUTNR Regulators Figure 6. Block diagram of binary half-bridge mode INL[1,2] INR[1,2] VL PWRDN TRISTATE FAULT Logic interface and decode LeftA ½-bridge OUTPL LeftB ½-bridge OUTNL Protection RightA ½-bridge OUTPR RightB ½-bridge OUTNR THWARN Regulators 5.1 Logic interface and decode The STA516B power outputs are controlled using one or two logic-level timing signals. In order to provide a proper logic interface, the VL input must operate at the same voltage as the FFX® control logic supply. 10/17 Doc ID 13183 Rev 4 STA516B 5.2 Applications information Protection circuitry The STA516B includes protection circuitry for overcurrent and thermal overload conditions. A thermal warning pin (THWARN, pin 28, open drain MOSFET) is activated low when the IC temperature exceeds 130 °C, just in advance of thermal shutdown. When a fault condition is detected an internal fault signal immediately disables the output power MOSFETs, placing both H-bridges in a high-impedance state. At the same time the open-drain MOSFET of pin FAULT (pin 27) is switched on. There are two possible modes subsequent to activating a fault. 5.3 " Shutdown mode: with pins FAULT (with pull-up resistor) and TRISTATE separate, an activated fault disables the device, signalling a low at pin FAULT output. The device may subsequently be reset to normal operation by toggling pin TRISTATE from high to low to high using an external logic signal. " Automatic recovery mode: This is shown in the applications circuits below where pins FAULT and TRISTATE are connected together to a time-constant circuit (R59 and C58). An activated fault forces a reset on pin TRISTATE causing normal operation to resume following a delay determined by the time constant of the circuit. If the fault condition persists, the circuit operation repeats until the fault condition is cleared. An increase in the time constant of the circuit produces a longer recovery interval. Care must be taken in the overall system design not to exceed the protection thresholds under normal operation. Power outputs The STA516B power and output pins are duplicated to provide a low-impedance path for the device bridged outputs. All duplicate power, ground and output pins must be connected for proper operation. The PWRDN or TRISTATE pin should be used to set all power MOSFETs to the high-impedance state during power-up until the logic power supply, VL, has settled. 5.4 Parallel output / high current operation When using the FFX® mode output, the STA516B outputs can be connected in parallel to increase the output current capability to the load. In this configuration the STA516B can provide up to 400 W into a 3-Ω load. This mode of operation is enabled with pin CONFIG (pin 24) connected to pin VDD. The inputs are joined so that IN1A = IN1B, IN2A = IN2B and similarly the outputs OUT1A = OUT1B, OUT2A = OUT2B as shown in Figure 8. 5.5 Output filtering A passive 2nd-order filter is used on the STA516B power outputs to reconstruct the analog audio signal. System performance can be significantly affected by the output filter design and choice of passive components. Filter designs for 3- and 6-Ω loads are shown in the applications circuits of Figure 7, Figure 8 and Figure 9. Doc ID 13183 Rev 4 11/17 Applications information 5.6 STA516B Applications circuits Figure 7. Typical stereo-BTL configuration for 200 W per channel +VCC VCC1A IN1A 29 VL 23 CONFIG 24 PWRDN 25 FAULT 27 M3 IN1A +3.3V PWRDN R57 10K R59 10K 16 M2 PROTECTIONS & LOGIC TRI-STATE TH_WAR M5 TH_WAR 28 IN1B 30 VDD 21 VDD 22 VSS 33 VSS 34 14 GND1A 12 VCC1B REGULATORS 13 GND1B 7 VCC2A VCCSIGN C32 1µF C60 100nF VCCSIGN IN2A IN2A GND-Reg GND-Clean IN2B IN2B GNDSUB 8 35 9 36 M15 31 20 19 M16 4 VCC2B 2 32 C33 1µF 3 5 R104 20 R102 6 C107 100nF C108 470nF C106 100nF 6Ω 8Ω C111 100nF OUT2B OUT2B M14 1 68Ω Ω C21 100nF C110 100nF C109 330pF R103 6 OUT2A GND2A R100 6 C99 100nF C23 470nF C101 100nF L113 22µH OUT2A 6 R98 6 L19 22µH OUT1B M4 R63 20 OUT1B M17 C53 100nF C20 100nF C52 330pF C31 1µF 11 C55 1000µF L18 22µH OUT1A OUT1A 10 IN1B C58 100nF C30 1µF 17 26 C58 100nF 15 L112 22µH GND2B D00AU1148B Figure 8 below shows a single-BLT configuration capable of giving 400 W into a 3-Ω load at 10% THD with VCC = 52 V. This result was obtained using the STA30X+STA50X demo board. Note that a PWM modulator as driver is required. Figure 8. Typical single-BTL configuration for 400 W VL +3.3V GND-Clean GND-Reg 10K 23 18 N.C. 12µH 100nF 100nF X7R VDD VDD CONFIG TH_WAR TH_WAR PWRDN nPWRDN 10K FAULT IN1A IN1B IN1A IN2A IN2B IN1B VSS VSS 100nF X7R 20 21 22 24 28 25 27 TRI-STATE 100nF 19 VCCSIGN 100nF X7R VCCSIGN Add. GNDSUB 26 29 17 16 11 10 OUT1B OUT2A 8 34 22Ω 1/2W 6.2 1/2W 330pF 6.2 1/2W OUT2B 3 15 12 7 4 12µH VCC1A VCC1B VCC +36V 1µF X7R VCC2A VCC2B GND1A 14 13 GND2A 36 6 1 5 GND2B D04AU1545 12/17 Doc ID 13183 Rev 4 2200µF 63V VCC +36V 1µF X7R GND1B 35 100nF X7R 680nF FILM 100nF X7R 100nF FILM OUT2B 2 32 33 100nF FILM OUT1A OUT1B OUT2A 9 30 31 OUT1A 3Ω 4Ω STA516B Applications information Figure 9. Typical quad half-bridge configuration for 100 W per channel +VCC VCC1P IN1A 29 M3 IN1A +3.3V PWRDN R57 10K R59 10K C58 100nF TH_WAR VL 23 CONFIG 24 PWRDN 25 FAULT 27 26 16 M2 PROTECTIONS & LOGIC M5 28 IN1B 30 VDD 21 VDD 22 VSS 33 C53 100nF VSS 34 C60 100nF IN2A GND-Reg GND-Clean IN2B PGND1P 12 VCC1N C51 1µF REGULATORS 13 7 PGND1N VCC2P C71 100nF R51 6 C81 100nF C61 100nF OUTNL OUTNL M4 R41 20 C41 330pF C42 330pF C72 100nF R52 6 C82 100nF IN2B GNDSUB 9 36 M15 31 20 19 M16 1 OUTPR 6 PGND2P 4 VCC2N 3 2 32 OUTPR C52 1µF 5 C43 330pF PGND2N D03AU1474 C73 100nF R53 6 C83 100nF C62 100nF OUTNR OUTNR M14 R43 20 C44 330pF R66 5K R67 5K L14 22µH R44 20 R64 5K R65 5K L13 22µH 8 35 R62 5K R63 5K L12 22µH R42 20 M17 VCCSIGN VCCSIGN IN2A OUTPL 10 IN1B C58 100nF OUTPL 14 11 R61 5K L11 22µH 17 TRI-STATE TH_WAR 15 C74 100nF R54 6 C84 100nF R68 5K C21 2200µF C31 820µF C91 1µF 4Ω 3Ω C32 820µF C92 1µF 4Ω 3 Ω C33 820µF C93 1µF 3Ω 4Ω C34 820µF C94 1µF 3Ω 4Ω For more information, refer to the applications note AN1994. Doc ID 13183 Rev 4 13/17 6 14/17 Figure 10. PowerSO36 exposed pad up outline drawing Package mechanical data Package mechanical data STA516B Doc ID 13183 Rev 4 STA516B Package mechanical data Table 9. PowerSO36 exposed pad up dimensions Dimensions in mm Dimensions in inch Symbol Min Typ Max Min Typ Max A 3.25 - 3.43 0.128 - 0.135 A2 3.10 - 3.20 0.122 - 0.126 A4 0.80 - 1.00 0.031 - 0.039 A5 - 0.20 - - 0.008 - a1 0.03 - -0.04 0.001 - -0.002 b 0.22 - 0.38 0.009 - 0.015 c 0.23 - 0.32 0.009 - 0.013 D 15.80 - 16.00 0.622 - 0.630 D1 9.40 - 9.80 0.370 - 0.386 D2 - 1.00 - - 0.039 - E 13.90 - 14.50 0.547 - 0.571 E1 10.90 - 11.10 0.429 - 0.437 E2 - - 2.90 - - 0.114 E3 5.80 - 6.20 0.228 - 0.244 E4 2.90 - 3.20 0.114 - 0.126 e - 0.65 - - 0.026 - e3 - 11.05 - - 0.435 - G 0 - 0.08 0 - 0.003 H 15.50 - 15.90 0.610 - 0.626 h - - 1.10 - - 0.043 L 0.80 - 1.10 0.031 - 0.043 M 2.25 - 2.60 0.089 - 0.102 N - - 10 degrees - - 10 degrees R - 0.6 - - 0.024 - s - - 8 degrees - - 8 degrees In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Doc ID 13183 Rev 4 15/17 Revision history 7 STA516B Revision history Table 10. 16/17 Document revision history Date Revision Changes 01-Feb-2007 1 Initial release. 19-Mar-2007 2 Update to reflect product maturity 11-Aug-2009 3 Updated section Description on cover page. 16-Nov-2010 4 Modified presentation Updated Chapter 3: Electrical specifications on page 5 Added Chapter 5: Applications information on page 10 Doc ID 13183 Rev 4 STA516B Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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