STA533WF 18-volt, 3-amp, quad power half-bridge Features ■ Multipower BCD technology ■ Low input/output pulse width distortion ■ 200-mΩ RdsON complementary DMOS output stage ■ CMOS-compatible logic inputs ■ Thermal protection ■ Thermal warning output ■ Undervoltage protection ■ Short-circuit protection PowerSSO36 package with exposed pad down loads with 10% THD at VCC = 18 V in single-ended configuration. Description The STA533WF is a monolithic quad half-bridge stage in multipower BCD technology. The device can be used as a dual bridge or reconfigured, by connecting pin CONFIG to pins VDD, as a single bridge with double-current capability. The device is designed for the output stage of a stereo Full Flexible Amplifier (FFX™). It is capable of delivering 10 W x 4 channels into 4-Ω Table 1. It can also deliver 20 W + 20 W into 8-Ω loads with 10% THD at VCC = 18 V in BTL configuration or, in single parallel BTL configuration, 40 W into a 4-Ω load with 10% THD at VCC = 18 V. The input pins have a threshold proportional to the voltage on pin VL. The STA533WF comes in a 36-pin PowerSSO package with exposed pad down (EPD). Device summary Order code Temperature range Package Packaging STA533WF 0 to 70 °C PowerSSO36 EPD Tube STA533WF13TR 0 to 70 °C PowerSSO36 EPD Tape and reel June 2011 Doc ID 17658 Rev 2 1/15 www.st.com 15 Pin description 1 STA533WF Pin description Figure 1. Pin out GNDSUB OUT2B OUT2B VCC2B GND2B GND2A VCC2A OUT2A OUT2A OUT1B OUT1B VCC1B GND1B GND1A VCC1A OUT1A OUT1A N.C. Table 2. STA533WF 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VCCSIG VCCSIG VSS VSS IN2B IN2A IN1B IN1A THWARN FAULT TRISTATE PWRDN CONFIG VL VDD VDD GNDREG GNDCLEAN Pin list Pin 2/15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Name Type Description 1 GNDSUB PWR Substrate ground 2, 3 OUT2B O Output half-bridge 2B 4 VCC2B PWR Positive supply 5 GND2B PWR Negative supply 6 GND2A PWR Negative supply 7 VCC2A PWR Positive supply 8, 9 OUT2A O Output half-bridge 2A 10, 11 OUT1B O Output half-bridge 1B 12 VCC1B PWR Positive supply 13 GND1B PWR Negative supply 14 GND1A PWR Negative supply 15 VCC1A PWR Positive supply 16, 17 OUT1A O Output half-bridge 1A 18 N.C. - No internal connection 19 GNDCLEAN PWR Logical ground 20 GNDREG PWR Filtering for regulator; this is an internally generated ground for VDD 21, 22 VDD PWR 5-V regulator referred to ground 23 VL PWR High logical state setting voltage, VL Doc ID 17658 Rev 2 STA533WF Pin description Table 2. Pin Pin list (continued) Name Type Description 24 CONFIG I Configuration pin: 0: normal operation 1: bridges in parallel, see Parallel-output and high-current operation on page 8 25 PWRDN I Stand-by pin: 0: low-power mode 1: normal operation 26 TRISTATE I Hi-Z pin: 0: all power amplifier outputs in high-impedance state 1: normal operation 27 FAULT O Fault pin advisor (open-drain device, needs pull-up resistor): 0: fault detected (short circuit or thermal, for example) 1: normal operation 28 THWARN O Thermal-warning advisor (open-drain device, needs pull-up resistor): 0: temperature of the IC >130 oC 1: normal operation 29 IN1A I Input of half-bridge 1A 30 IN1B I Input of half-bridge 1B 31 IN2A I Input of half-bridge 2A 32 IN2B I Input of half-bridge 2B 33, 34 VSS PWR 5-V regulator referred to +VCC 35, 36 VCCSIG PWR Filtering for regulator, this is an internally generated supply for VSS Doc ID 17658 Rev 2 3/15 Electrical characteristics 2 STA533WF Electrical characteristics Table 3. Absolute maximum ratings Symbol Parameter Value Unit VCC DC supply voltage (Pins 4, 7, 12, 15) 23 V VLmax Voltage on pin 23 4.0 V Vinputs Voltage on pins 25, 26, 29 to 32 -0.3 to VL + 0.3 V Vconfig Voltage on pins 24 -0.3 to VDD + 0.3 V Tstg, Tj Storage and junction temperature -40 to 150 °C Table 4. Recommended operating conditions Symbol Parameter Min Typ Max Unit VCC DC supply voltage (Pins 4, 7, 12, 15) 5.0 - 18 V VL Input logic reference 2.7 3.3 3.6 V Tamb Ambient temperature 0 - 70 °C Table 5. Thermal data Symbol Parameter Min Typ Max Unit Tj-case Thermal resistance junction to case (thermal pad) - - 1.5 °C/W TjSD Thermal shut-down junction temperature - 150 - °C Twarn Thermal warning temperature - 130 - °C thSD Thermal shut-down hysteresis - 25 - °C Unless otherwise stated, the test conditions for Table 6 below are VL = 3.3 V, VCC = 18 V, RL = 8 Ω, fSW = 384 kHz and Tamb = 25 °C. Table 6. Symbol 4/15 Electrical characteristics Parameter Test conditions Min Typ Max Unit POUT Output power in BTL mode THD+N > 10% - 20 - W RdsON Power P-channel/N-channel MOSFET on resistance Idd = 1 A - 180 230 mΩ Idss Power P-channel/N-channel leakage - - - 10 μA gN Power P-channel RdsON matching Idd = 1 A 95 - - % gP Power N-channel RdsON matching Idd = 1 A 95 - - % Dt_s Low current dead time (static) see Figure 2 - 5 10 ns Doc ID 17658 Rev 2 STA533WF Electrical characteristics Table 6. Electrical characteristics (continued) Symbol Parameter Test conditions Min Typ Max Unit Dt_d High current dead time (dynamic) L = 22 μH, C = 470 nF RL = 8 Ω, Idd = 2.0 A see Figure 3 10 20 ns td_ON Turn-on delay time Resistive load - 40 60 ns td OFF Turn-off delay time Resistive load - 40 60 ns tr Rise time Resistive load see Figure 2 - 8 10 ns tf Fall time Resistive load see Figure 2 - 8 10 ns VIN-Low Half-bridge input, low-level voltage - - - VL / 2 V 300 mV VIN-High Half-bridge input, high-level voltage - VL / 2 + 300 mV - V IIN-H High-level input current VIN = VL - 1 - μA IIN-L Low-level input current VIN = 0.3 V - 1 - μA IPWRDN-H High level PWRDN pin input current VL = 3.3 V - 35 - μA VLow Low logical state voltage (pins PWRDN, TRISTATE) VL = 3.3 V - - 0.8 V VHigh High logical state voltage (pins PWRDN, TRISTATE) VL = 3.3 V 1.7 - - V Supply current from VCC in power down mode VPWRDN = 0 V - - 10 µA IFAULT Output current on pins FAULT, THWARN with fault condition Vpin = 3.3 V - 1 - mA IVCC-HiZ Supply current from VCC in 3-state VTRISTATE = 0 V - 22 - mA IVCC Supply current from VCC in operation (both channels switching) Input pulse width = 50% duty, switching frequency = 384 kHz, no LC filters - 50 - mA IOCP Overcurrent protection threshold (short-circuit current limit) - 3.0 4.0 - A VUVP Undervoltage protection threshold - - 3.5 4.3 V tpw_min Output minimum pulse width No load 70 - 150 ns IVCCPWRDN Doc ID 17658 Rev 2 5/15 Electrical characteristics Table 7. Pin PWRDN STA533WF Logic truth table Pin TRISTATE Inputs as per Figure 3 Transistors as per Figure 3 Output mode INxA INxB Q1 Q2 Q3 Q4 0 0 x x Off Off Off Off Hi Z 1 1 0 0 Off Off On On Dump 1 1 0 1 Off On On Off Negative 1 1 1 0 On Off Off On Positive 1 1 1 1 On On Off Off Not used Test circuits Figure 2. Test circuit OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t DTr Duty cycle = 50% OUTxY INxY DTf R 8Ω + - gnd Figure 3. vdc = Vcc/2 D03AU1458 Current dead time test circuit High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B DTout(A) Q2 Q1 DTin(A) INxA Iout Q3 DTout(B) Rload=8Ω OUTxA 22μ 470nF 22μ 470nF 470nF OUTxB Iout Q4 Duty cycle A and B: Fixed to have DC output current of Iout in the direction shown in figure 6/15 Doc ID 17658 Rev 2 DTin(B) INxB D00AU1162_00 STA533WF 3 Applications information Applications information The STA533WF is a dual-channel H-bridge audio power amplifier that can deliver 20 W per channel into 8 Ω with 10% THD at VCC = 18 V with high efficiency. The STA533WF converts both FFX and binary-logic-controlled PWM signals into audio power at the load. It includes a logic interface, integrated bridge drivers, high-efficiency MOSFET outputs and thermal and short-circuit protection circuitry. In FFX mode, two logic-level signals per channel are used to control the high-speed MOSFET switches which drive the speaker load in a bridge configuration, according to the damped ternary modulation operation. In binary mode, both full-bridge and half-bridge modes are supported. The STA533WF includes overcurrent and thermal protection as well as an undervoltage lockout with automatic recovery. A thermal warning status is also provided. Figure 4. Block diagram for FFX or binary modes INL[1,2] Logic interface and decode INR[1,2] VL PWRDN TRISTATE FAULT THWARN Protection circuit Left H-bridge OUTPL OUTNL Right H-bridge OUTPR OUTNR Regulators Figure 5. Block diagram for binary half-bridge mode INL[1,2] Logic interface and decode INR[1,2] VL PWRDN TRISTATE FAULT THWARN Protection circuit Left A bridge OUTPL Left B bridge OUTNL Right A bridge OUTPR Right B bridge OUTNR Regulators Logic interface and decode The STA533WF power outputs are controlled using one or two logic-level timing signals. In order to provide a proper logic interface, pin VL must have the same voltage as the PWM input signal. Doc ID 17658 Rev 2 7/15 Applications information STA533WF Protection circuits The STA533WF includes protection circuitry for overcurrent and thermal overload conditions. A thermal warning pin (THWARN) is activated low (open-drain MOSFET) when the IC temperature exceeds 130 °C, which is in advance of the thermal shutdown protection. When a fault condition is detected an internal fault signal acts to immediately disable the output power MOSFETs, placing both H-bridges in the high-impedance state. At the same time an open-drain MOSFET connected to pin FAULT is switched on. There are two possible modes subsequent to activating a fault: ● Shutdown mode: with pins FAULT (with pull-up resistor) and TRISTATE independent, an activated fault disables the device, signalling low at pin FAULT. The device may subsequently be reset to normal operation by toggling pin TRISTATE from high to low and back to high using an external logic signal. ● Automatic recovery mode: This is shown in the applications circuit in Figure 6 and Figure 7 on page 10. Pins FAULT and TRISTATE are shorted together and connected to a time constant circuit comprising R59 and C58. An activated fault forces a reset on pin TRISTATE causing normal operation to resume following a delay determined by the time constant of the circuit. If the fault condition is still present this operation continues to repeat until the fault condition is removed. An increase in the time constant of the circuit produces a longer recovery interval. Care must be taken in the overall system design so as not to exceed the protection thresholds under normal operation. Power outputs The STA533WF power and output pins are duplicated to provide a low-impedance path for the device bridged outputs. All duplicated power, ground and output pins must be connected for reliable operation. Pins PWRDN or TRISTATE should be used to set all MOSFETS to the high-impedance state during power-up and until the logic power supply on pin VL has settled. Parallel-output and high-current operation When using FFX mode, the STA533WF outputs can be connected in parallel to increase the output current capability. In this configuration the device can provide 40 W into 4 Ω. This mode of operation is enabled with pin CONFIG connected to VDD. The inputs must be combined to give INLA = INLB and INRA = INRB, then the corresponding outputs can be shorted together to give OUTLA = OUTLB and OUTRA = OUTRB. The snubber RC network shown in the applications figures must be placed as close as possible to the output pins. This reduces ringing, over- and undervoltage effects, and improves the audio quality and EMI performance. 8/15 Doc ID 17658 Rev 2 STA533WF Applications information Supply decoupling capacitors To meet the performance figures given in this datasheet the STA533WF power supply must be adequately filtered. For this purpose capacitors connected from pins VCC1 to GND1 and from VCC2 to GND2 must be placed as close as possible to the related IC pins. For reliability and optimum performance the following capacitors are suggested: ● 100-nF ceramic capacitor with lead length less than 2 mm, connected to the ground plane and as close as possible to the GND pin ● 1-uF X7R (low ESR) capacitors. Pin GNDREG is used to filter the internal reference voltage VDD; This pin must not be connected to other ground pins, it is an internally generated supply. Pin VCCSIG is used to filter the internal reference voltage VSS; This pin must not be connected to other supply pins, it is an internally generated supply. Output filter A passive 2nd-order filter is used on the STA533WF power outputs to reconstruct an analog audio signal. The system performance can be significantly affected by the output filter design and choice of passive components. Filter designs for 4-Ω and 8-Ω loads are shown in the applications circuits below. Applications circuits Figure 6 shows a typical full-bridge circuit for supplying 20 W + 20 W into 8-Ω speakers with 10% THD when VCC = 18 V. Figure 7 shows a single-BTL configuration capable of supplying 40 W into a 4-Ω load at 10% THD when VCC = 19 V. This result was obtained with peak power for <1 s using the STA309A + STA533WF demo board. For both applications circuits a PWM modulator is required as driver. Doc ID 17658 Rev 2 9/15 Applications circuit for stereo full-bridge configuration L3 22uH C20 100nF C38 U2 3V3 C22 100nF RIGHT_B RIGHT_A LEFT_B LEFT_A R8 10K TH W R10 EAPD C29 10k 3V3 100nF C30 C31 100nF 100nF 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VCCSIG GNDSUB VCCSIG OUT2B OUT2B VSS VSS VCC2B IN2B GND2B IN2A GND2A IN1B VCC2A IN1A OUT2A THWARN OUT2A FAULT OUT1B TRISTATE OUT1B PWRDN VCC1B CONFIG GND1B VL GND1A VDD VCC1A VDD OUT1A GNDREG OUT1A GNDCLEAN NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 STA533WF C23 100nF C25 1uF 25V R6 R7 22 6.2 C26 R9 C24 C35 470nF 1nF C32 Vcc 100nF C33 1uF 25V L4 22uH L5 22uH C43 100nF R12 22 6.2 C45 C39 C47 1nF 100nF R13 C44 C40 470nF 1nF C46 Doc ID 17658 Rev 2 6.2 330pF C42 J3 1 2 LEFT 8OHM C41 1nF 100nF 22uH RIGHT 8OHM 100nF R11 L6 1 2 1nF + 1000uF/25V J2 C37 100nF C28 C36 Figure 7. C27 6.2 330pF 1nF C21 100nF Applications information 10/15 Figure 6. 100nF Applications circuit for single-BTL configuration L1 U1 3V3 C2 100nF R1 10K INPUT_A INPUT_B TH W EAPD C12 3V3 100nF C13 100nF R5 10k C14 100nF 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VCCSIG GNDSUB VCCSIG OUT2B OUT2B VSS VSS VCC2B IN2B GND2B IN2A GND2A IN1B VCC2A IN1A OUT2A THWARN OUT2A FAULT OUT1B TRISTATE OUT1B PWRDN VCC1B CONFIG GND1B VL GND1A VDD VCC1A VDD OUT1A GNDREG OUT1A GNDCLEAN NC C18 C1 100nF C4 C3 680pF C6 220nF C5 1nF C7 R2 1uF 25V 220nF 3R3 C9 C8 R3 10 R4 C10 C15 100nF L2 10uH 1 2 OUT 4OHM 1uF 220nF C11 1nF J1 3R3 220nF C16 1nF Vcc C17 1uF 25V STA533WF C19 1000uF/25V + STA533WF 100nF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 10uH STA533WF 4 Heatsink requirements Heatsink requirements Using the STA533WF mounted on a double-layer PCB having 2 copper ground areas of 3 x 3 cm2 and with 16 via holes the junction to ambient thermal resistance is approximately 24 °C/W in natural air convection. Figure 8. Double-layer PCB with copper ground areas and 16 via holes With the dissipated power within the device depending primarily on the supply voltage, the load impedance and the output modulation level, the maximum estimated dissipated power, Pdmax, for the STA533WF is: 4 W for 2 x 20 W into 8 Ω at 18 V < 5 W for 2 x 10 W into 8 Ω + 1 x 20 W into 4 Ω at 18 V. The figure below shows the power derating curve for the PowerSSO36 EPD package on PCBs with copper areas of 2 x 2 cm2 and 3 x 3 cm2. Figure 9. Pd (W) Power derating curves for PCB used as heatsink 8 7 Copper Area 3x3 cm and via holes 6 5 TDA7491P STA533WF PSSO36 PowerSSO36 4 3 Copper Area 2x2 cm and via holes 2 1 0 0 20 40 60 80 100 120 140 160 Tamb ( °C) Doc ID 17658 Rev 2 11/15 Package mechanical data 5 STA533WF Package mechanical data The STA533WF comes in a 36-pin PowerSSO package with exposed pad down (EPD). Figure 10 below shows the package outline and Table 8 gives the dimensions. In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 8. PowerSSO36 EPD dimensions Dimensions in mm Dimensions in inches Symbol Min 12/15 Typ Max Min Typ Max A 2.15 - 2.47 0.085 - 0.097 A2 2.15 - 2.40 0.085 - 0.094 a1 0.00 - 0.10 0.000 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 D 10.10 - 10.50 0.398 - 0.413 E 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - F - 2.3 - - 0.091 - G - - 0.10 - - 0.004 H 10.10 - 10.50 0.398 - 0.413 h - - 0.40 - - 0.016 k 0 - 8 degrees 0 - 8 degrees L 0.60 - 1.00 0.024 - 0.039 M - 4.30 - - 0.169 - N - - 10 degrees - - 10 degrees O - 1.20 - - 0.047 - Q - 0.80 - - 0.031 - S - 2.90 - - 0.114 - T - 3.65 - - 0.144 - U - 1.00 - - 0.039 - X 4.10 - 4.70 0.161 - 0.185 Y 6.50 - 7.10 0.256 - 0.280 Doc ID 17658 Rev 2 STA533WF Figure 10. PowerSSO36 EPD outline drawing h x 45° Doc ID 17658 Rev 2 Package mechanical data 13/15 Revision history 6 STA533WF Revision history Table 9. 14/15 Document revision history Date Revision Changes 02-Jul-2010 1 Initial release. 22-Jun-2011 2 Updated Applications circuits on page 9 Doc ID 17658 Rev 2 STA533WF Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2011 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 17658 Rev 2 15/15