CGS701AV Commercial Low Skew PLL 1 to 8 CMOS Clock Driver CGS701ATV Industrial Low Skew PLL 1 to 8 CMOS Clock Driver General Description Features CGS701A is an off the shelf clock driver specifically designed for today’s high speed designs. It provides low skew outputs which are produced at different frequencies from three fixed input references. The XTALIN input pin is designed to be driven from a 25 MHz–40 MHz crystal oscillator. The PLL, using a charge pump and an internal loop filter, multiplies this input frequency to create a maximum output frequency of four times the input. The device includes a TRI-STATEÉ control pin to disable the outputs. This feature allows for low frequency functional testing and debugging. Also included, is an EXTSEL pin to allow testing the chip via an external source. The EXTSEL pin, once set to high, causes the External-ClockÐMUX to change its input from the output of the VCO and Counter to the external clock signal provided via SKWTST input pin. (continued) Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Connection Diagram Guaranteed: 400 ps pin-to-pin skew (tOSHL and tOSLH) on 1X outputs. PentiumÉ and PowerPCTM compatible g 300 ps propagation delay Output buffer of eight drivers for large fanout 25 MHz – 160 MHz output frequency range Outputs operating at 4X, 2X, 1X of the reference frequency for multifrequency bus applications Selectable output frequency Internal loop filter to reduce noise and jitter Separate analog and digital VCC and ground pins Low frequency test mode by disabling the PLL Implemented on National’s Core CMOS process Symmetric output current drive: a 30/b30 mA IOL/IOH Industrial temperature of b40§ C to a 85§ C 28-pin PLCC for optimum skew performance Guaranteed 2k volts ESD protection Pin Description PLCC Package Pin Assignment for PLCC TL/F/11920 – 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. PentiumÉ is a registered trademark of Intel Corporation. PowerPCTM is a trademark of International Business Machines Corporation. C1996 National Semiconductor Corporation TL/F/11920 Pin Name Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VCC FBK IN CLK4 VCC XTALIN GND FBK OUT VCC CLK1Ðl GND CLK1Ð2 TRI-STATE SKWTST CLK1Ð3 GND CLK1Ð4 VCC SKWSEL GNDA VCCA EXTSEL GND CLK1Ð5 VCC CLK1Ð0 CLK1SEL GND CLK2 Digital VCC Feedback Input Pin 4X Clock Output Digital VCC Crystal Oscillator Input Digital Ground Feedback Output Pin Digital VCC 1X Clock Output Digital Ground 1X Clock Output Output TRI-STATE Control Skew Testing Pin 1X Clock Output Digital Ground 1X Clock Output Digital VCC Skew Test Selector Pin Analog Ground Analog VCC External Clock MUX Selector Digital Ground 1X Clock Output Digital VCC 1X Clock Output CLK1 Multiplier Selector Digital Ground 2X Clock Output RRD-B30M106/Printed in U. S. A. http://www.national.com CGS701AV Commercial Low Skew PLL 1 to 8 CMOS Clock Driver CGS701ATV Industrial Low Skew PLL 1 to 8 CMOS Clock Driver December 1995 CGS701A In addition, another pin is added for increasing the test capability. SKWSEL pin allows testing of the counter’s output and skew of the output drivers by bypassing the VCO. In this test mode CLK4 frequency is the same as SKWTST input frequency, while CLK2 is 1/2 and CLK1 frequencies are 1/4 respectively (refer to the Truth Table). In addition CLK1SEL functionality is also true under this test condition. General Description (Continued) CLK1SEL pin changes the output frequency of the CLK1Ð0 thru CLK1Ð5 outputs. During normal operation, when CLK1SEL pin is high, these outputs are at the same frequency as the input crystal oscillator, while CLK2 and CLK4 outputs are at twice and four times the input frequency respectively. Once CLK1SEL pin is set to a low logic level, the CLK1 outputs will be at twice the input frequency, the same as the CLK2 output, with CLK4 output still being at four times the input frequency. Block Diagram TL/F/11920 – 2 http://www.national.com 2 CGS701A Truth Table Input Output CLK1 SEL EXT SEL EXT CLK SKW SEL SKW TST TRI-STATE CLK4 CLK2 *H L X L X H 4 x f in 2 x f in f in *L L X L X H 4 x f in 2 x f in 2 x f in X H É X X H É É É H L X H É H 1 x f tst (/2 x f tst (/4 x f tst CLK1 L L X H É H 1 x f tst (/2 x f tst (/2 x f tst X X X X X L Z Z Z *Steady state phase, frequency lock Typical Application TL/F/11920 – 3 3 http://www.national.com CGS701A Recommended Operating required, Conditions Absolute Maximum Ratings (Note A) If Military/Aerospace specified devices are please contact the National Semiconductor Sales Office/Distributors for availability and specifications. b 0.5V to a 7.0V Supply Voltage (VCC) Supply Voltage (VCC) DC Input Voltage Diode Current (IIK) b 20 mA V e b0.5V a 20 mA V e VCC a 0.5V b 0.5V to VCC a 0.5V DC Input Voltage (VI) DC Output Diode Current (IO) b 20 mA V e b0.5V a 20 mA V e VCC a 0.5V b 0.5V to VCC a 0.5V DC Output Voltage (VO) DC Output Source g 60 mA or Sink Current (IO) DC VCC or Ground Current g 60 mA per Output Pin (ICC or IGND) b 65§ C to a 150§ C Storage Temperature (TSTG) Junction Temperature 150§ C Power Dissipation (Static and Dynamic) (Note B) 4.5V to 5.5V Input Voltage (VI) 0V to VCC Output Voltage (VO) 0V to VCC Input Frequency 25 MHz – 40 MHz Operating Temperature (TA) SKWTST 0§ C to a 70§ C External Clock Frequency (Pin) 1 MHz – 10 MHz XTALIN Duty Cycle Range 25/75 (75/25)% Input Rise and Fall Times (0.8V to 2.0V) XTALIN (Pin 5) 5 ns max All Other Inputs 10 ns max Typical iJA LFM § C/W 0 54 225 45 500 38 900 34 1400 mW Note A: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the DC and AC Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions will define the conditions for actual device operation. Note B: Power dissipation is calculated using 49§ C/W as the thermal coefficient for the PCC package at 225 LFM airflow. The input frequency is assumed at 33 MHz with CLK4 at 132 MHz and CLK2 and CLK1 being at 66 MHz. In addition, the ambient temperature is assumed 70§ C. DC Electrical Characteristics Over recommended operating free air temperature range. All typical values are measured at VCC e 5V, TA e 25§ C. Symbol VCC e 4.5V – 5.5V T e 0§ C to 70§ C Parameter Min VIH Minimum Input High Level Voltage VIL Maximum Input Low Level Voltage VOH Minimum Output High Level Voltage VOL Maximum Output Low Level Voltage Typ Units Conditions Max 2.0 V 0.8 VCC b 0.1 V V VCC b 0.6 IOUT e b50 mA IOH e b30 mA 0.1 V IOUT e 50 mA IOL e 30 mA 0.6 IOHD High Level Output Current b 50 b 110 b 170 mA VOH e VCC b 1.0V IOLD Low Level Output Current 50 110 170 mA VOL e 1.0V IIN Leakage Current 50 mA VIN e 0.4V or 4.6V IOZL/H Output Leakage Current CIN Input Capacitance 10.0 pF ICC Quiescent digital a analog b 50 3.0 Current (No Load) ICCT ICC per TTL Input http://www.national.com 5.0 2.5 4 VIN e VCC, GND mA VIN e VCC b 2.1, GND CGS701A AC Electrical Characteristics Over recommended operating free air temperature range. All typical values are measured at VCC e 5V, TA e 25§ C. Symbol VCC e 4.5V – 5.5V FIN e 25 to 40 MHz T e 0§ C to a 70§ C CL e Circuit 1 RL e Circuit 1 Parameter Min trise tfall tSKEW Output Rise Output Fall 0.8V to 2.6V 1.0V to VCC b 1.0V 1.0V to VCC b 1.0V 2.0 All 0.8V to 2.0V 1.5 CLK4 CLK2 CLK1 2.6V to 0.8V VCC b 1.0V to 1.0V VCC b 1.0V to 1.0V 2.0 All 0.8V to 2.0V Maximum Edge-toEdge Output Skew a to a Edges a to a Edges a to a Edges Notes Max CLK4 CLK2 CLK1 (Note 1, 7) ns (Note 1, 7) ns 1.5 CLK1ÐCLK1 CLK1ÐCLK4 CLK2ÐCLK4 tLOCK Time to Lock the Output to the Synch Input tCYCLE Output Duty Cycle JLT Typ Units 20 CLK1 Outputs CLK2 Output CLK4 Output 400 1000 1000 ps (Note 2, 7) 100 ms 49 49 35 51 51 65 % 0.3 ns (Note 4, 7) b 0.3 a 0.3 ns (Notes 2, 4, 5, 6, 7) Output Jitter (Long Term) (Note 3, 7) tPD Propogation Delay from XTALIN to FBKOUT FMIN Minimum XTALIN Frequency 15 MHz FMAX Maximum XTALIN Frequency 43 MHz Note 1: trise and tfall parameters are measured at the pin of the device. Note 2: Skew is measured at 50% of VCC for CLK1 and CLK2 while it is being measured at 1.4V for CLK4. Limits are guaranteed by design. Note 3: Output duty cycle is measured at VDD/2 for CLK1 and CLK2 while it is being measured at 1.4V for CLK4. Limits are guaranteed by design. Note 4: Jitter parameter is characterized and is guaranteed by design only. It measures the uncertainty of either the positive or the negative edge over 1000 cycles. It is also measured at output levels of VCC/2. Refer to Figure 3 for further explanation. Note 5: Measured from the ref. input to any output pin. The length of the feedback and XTALIN traces will impact this delay time. Note 6: This parameter includes pin-to-pin skew, longterm jitter over 1000 cycles, part-to-part variation as well as propagation delay thru the device. Note 7: The GNDA pins of the 701 must be as free of noise as possible for minimum jitter. Separate analog ground plane is recommended for the PCB. Also the VCCA pin requires extra filtering to further reduce noise. Ferrite beads for filtering and bypass capacitors are suggested for the VCCA pin. Circuit 1. Test Circuit TL/F/11920 – 4 5 http://www.national.com CGS701A AC Electrical Characteristics (Continued) TL/F/11920 – 5 FIGURE 2. Waveforms TL/F/11920 – 6 Jitter e l Period(n) b Period(n a 1) l e 300 ps for either the rising or falling edge, where n is 1 to 1000 cycles. FIGURE 3. Jitter APPLICATION REFERENCES AND BIBLIOGRAPHY: Information relating to EMI, external feedback and general application issues are in the following application notes: AN-968 AN-988 (EMI Application Note) AN-640 AN-991 http://www.national.com 6 Application Example: Cascading CGS701A TL/F/11920 – 7 Application Example: External Feedback Option for the CGS701A Any one of the 1X output clocks, (CLK1 – 0–CLK1 – 5), on the CGS701A can be used instead of the FBK OUT pin. When used in this configuration, pin 7 is a no connect and the 1X outputs can no longer be used in the 2X mode. TL/F/11920 – 15 7 http://www.national.com Ordering Information (Contact NSC Marketing for Specific Date of Availability) TL/F/11920 – 16 http://www.national.com 8 9 http://www.national.com CGS701AV Commercial Low Skew PLL 1 to 8 CMOS Clock Driver CGS701ATV Industrial Low Skew PLL 1 to 8 CMOS Clock Driver Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Molded Plastic Leaded Chip Carrier Order Number CGS701AV or CGS701ATV NS Package Number V28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 http://www.national.com 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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