THC63LVDM83D _Rev.3.1_E THC63LVDM83D REDUCED SWING LVDS 24Bit COLOR HOST-LCD PANEL INTERFACE General Description Features The THC63LVDM83D transmitter is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to 1080p(60Hz). The THC63LVDM83D converts 28bits of CMOS/TTL data into LVDS(Low Voltage Differential Signaling) data stream. The transmitter can be programmed for rising edge or falling edge clocks through a dedicated pin. At a transmit clock frequency of 160MHz, 24bits of RGB data and 4bits of timing and control data (HSYNC, VSYNC, CNTL1, CNTL2) are transmitted at an effective rate of 1120Mbps per LVDS channel. • Wide dot clock range: 8-160MHz suited for NTSC, VGA, SVGA, XGA,SXGA and SXGA+ • • • • • • • • • • PLL requires no external components Supports spread spectrum clock generator On chip jitter filtering Clock edge selectable Supports reduced swing LVDS for low EMI Power down mode Low power single 3.3V CMOS design Low profile 56 Lead TSSOP Package 1.2 up to 3.3V tolerant data inputs to connect directly to low power,low voltage application and graphic processor. Pin compatible with THC63LVDM83C/83R(24bits) Block Diagram THC63LVDM83D CMOS/TTL INPUTS TB0-6 TC0-6 TD0-6 7 7 7 7 TTL PARALLEL TO SERIAL TA0-6 DATA (LVDS) TA +/TB +/TC +/TD +/(56-1120Mbit/On Each LVDS Channel) TRANSMITTER CLKIN (8 to 160MHz) TCLK +/- PLL CLOCK (LVDS) 8-160MHz R/F /PDWN RS Copyright©2011 THine Electronics, Inc. 1/12 THine Electronics, Inc. THC63LVDM83D_Rev.3.1_E Pin Out THC63LVDM83D RS TD1 TA5 TA6 GND TB0 TB1 TD2 VCC TD3 TB2 TB3 GND TB4 TB5 TD4 R/F TD5 TB6 TC0 GND TC1 TC2 TC3 TD6 VCC TC4 TC5 Copyright©2011 THine Electronics, Inc. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 2/12 TA4 TA3 TA2 GND TA1 TA0 TD0 LVDS GND TATA+ TBTB+ LVDS VCC LVDS GND TCTC+ TCLKTCLK+ TDTD+ LVDS GND PLL GND PLL VCC PLL GND /PDWN CLK IN TC6 GND THine Electronics, Inc. THC63LVDM83D_Rev.3.1_E Pin Description Pin Name Pin # Type Description TA+, TA- 47, 48 LVDS OUT TB+, TB- 45, 46 LVDS OUT TC+, TC- 41, 42 LVDS OUT TD+, TD- 37, 38 LVDS OUT TCLK+, TCLK- 39, 40 LVDS OUT TA0 ~ TA6 51, 52, 54, 55, 56, 3, 4 IN TB0 ~ TB6 6, 7, 11, 12, 14, 15, 19 IN TC0 ~ TC6 20, 22, 23, 24, 27, 28, 30 IN TD0 ~ TD6 50, 2, 8, 10, 16, 18, 25 IN /PDWN 32 IN LVDS Data Out. LVDS Clock Out. Pixel Data Inputs. H: Normal operation, L: Power down (all outputs are Hi-Z) LVDS swing mode, VREF select.See Fig4, 5. RS 1 IN RS LVDS Swing Small Swing Input Support VCC 350mV N/A 0.6 ~ 1.4V 350mV RS=VREFa GND 200mV N/A a. VREF is Input Reference Voltage. R/F 17 IN VCC 9, 26 Power CLKIN 31 IN GND 5, 13, 21, 29, 53 Input Clock Triggering Edge Select. H: Rising edge, L: Falling edge Power Supply Pins for TTL inputs and digital circuitry. Clock in. Ground Ground Pins for TTL inputs and digital circuitry. LVDS VCC 44 Power Power Supply Pins for LVDS Outputs. LVDS GND 36, 43, 49 Ground Ground Pins for LVDS Outputs. PLL VCC 34 Power Power Supply Pin for PLL circuitry. PLL GND 33, 35 Ground Ground Pins for PLL circuitry. Copyright©2011 THine Electronics, Inc. 3/12 THine Electronics, Inc. THC63LVDM83D _Rev.3.1_E Absolute Maximum Ratings 1 Supply Voltage (VCC) -0.3V ~ +4.0V CMOS/TTL Input Voltage -0.3V ~ (VCC + 0.3V) CMOS/TTL Output Voltage -0.3V ~ (VCC + 0.3V) LVDS Transmitter Output Voltage -0.3V ~ (VCC + 0.3V) Output Current continuous Junction Temperature +125 °C Storage Temperature Range -55 °C ~ +150 °C Reflow Peak Temperature / Time +260 °C / 10sec. Maximum Power Dissipation @+25 °C 1.8W 1. “Absolute Maximum Ratings” are those valued beyond which the safety of the device can not be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. Copyright©2011 THine Electronics, Inc. 4/12 THine Electronics, Inc. THC63LVDM83D_Rev.3.1_E Electrical Characteristics CMOS/TTL DC Specifications VCC = 3.0V ~ 3.6V, Ta = 0 °C ~ +70 °C Symbol Parameter VIH High Level Input Voltage RS=VCC or GND 2.0 VCC V VIL Low Level Input Voltage RS=VCC or GND GND 0.8 V 1.2 2.8 V VDDQ1 Conditions Small Swing Voltage VREF Input Reference Voltage Small Swing (RS=VDDQ/2) VSH2 Small Swing High Level Input Voltage VREF = VDDQ/2 VSL2 Small Swing Low Level Input Voltage VREF = VDDQ/2 IINC Input Current 0V ≤ V IN ≤ V CC Min. Typ. Max. Units VDDQ/2 VDDQ/2 +100mV V VDDQ/2 -100mV ± 10 V μA Notes: 1VDDQ voltage defines max voltage of small swing input. It is not an actual input voltage. 2 Small swing signal is applied to TA0-6,TB0-6,TC0-6,TD0-6 and CLKIN. LVDS Transmitter DC Specifications VCC = 3.0V ~ 3.6V, Ta = 0 °C ~ +70 °C Symbol Parameter Conditions Normal swing VOD Differential Output Voltage Min. Typ. Max. Units 250 350 450 mV 100 200 300 mV 35 mV RS=VCC RL=100Ω Reduced swing RS=GND ΔVOD VOC Change in VOD between complementary output states Common Mode Voltage ΔVOC Change in VOC between complementary output states IOS Output Short Circuit Current IOZ Output TRI-STATE Current Copyright©2011 THine Electronics, Inc. RL=100Ω 1.125 VOUT=0V, RL=100Ω /PDWN=0V, VOUT=0V to VCC 5/12 1.25 1.375 V 35 mV -24 mA ± 10 μA THine Electronics, Inc. THC63LVDM83D_Rev.3.1_E Supply Current VCC = 3.0V ~ 3.6V, Ta = 0 °C ~ +70 °C Symbol ITCCW ITCCS Parameter Transmitter Supply Current Transmitter Power Down Supply Current Condition(*) Typ. Max. Units RL=100Ω,CL=5pF f=85MHz 61 67 mA VCC=3.3V, RS=VCC f=135MHz 77 83 mA Worst Case Pattern f=160MHz 84 92 mA RL=100Ω,CL=5pF f=85MHz 50 56 mA VCC=3.3V, RS=GND f=135MHz 65 71 mA Worst Case Pattern f=160MHz 73 80 mA /PDWN = L, All Inputs = L or H 10 μA Worst Case Pattern CLKIN Tx0 Tx1 Tx2 Tx3 Tx4 Tx5 Tx6 x= A, B, C, D Fig1. Worst Case Pattern Copyright©2011 THine Electronics, Inc. 6/12 THine Electronics, Inc. THC63LVDM83D_Rev.3.1_E Switching Characteristics VCC = 3.0V ~ 3.6V, Ta = 0°C ~ +70 °C Symbol Parameter tTCIT CLK IN Transition time tTCP CLK IN Period tTCH Min. Typ. Max. Units 5.0 ns 6.25 T 125 ns CLK IN High Time 0.35T 0.5T 0.65T ns tTCL CLK IN Low Time 0.35T 0.5T 0.65T ns tTCD CLK IN to TCLK+/- Delay tTS TTL Data Setup to CLK IN 2.0 ns tTH TTL Data Hold from CLK IN 0.0 ns tLVT LVDS Transition Time 3T ns 0.6 1.5 ns 0.0 +0.15 ns tTOP1 Output Data Position0 (T=6.25ns~20ns) -0.15 tTOP0 Output Data Position1 (T=6.25ns~20ns) T --- – 0.15 7 T --7 T --- + 0.15 7 ns tTOP6 Output Data Position2 (T=6.25ns~20ns) T 2 --- – 0.15 7 T 2 --7 T 2 --- + 0.15 7 ns tTOP5 Output Data Position3(T=6.25ns~20ns) T 3 --- – 0.15 7 T 3 --7 T 3 --- + 0.15 7 ns tTOP4 Output Data Position4 (T=6.25ns~20ns) T 4 --- – 0.15 7 T 4 --7 T 4 --- + 0.15 7 ns tTOP3 Output Data Position5 (T=6.25ns~20ns) T 5 --- – 0.15 7 T 5 --7 T 5 --- + 0.15 7 ns tTOP2 Output Data Position6 (T=6.25ns~20ns) T 6 --- – 0.15 7 T 6 --7 T 6 --- + 0.15 7 ns tTPLL Phase Lock Loop Set 10.0 ms AC Timing Diagrams TTL Input 90% 90% CLK IN 10% 10% tTCIT tTCIT Fig2. CLKIN Transition Time LVDS Output Vdiff=(TA+)-(TA-) TA+ Vdiff 5pF 80% 80% 20% 20% 100Ω TAtLVT LVDS Output Load tLVT Fig3. LVDS Output Load and Transition Time Copyright©2011 THine Electronics, Inc. 7/12 THine Electronics, Inc. THC63LVDM83D_Rev.3.1_E AC Timing Diagrams RS pin tTCP TTL Inputs VOD VCC 0.6~1.4V tTCH GND 350mV 200mV VCC CLK IN VCC/2 VCC/2 VCC/2 GND tTCL tTS tTH VCC Tx0-Tx6 VCC/2 VCC/2 GND tTCD TCLK+ VOD VOC TCLKNote: CLK IN: for R/F=GND, denote as solid line, for R/F=VCC, denote as dashed line. Fig4. CLKIN Period, High/Low Time, Setup/Hold Timing Small Swing Inputs tTCP tTCH RS pin VREF VCC VCC/2 0.6~1.4V Input Voltage of RS pin GND VCC/2 VDDQ CLK IN VDDQ/2 VREF GND VDDQ/2 VDDQ/2 tTCL tTS tTH VDDQ Tx0-Tx6 VDDQ/2 VDDQ/2 VREF GND tTCD TCLK+ VOC TCLK- Note: CLK IN: for R/F=GND, denote as solid line, for R/F=VCC, denote as dashed line. Fig5. Small Swing Inputs Copyright©2011 THine Electronics, Inc. 8/12 THine Electronics, Inc. THC63LVDM83D_Rev.3.1_E AC Timing Diagrams LVDS Output Vdiff = 0V Vdiff = 0V TCLK+/(Differential) TA+/- TA6 TA5 TA4 TA3 TA2 TA1 TA0 TB+/- TB6 TB5 TB4 TB3 TB2 TB1 TB0 TC+/- TC6 TC5 TC4 TC3 TC2 TC1 TC0 TD+/- TD6 TD5 TD4 TD3 TD2 TD1 TD0 Previous Cycle Next Cycle tTOP1 tTOP0 tTOP6 tTOP5 tTOP4 tTOP3 tTOP2 Fig6. LVDS Output Data Position Phase Lock Loop Set Time /PDWN 2.0V 3.6V VCC 3.0V tTPLL CLKIN Vdiff = 0V TCLK+/Fig7. PLL Lock Set Time Copyright©2011 THine Electronics, Inc. 9/12 THine Electronics, Inc. THC63LVDM83D_Rev.3.1_E Note 1)Cable Connection and Disconnection Don't connect and disconnect the LVDS cable, when the power is supplied to the system. 2)GND Connection Connect the each GND of the PCB which THC63LVDM83D and LVDS-Rx on it. It is better for EMI reduction to place GND cable as close to LVDS cable as possible. 3)Multi Drop Connection Multi drop connection is not recommended. TCLK+ THC63LVDM83D LVDS-Rx TCLKLVDS-Rx 4)Asynchronous use Asynchronous use such as following systems are not recommended. CLKOUT DATA IC CLKOUT DATA LVDS-Rx TCLK- DATA IC TCLK+ THC63LVDM83D DATA TCLK+ THC63LVDM83D TCLK- CLKOUT DATA Copyright©2011 THine Electronics, Inc. DATA LVDS-Rx TCLK- CLKOUT IC CLKOUT TCLK+ THC63LVDM83D TCLK+ THC63LVDM83D IC TCLK- 10/12 THine Electronics, Inc. THC63LVDM83D_Rev.3.1_E Package 1 14.00 ± 0.10 8.10 ± 0.10 S 6.10 ± 0.10 0.50 TYP 0.10 S 0.17~0.27 1.20 MAX 0.95 ± 0.05 0.25 GAGE PLANE 0°~8° 0.10 ± 0.05 0.60 ± 0.15 1.00 Detail of Lead End Unit:mm Copyright©2011 THine Electronics, Inc. 11/12 THine Electronics, Inc. THC63LVDM83D_Rev.3.1_E Notices and Requests 1. The product specifications described in this material are subject to change without prior notice. 2. The circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. We are not responsible for possible errors and omissions in this material. Please note if errors or omissions should be found in this material, we may not be able to correct them immediately. 3. This material contains our copy right, know-how or other proprietary. Copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. Note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. This product is presumed to be used for general electric equipment, not for the applications which require very high reliability (including medical equipment directly concerning people's life, aerospace equipment, or nuclear control equipment). Also, when using this product for the equipment concerned with the control and safety of the transportation means, the traffic signal equipment, or various Types of safety equipment, please do it after applying appropriate measures to the product. 6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. Please note that this product is not designed to be radiation-proof. 8. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the Foreign Exchange and Foreign Trade Control Law. THine Electronics, Inc. E-mail: [email protected] Copyright©2011 THine Electronics, Inc. 12/12 THine Electronics, Inc.