THINE THC63LVDM87

THC63LVDM87_Rev.1.00_E
THC63LVDM87
LOW POWER / SMALL PACKAGE / 24Bit COLOR LVDS TRANSMITTER
General Description
Features
The THC63LVDM87 transmitter is designed to support
pixel data transmission between Host and Flat Panel
Display up to 1080p/WUXGA resolutions.
The THC63LVDM87 converts 28bits of CMOS/TTL
data into LVDS(Low Voltage Differential Signaling)
data stream. The transmitter can be programmed for rising edge or falling edge clocks through a dedicated pin.
At a transmit clock frequency of 160MHz, 24bits of
RGB data and 4bits of timing and control data
(HSYNC, VSYNC, DE, CONT1) are transmitted at an
effective rate of 1120Mbps per LVDS channel.
• Low power 1.8V CMOS design
• 5mm x 5mm/49pin/0.65mm pitch VFBGA Package
applicable to non-HDI PCB
• Wide dot clock range, 8-160MHz suited for
TV Signal: NTSC(12.27MHz) - 1080p(148.5MHz)
PC Signal: QVGA(8MHz) - WUXGA(154MHz)
• Supports 1.8V single power supply
• 1.8V/2.5V/3.3V CMOS inputs are supported by
setting IOVCC=1.8V/2.5V/3.3V
• LVDS swing is reducible by RS-pin to reduce EMI
and power consumption
•
•
•
•
•
PLL requires no external components
Supports spread spectrum clock generator
On chip jitter filtering
Power down mode
Input clock triggering edge is selectable by R/F-pin
Block Diagram
THC63LVDM87
TTL/CMOS
Inputs
TB0-6
TC0-6
TD0-6
7
7
7
7
TTL PARALLEL TO SERIAL
TA0-6
LVDS
Outputs
TA +/TB +/TC +/TD +/(56-1120Mbit/On Each
LVDS Channel)
TRANSMITTER
CLKIN
(8 to 160MHz)
TCLK +/-
PLL
CLOCK
(LVDS)
8-160MHz
R/F
/PDWN
RS
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THC63LVDM87_Rev.1.00_E
Pin Out
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THC63LVDM87_Rev.1.00_E
Pin Description
Pin Name
Pin #
Type
Description
TA+, TA-
B7, B6
LVDS OUT
TB+, TB-
C7, C6
LVDS OUT
TC+, TC-
D7, D6
LVDS OUT
TD+, TD-
F7, F6
LVDS OUT
TCLK+,
TCLK-
E7, E6
LVDS OUT
TA0 ~ TA6
A7,A6,A5,A4,A3,A2,A1
IN
TB0 ~ TB6
C2,D2,E2,F2,B1,C1,D1
IN
TC0 ~ TC6
E1,F1,G1,G2,G3,G4,G5
IN
TD0 ~ TD6
B5,B4,B3,B2,F3,F4,F5
IN
LVDS Data Out.
LVDS Clock Out.
Pixel Data Inputs.
H: Normal operation,
/PDWN
G7
IN
L: Power down
(All outputs are Hi-Z and all circuits are standby mode with minimum current(ITCCS))
LVDS swing mode select.
RS
C5
IN
RS
LVDS Swing(VOD, see Fig4)
H
350mV
L
200mV
Input Clock Triggering Edge Select.
R/F
E5
IN
CLKIN
G6
IN
IO VCC
D4
Power
Power Supply Pin for IO Inputs.
VCC
C4
Power
Power Supply Pin for digital circuitry.
LVDS VCC
D5
Power
Power Supply Pin for LVDS Outputs.
PLL VCC
E4
Power
Power Supply Pin for PLL circuitry.
GND
C3,D3,E3
Ground
Ground Pins for Common.
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H: Rising edge, L: Falling edge
Clock input.
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THC63LVDM87_Rev.1.00_E
Absolute Maximum Ratings
Supply Voltage (IO VCC)
-0.3V ~ +4.0V
Supply Voltage (VCC, PLL VCC, LVDS VCC)
-0.3V ~ +2.1V
CMOS/TTL Input Voltage
-0.3V ~ (IO VCC + 0.3V)
LVDS Transmitter Output Voltage
-0.3V ~ (LVDS VCC + 0.3V)
LVDS Total Output Current
-50mA ~ 50mA
Junction Temperature (Tj)
+125 °C
Storage Temperature Range
-55 °C ~ +125 °C
Reflow Peak Temperature / Time
+260 °C / 10sec.
Maximum Power Dissipation @+25 °C
1.3W
Recommended Operating Conditions
Parameter
Min.
Typ
Max
Units
Supply Voltage (IOVCC)
1.62
1.8/2.5/3.3
3.6
V
Supply Voltage (PLLVCC / LVDSVCC / VCC)
1.62
1.8
1.98
V
Operating Ambient Temperature (Ta)
-40
85
°C
Input
8
160
MHz
LVDS Output
8
160
MHz
Clock Frequency
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THC63LVDM87_Rev.1.00_E
Electrical Characteristics
CMOS/TTL DC Specifications
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
VIH18
High Level Input Voltage
VIL18
Low Level Input Voltage
VIH25
High Level Input Voltage
VIL25
Low Level Input Voltage
VIH33
High Level Input Voltage
VIL33
Low Level Input Voltage
IINC
Input Current
Conditions
Min.
IOVCC=1.62~1.98V
Max.
Units
0.65 IOVCC
IOVCC+0.3
V
-0.3
0.35 IOVCC
V
1.7
IOVCC+0.3
V
-0.3
0.7
V
2.0
IOVCC+0.3
V
-0.3
0.8
V
-10
10
μA
IOVCC=2.3~2.7V
IOVCC=3.0~3.6V
Typ.
VIN=GND~IOVCC
LVDS Transmitter DC Specifications
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Normal swing
VOD
Differential Output Voltage
RL=100Ω
RS=H
Reduced swing
RS=L
ΔVOD
VOC
Min.
Typ.
ΔVOC
Change in VOC between
complementary output states
IOS
Output Short Circuit Current
IOZ
Output TRI-STATE Current
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RL=100Ω
350
450
mV
140
200
300
mV
35
mV
1.125
VOUT=GND, RL=100Ω
/PDWN=L,
VOUT=GND~LVDSVCC
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Units
250
Change in VOD between
complementary output states
Common Mode Voltage
Max.
-20
1.25
1.375
V
35
mV
100
mA
20
μA
THine Electronics, Inc.
THC63LVDM87_Rev.1.00_E
Supply Current
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
ITCCW
Parameter
Transmitter
Supply
Current
ITCCS
Transmitter
Power Down
Supply Current
Condition(*)
RL=100Ω
CL=5pF
Typ.
Max.
Units
RS=H
f=37MHz
25
33
mA
Normal swing
mode
f=71MHz
30
46
mA
f=160MHz
44
79
mA
RS=L
f=37MHz
19
27
mA
Reduced swing
mode
f=71MHz
24
40
mA
f=160MHz
38
73
mA
/PDWN = L, All Inputs = L or H
1
50
μA
(a) All Typ. values are at Vcc=1.8V, Ta=25 °C . The 16 Grayscale Pattern (Fig1) inputs test for a typical display pattern.
(b) All Max. values are at Vcc=1.98V, Ta=85 °C . LVDS Output Full Toggle Pattern (Fig2) produces maximum switching
frequency for all the LVDS outputs.
Fig1 16 Grayscale Pattern
TCLK+
Tx+
x= A, B, C, D
Fig2 LVDS Output Full Toggle Pattern
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THC63LVDM87_Rev.1.00_E
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
Units
6.25
T
125
ns
tTCP
CLK IN Period
tTCH
CLK IN High Time
0.35T
0.5T
0.65T
ns
tTCL
CLK IN Low Time
0.35T
0.5T
0.65T
ns
tTCD
CLK IN to TCLK+/- Delay (Fig4)
5T+3.1
5T+8
ns
tTS
TTL Data Setup to CLK IN
0.8
ns
tTH
TTL Data Hold from CLK IN
0.8
ns
tLVT
LVDS Transition Time
0.6
1.5
ns
0.0
+0.15
ns
tTOP1
Output Data Position0 (T=6.25ns~15ns)
-0.15
tTOP0
Output Data Position1 (T=6.25ns~15ns)
T
--- – 0.15
7
T
--7
T
--- + 0.15
7
ns
tTOP6
Output Data Position2 (T=6.25ns~15ns)
T
2 --- – 0.15
7
T
2 --7
T
2 --- + 0.15
7
ns
tTOP5
Output Data Position3 (T=6.25ns~15ns)
T
3 --- – 0.15
7
T
3 --7
T
3 --- + 0.15
7
ns
tTOP4
Output Data Position4 (T=6.25ns~15ns)
T
4 --- – 0.15
7
T
4 --7
T
4 --- + 0.15
7
ns
tTOP3
Output Data Position5 (T=6.25ns~15ns)
T
5 --- – 0.15
7
T
5 --7
T
5 --- + 0.15
7
ns
tTOP2
Output Data Position6 (T=6.25ns~15ns)
T
6 --- – 0.15
7
T
6 --7
T
6 --- + 0.15
7
ns
tTPLL
Phase Lock Loop Set
10.0
ms
AC Timing Diagrams
LVDS Output
Vdiff=(TA+)-(TA-)
TA+
Vdiff
5pF
80%
80%
20%
20%
100Ω
TAtLVT
LVDS Output Load
tLVT
Fig3. LVDS Output Load and Transition Time
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THC63LVDM87_Rev.1.00_E
AC Timing Diagrams
tTCP
TTL Inputs
tTCH
R/F=H
IOVCC
CLK IN IOVCC/2
IOVCC/2
IOVCC/2
R/F=L
GND
tTCL
tTS
tTH
IOVCC
Tx0-Tx6
IOVCC/2
IOVCC/2
GND
tTCD
TCLK+
VOD
VOC
TCLK-
Fig4. CLKIN Period, High/Low Time, Setup/Hold Timing
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THC63LVDM87_Rev.1.00_E
AC Timing Diagrams
LVDS Output
Vdiff = 0V
Vdiff = 0V
TCLK+/(Differential)
TA+/-
TA6
TA5
TA4
TA3
TA2
TA1
TA0
TB+/-
TB6
TB5
TB4
TB3
TB2
TB1
TB0
TC+/-
TC6
TC5
TC4
TC3
TC2
TC1
TC0
TD+/-
TD6
TD5
TD4
TD3
TD2
TD1
TD0
Previous Cycle
Next Cycle
tTOP1
tTOP0
tTOP6
tTOP5
tTOP4
tTOP3
tTOP2
Fig5. LVDS Output Data Position
Phase Lock Loop Set Time
/PDWN
VIH
tTPLL
CLKIN
Vdiff = 0V
TCLK+/-
Fig6. PLL Lock Time
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THC63LVDM87_Rev.1.00_E
Note
1)Cable Connection and Disconnection
Don't connect and disconnect the LVDS cable, when the power is supplied to the system.
2)GND Connection
Connect the each GND of the PCB which THC63LVDM87 and LVDS-Rx on it. It is better for EMI reduction to place
GND cable as close to LVDS cable as possible.
3)Multi Drop Connection
Multi drop connection is not recommended.
4)Asynchronous use
Asynchronous use such as following systems are not recommended.
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THC63LVDM87_Rev.1.00_E
Package
VFBGA
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THC63LVDM87_Rev.1.00_E
Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not
always apply to the customer's design. We are not responsible for possible errors and omissions
in this material. Please note if errors or omissions should be found in this material, we may not
be able to correct them immediately.
3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to
third parties the contents of this material without our prior permission is prohibited.
4. Note that if infringement of any third party's industrial ownership should occur by using this
product, we will be exempted from the responsibility unless it directly relates to the production
process or functions of the product.
5. This product is presumed to be used for general electric equipment, not for the applications
which require very high reliability (including medical equipment directly concerning people's
life, aerospace equipment, or nuclear control equipment). Also, when using this product for the
equipment concerned with the control and safety of the transportation means, the traffic signal
equipment, or various Types of safety equipment, please do it after applying appropriate
measures to the product.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur
with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you
are encouraged to have sufficiently redundant or error preventive design applied to the use of the
product so as not to have our product cause any social or public damage.
7. Please note that this product is not designed to be radiation-proof.
8. Customers are asked, if required, to judge by themselves if this product falls under the category
of strategic goods under the Foreign Exchange and Foreign Trade Control Law.
THine Electronics, Inc.
E-mail: [email protected]
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