54FCT273 Octal D-Type Flip-Flop General Description Features The ’FCT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. n n n n n n n Eight edge-triggered D flip-flops Buffered common clock Buffered, asynchronous Master Reset See ’FCT377 for clock enable version See ’FCT373 for transparent latch version See ’FCT374 for TRI-STATE ® version Output sink capability of 32 mA, source capability of 12 mA n TTL input and output level compatible n CMOS power consumption n Standard Microcircuit Drawing (SMD) 5962-8765601 Ordering Code Military Package Package Description Number 54FCT273DMQB J20A 20-Lead Ceramic Dual-In-Line 54FCT273FMQB W20A 20-Lead Cerpack 54FCT273LMQB E20A 20-Lead Ceramic Leadless Chip Carrier, Type C Connection Diagrams Pin Assignment for DIP and Flatpack Pin Assignment for LCC DS100956-2 DS100956-1 Pin Description Names D0–D7 Data Inputs MR Master Reset CP Clock Pulse Input Q0–Q7 Data Outputs (Active LOW) (Active Rising Edge) TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100956 www.national.com 54FCT273 Octal D-Type Flip-Flop August 1998 Truth Table H = HIGH Voltage Level steady state h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition L = LOW Voltage Level steady state I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition X = Immaterial N = LOW-to-HIGH clock transition Mode Select-Function Table Operating Mode Inputs Output MR CP Dn Reset (Clear) L X X L Load “1” H N h H Load “0” H N l L Qn Logic Diagram DS100956-3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) Current Applied to Output in LOW State (Max) twice the rated IOL (mA) DC Latchup Source Current −500 mA (Across Comm Operating Range) Over Voltage Latchup VCC + 4.5V If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State −65˚C to +150˚C −55˚C to +125˚C Recommended Operating Conditions −55˚C to +175˚C Free Air Ambient Temperature Military Supply Voltage Military −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA −55˚C to +125˚C +4.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. −0.5V to +4.75V −0.5V to VCC Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol Parameter FCT240 Min Max Units VCC VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage 54FCT 4.3 V Min 54FCT 2.4 V Min Output LOW Voltage 54FCT 0.2 V Min 54FCT 0.5 V Min 5 µA Max VOL 2.0 Conditions V Recognized HIGH Signal 0.8 V −1.2 V Recognized LOW Signal IIN = −18 mA Min IOH = −300 uA IOH = −12 mA IOL = 300 µA IOL = 32 mA VIN = 5.5V IIH Input HIGH Current IIL Input LOW Current −5 µA Max IOS Output Short-Circuit Current −60 mA Max VIN = 0.0V VOUT = 0.0V ICCQ Power Supply Current 1.5 mA Max VIN = 0.2V or VIN = 5.3V ∆ICC Power Supply Current 2.0 mA Max ICCT Total Power Supply Current 6.0 mA Max 4.0 mA Max VIN = 3.4V VIN = 3.4V or VIN = GND, OE = GND, fI = 10Mhz, outputs open, one bit toggling - 50% duty cycle VIN = 5.3V or VIN = 0.2V,OE = GND, fI = 10Mhz, outputs open, one bit toggling - 50% duty cycle Outputs Open,OE = GND, One Bit Toggling, 50% Duty Cycle ICCD Dynamic ICC 0.25 mA/MHz Max AC Electrical Characteristics Symbol Parameter 54FCT TA = −55˚C to +125˚C VCC = 4.5V to 5.5V Units Fig. No. ns Figures 2, 5 ns Figures 2, 5 CL = 50 pF Min Max tPLH Propagation Delay 2.0 15.0 tPHL CP to On 2.0 15.0 tPHL Propagation Delay 2.0 15.0 MR to On 3 www.national.com AC Operating Requirements Symbol 54FCT TA = −55˚C to +125˚C VCC = 4.5V to 5.5V Parameter Units Fig. No. ns Figure 6 ns Figure 6 ns Figure 2 CL = 50 pF Min Max ts(H) Setup Time, HIGH 3.5 ts(L) or LOW Dn to CP 3.5 th(H) Hold Time, HIGH 2.5 th(L) or LOW Dn to CP 2.5 tw(H) Pulse Width, CP, 7.0 tw(L) HIGH or LOW 7.0 Master Reset Pulse 7.0 ns Figure 2 5.0 ns Figure 6 tw(L) Width, LOW tREC Recovery Time MR to CP Capacitance Symbol Parameter Max Units CIN Input Capacitance 10 pF COUT (Note 3) Output Capacitance 12 pF Note 3: COUT is measured at frequency f = 1 MHz, per MIL-STD-833B, Method 3012. www.national.com 4 Conditions TA = 25˚C VCC = 0V VCC = 5.0V AC Loading DS100956-4 DS100956-6 *Includes jig and probe capacitance FIGURE 3. VM = 1.5V Input Pulse Requirements FIGURE 1. Standard AC Test Load Amplitude Rep. Rate tw tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 4. Test Input Signal Requirements DS100956-5 FIGURE 2. Propagation Delay, Pulse Width Waveforms DS100956-8 FIGURE 5. Propagation Delay Waveforms for Inverting and Non-Inverting Functions DS100956-9 FIGURE 6. Setup Time, Hold Time and Recovery Time Waveforms 5 www.national.com 6 Physical Dimensions inches (millimeters) unless otherwise noted 20-Terminal Ceramic Chip Carrier (L) NS Package Number E20A 20-Lead Ceramic Dual-In-Line (D) NS Package Number J20A 7 www.national.com 54FCT273 Octal D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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