SMD Type Product specification FDN358P General Description Features SuperSOTTM-3 P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMCIA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package. SuperSOTTM-8 SuperSOTTM-6 SuperSOTTM-3 -1.5 A, -30 V, RDS(ON) = 0.125 Ω @ VGS = -10 V RDS(ON) = 0.20 Ω @ VGS = - 4.5 V. High power version of industry SOT-23 package: identical pin out to SOT-23; 30% higher power handling capability. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. SO-8 SOIC-16 SOT-223 D D 8 35 S S G TM SuperSOT -3 Absolute Maximum Ratings G TA = 25oC unless other wise noted Symbol Parameter FDN358P VDSS Drain-Source Voltage -30 V VGSS Gate-Source Voltage ±20 V ID Drain/Output Current - Continuous -1.5 A - Pulsed PD Maximum Power Dissipation -5 (Note 1a) (Note 1b) TJ,TSTG Units Operating and Storage Temperature Range 0.5 W 0.46 -55 to 150 °C THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W RθJC Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W http://www.twtysemi.com 4008-318-123 1 of 2 SMD Type Product specification FDN358P Electrical Characteristics (TA = 25 OC unless otherwise noted ) Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage ∆BVDSS/∆TJ Breakdown Voltage Temp. Coefficient VGS = 0 V, ID = -250 µA -30 ID = -250 µA, Referenced to 25 C IDSS Zero Gate Voltage Drain Current VDS = -24 V, VGS = 0 V IGSSF Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V IGSSR Gate - Body Leakage, Reverse VGS = -20 V, VDS = 0 V -100 nA o V TJ = 55°C ON CHARACTERISTICS mV/ oC -28 -1 µA -10 µA 100 nA (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = -250 µA ∆VGS(th)/∆TJ Gate Threshold Voltage Temp. Coefficient ID = -250 µA, Referenced to 25 oC -1 RDS(ON) Static Drain-Source On-Resistance VGS = -10 V, ID = -1.5 A -1.5 -2 TJ =125°C VGS = -4.5 V, ID = -1.2 A V mV/ oC 3 0.11 0.125 0.15 0.21 0.175 0.2 -5 Ω ID(ON) On-State Drain Current VGS = -4.5 V, VDS = -5 V gFS Forward Transconductance VDS = -10 V, ID = -1.5 A 7 A S VDS = -10 V, VGS = 0 V, f = 1.0 MHz 270 pF 150 pF 45 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS tD(on) Turn - On Delay Time tr Turn - On Rise Time tD(off) Turn - Off Delay Time tf Turn - Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge (Note 2) 8 16 ns 7 14 ns 17 27 ns 10 1.8 ns 6.5 9.1 nC VDD = -15 V, ID = -1 A, VGS = -10 V, RGEN = 6 Ω VDS = -5 V, ID = -1.5 A, VGS = -10 V 1 nC 1.1 nC DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = -0.42 A -0.74 (Note 2) -0.42 A -1.2 V Note: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. Typical RθJA using the board layouts shown below on FR-4 PCB in a still air environment : a. 250oC/W when mounted on 0.02 in2 pad of 2oz Cu. a b. 270oC/W when mounted on a 0.001 in2 pad of 2oz Cu. Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. http://www.twtysemi.com 4008-318-123 2 of 2