TYSEMI NDS331N

SMD Type
Product specification
NDS331N
General Description
Features
These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications in notebook computers, portable phones, PCMCIA
cards, and other
battery powered circuits where fast
switching, and low in-line power loss are needed in a very
small outline surface mount package.
1.3 A, 20 V. RDS(ON) = 0.21 Ω @ VGS= 2.7 V
RDS(ON) = 0.16 Ω @ VGS= 4.5 V.
Industry standard outline SOT-23 surface mount package
using poprietary SuperSOTTM-3 design for superior thermal
and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
_______________________________________________________________________________
D
S
G
Absolute Maximum Ratings
Symbol
T A = 25°C unless otherwise noted
Parameter
NDS331N
Units
VDSS
Drain-Source Voltage
20
V
VGSS
Gate-Source Voltage - Continuous
8
V
ID
Maximum Drain Current - Continuous
1.3
A
(Note 1a)
- Pulsed
PD
Maximum Power Dissipation
TJ,TSTG
Operating and Storage Temperature Range
10
(Note 1a)
(Note 1b)
0.5
W
0.46
-55 to 150
°C
250
°C/W
75
°C/W
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient
RθJC
Thermal Resistance, Junction-to-Case
(Note 1a)
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(Note 1)
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1 of 3
SMD Type
Product specification
NDS331N
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
1
µA
OFF CHARACTERISTICS
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = 250 µA
IDSS
Zero Gate Voltage Drain Current
VDS = 16 V, VGS= 0 V
20
V
10
µA
IGSSF
Gate - Body Leakage, Forward
VGS = 8 V, VDS = 0 V
100
nA
IGSSR
Gate - Body Leakage, Reverse
VGS = -8 V, VDS = 0 V
-100
nA
V
TJ =125°C
ON CHARACTERISTICS (Note 2)
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
TJ =125°C
RDS(ON)
Static Drain-Source On-Resistance
0.5
0.7
1
0.3
0.53
0.8
VGS = 2.7 V, ID = 1.3 A
TJ =125°C
VGS = 4.5 V, ID = 1.5 A
ID(ON)
On-State Drain Current
gFS
Forward Transconductance
VGS = 2.7 V, VDS = 5 V
3
VGS = 4.5 V, VDS = 5 V
4
0.15
0.21
0.24
0.4
0.11
0.16
Ω
A
VDS = 5 V, ID = 1.3 A,
3.5
S
VDS = 10 V, VGS = 0 V,
f = 1.0 MHz
162
pF
85
pF
28
pF
DYNAMIC CHARACTERISTICS
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 2)
tD(on)
Turn - On Delay Time
tr
Turn - On Rise Time
tD(off)
Turn - Off Delay Time
tf
Turn - Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
http://www.twtysemi.com
VDD = 5 V, ID = 1 A,
VGS = 5 V, RGen = 6 Ω
VDS = 5 V, ID = 1.3 A,
VGS = 4.5 V
[email protected]
5
20
ns
25
40
ns
10
20
ns
5
20
ns
3.5
5
nC
0.3
nC
1
nC
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SMD Type
Product specification
NDS331N
Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.42
A
10
A
1.2
V
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
IS
Maximum Continuous Drain-Source Diode Forward Current
ISM
Maximum Pulsed Drain-Source Diode Forward Current
VSD
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = 0.42 A (Note 2)
0.8
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by
design while RθCA is determined by the user's board design.
PD(t ) =
T J− TA
R θJ A(t )
=
T J−TA
R θJ C+RθCA(t )
= I 2D (t ) × RDS (ON )
TJ
Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 250oC/W when mounted on a 0.02 in2 pad of 2oz copper.
b. 270oC/W when mounted on a 0.001 in2 pad of 2oz copper.
1a
1b
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
http://www.twtysemi.com
[email protected]
4008-318-123
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