100329 Low Power Octal ECL/TTL Bidirectional Translator with Register General Description The 100329 is an octal registered bidirectional translator designed to convert TTL logic levels to 100K ECL logic levels and vice versa. The direction of the translation is determined by the DIR input. A LOW on the output enable input (OE) holds the ECL outputs in a cut-off state and the TTL outputs at a high impedance level. The outputs change synchronously with the rising edge of the clock input (CP) even though only one output is enabled at the time. The cut-off state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-followers to turn off when the termination supply is −2.0V, presenting a high impedance to the data bus. This high impedance reduces the termination power and prevents loss of low state noise margin when several loads share the bus. The 100329 is designed with FAST ® TTL output buffers, featuring optimal DC drive and capable of quickly charging and discharging highly capacitive loads. All inputs have 50 kΩ pull-down resistors. Features n n n n n n n Bidirectional translation ECL high impedance outputs Registered outputs FAST TTL outputs TRI-STATE ® outputs Voltage compensated operating range = −4.2V to −5.7V Standard Microcircuit Drawing (SMD) 5962-9206601 Connection Diagrams 24-Pin DIP 24-Pin Quad Cerpack DS100306-4 DS100306-2 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FAST ® is a registered trademark of Fairchild Semiconductor. © 1999 National Semiconductor Corporation DS100306 www.national.com 100329 Low Power Octal ECL/TTL Bidirectional Translator with Register September 1999 Logic Symbol Functional Diagram DS100306-1 Pin Descriptions Pin Names Description E0–E7 ECL Data I/O T0–T7 TTL Data I/O OE Output Enable Input CP Clock Pulse Input (Active Rising Edge) DIR Direction Control Input All pins function at 100K ECL levels except for T0–T7. DS100306-5 Note: DIR and OE use ECL logic levels www.national.com 2 Detail DS100306-6 OE DIR CP ECL TTL Port Port Notes L L X Input Z 1, 3 L H X LOW Input 2, 3 1 (Cut-Off) H L N L L H L N H H 1 H L L X NC 1, 3 2 H H N L L H H N H H 2 H H L NC X 2, 3 H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance N = LOW-to-HIGH Clock Transition NC = No Change Note 1: ECL input to TTL output mode. Note 2: TTL input to ECL output mode. Note 3: Retains data present before CP. 3 www.national.com Absolute Maximum Ratings (Note 4) TRI-STATE Output Current Applied to TTL Output in LOW State (Max) ESD (Note 5) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature (TSTG) −65˚C to +150˚C Maximum Junction Temperature (Tj) Ceramic +175˚C VEE Pin Potential to Ground Pin −7.0V to +0.5V VTTL Pin Potential to Ground Pin −0.5V to +6.0V ECL Input Voltage (DC) VEE to +0.5V ECL Output Current (DC Output HIGH) −50 mA TTL Input Voltage (Note 6) −0.5V to +6.0V TTL Input Current (Note 6) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State −0.5V to +5.5V Twice the Rated IOL (mA) ≥2000V Recommended Operating Conditions Case Temperature (TC) Military ECL Supply Voltage (VEE) TTL Supply Voltage (VTTL) –55˚C to +125˚C −5.7V to −4.2V +4.5V to +5.5V Note 4: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 5: ESD testing conforms to MIL-STD-883, Method 3015. Note 6: Either voltage limit or current limit is sufficient to protect inputs. Military Version TTL-to-ECL DC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −55˚C to +125˚C, VTTL = +4.5V to +5.5V Symbol VOH Conditions Parameter Min Max Units TC Output HIGH Voltage −1025 −870 mV 0˚C to −1085 −870 mV −55˚C VIN = VIH (Max) −1830 −1620 mV 0˚C to or VIL (Min) Loading with 50Ω to −2.0V +125˚C VOL Output LOW Voltage Notes (Notes 7, 8, 9) +125˚C −1830 Cutoff Voltage −1555 mV −55˚C −1950 mV 0˚C to −1850 mV +125˚C VOHC Output HIGH Voltage −1035 OE or DIR Low −55˚C mV 0˚C to (Notes 7, 8, 9) +125˚C mV −55˚C VIN = VIH (Min) Loading with −1610 mV 0˚C to or VIL (Max) 50Ω0 to −2.0V −1555 mV −55˚C V −55˚C to −1085 VOLC Output LOW Voltage +125˚C VIH Input HIGH Voltage 2.0 Over VTTL, VEE, TC Range (Notes 7, 8, 9, 10) Over VTTL, VEE, TC Range (Notes 7, 8, 9, 10) VIN = +2.7V (Notes 7, 8, 9) +125˚C VIL Input LOW Voltage 0.8 V −55˚C to +125˚C IIH Input HIGH Current 70 µA −55˚C to 125˚C Breakdown Test 1.0 mA −55˚C to VIN = +5.5V +125˚C IIL Input LOW Current −1.0 mA −55˚C to VIN = +0.5V (Notes 7, 8, 9) IIN = −18 mA (Notes 7, 8, 9) OE and DIR High (Notes 7, 8, 9) +125˚C VFCD IEE Input Clamp −1.2 V −55˚C to Diode Voltage +125˚ C VEE Supply Current −55˚C to −206 www.national.com −70 mA +125˚C 4 Inputs Open VEE = −4.2V to −5.7V Military Version ECL-to-TTL DC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −55˚C to +125˚C, CL = 50 pF, VTTL = +4.5V to + 5.5V Symbol Parameter VOH Output HIGH Voltage VOL Output LOW Voltage Min Max Units 2.5 mV 2.4 TC 0˚C to +125˚C Conditions IOH = −1 mA, VTTL = 4.50V Notes (Notes 7, 8, 9) −55˚C 0.5 mV IOL = 24 mA, VTTL = 4.50V −55˚C +125˚C VIH VIL Input HIGH Voltage Input LOW Voltage −1165 −870 −1830 −1475 mV mV −55˚C Guaranteed HIGH Signal +125˚C for All Inputs −55˚C to +125˚C IIH Input HIGH Current 350 µA 500 IIL Input LOW Current 0.50 0˚C to +125˚C µA −55˚C to +125˚C IOZHT TRI-STATE Current 70 µA Output High IOZLT TRI-STATE Current Output Short-Circuit −1.0 mA (Notes 7, 8, 9) VIN = VIH (Max) VEE = −4.2V (Notes 7, 8, 9) VIN = VIL (Min) VOUT = +2.7V (Notes 7, 8, 9) −55˚C to VOUT = +0.5V (Notes 7, 8, 9) VOUT = 0.0V, VTTL = +5.5V (Notes 7, 8, 9) (Notes 7, 8, 9) +125˚C −60 −150 mA CURRENT ITTL (Notes 7, 8, 9, 10) for All Inputs VEE = −5.7V +125˚C Output Low IOS −55˚C to Guaranteed LOW Signal (Notes 7, 8, 9, 10) VTTL Supply Current −55˚C to +125˚C 70 mA −55˚C to TTL Outputs Low 47 mA +125˚C TTL Output High 70 mA TTL Output in TRI-STATE Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 8: Screen tested 100% on each device at −55˚C, +25˚C, and +125˚C, Subgroups, 1, 2 3, 7, and 8. Note 9: Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, and +125˚C, Subgroups A1, 2, 3, 7, and 8. Note 10: Guaranteed by applying specified input condition and testing VOH/VOL. Military Version TTL-to-ECL AC Electrical Characteristics VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, VCC = VCCA = GND Symbol tPLH Parameter CP to En TC = −55˚C TC = 25˚C TC = +125˚C Min Max Min Max Min Max 1.3 3.8 1.6 3.7 1.9 4.3 Conditions Notes ns Figures 1, 2 (Notes 11, 12, 13) (Notes 11, 12, 13) ns tPHL tPZH Units OE to En 1.0 4.3 1.5 4.4 1.7 9.0 ns Figures 1, 2 1.5 5.0 1.6 4.5 1.6 5.0 ns Figures 1, 2 1.6 4.7 1.6 4.3 1.7 4.7 ns Figures 1, 2 (Cutoff to HIGH) tPHZ OE to En (HIGH to Cutoff) tPHZ DIR to En (HIGH to Cutoff) tset Tn to CP 2.5 2.0 2.5 ns Figures 1, 2 thold Tn to CP 2.5 2.0 2.5 ns Figures 1, 2 ns Figures 1, 2 (Note 14) ns Figures 1, 2 (Note 14) tpw(H) Pulse Width CP 2.5 tTLH Transition Time 0.4 tTHL 20% to 80%, 80% to 20% fMAX CP 250 2.0 2.3 2.5 0.5 2.1 250 5 0.4 250 2.4 (Note 14) MHz www.national.com Military Version ECL-to-TTL AC Electrical Characteristics VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, VCC = VCCA = GND, CL = 50 pF Symbol tPLH Parameter CP to Tn TC = −55˚C TC = 25˚C TC = +125˚C Units Conditions Notes 8.0 ns Figures 1, 2 (Notes 11, 12, 13) ns Figures 3, 4 (Notes 11, 12, 13) ns Figures 3, 5 ns Figures 3, 6 Min Max Min Max Min Max 3.1 8.0 3.1 7.3 3.3 tPHL tPZH OE to Tn 3.4 9.1 3.7 9.0 4.0 10.1 tPZL (Enable Time) 3.7 9.5 4.0 9.3 4.3 10.4 tPHZ OE to Tn 3.2 10.0 3.3 9.0 3.5 9.3 tPLZ (Disable Time) 3.0 9.8 3.4 8.8 4.1 10.4 tPHZ DIR to Tn 2.6 9.5 2.8 8.8 3.0 9.0 tPLZ (Disable Time) 2.7 8.7 3.1 8.0 4.0 9.6 tset En to CP 2.5 2.0 2.5 ns Figures 3, 4 thold En to CP 3.0 2.5 3.0 ns Figures 3, 4 tpw(H) Pulse Width CP 2.5 2.5 5.0 ns Figures 3, 4 fMAX CP 200 200 100 MHz (Note 14) (Note 14) Note 11: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 12: Screen tested 100% on each device at +25˚C, temperature only, Subgroup A9. Note 13: Sample tested (Method 5005, Table I) on each mfg. lot at +25˚C, Subgroup A9, and at +125˚C and −55˚C temperatures, Subgroups A10 and A11. Note 14: Not tested at +25˚C, +125˚C and −55˚C temperature (design characterization data). www.national.com 6 Test Circuitry (TTL-to-ECL) DS100306-7 Note 15: RT = 50Ω termination resistive load. When an input or output is being monitored by a scope, RTis supplied by the scope’s 50Ω input resistance. When an input or output is not being monitored, an external 50Ω resistance must be applied to serve as RT. Note 16: TTL and ECL force signals are brought to the DUT via 50Ω coax lines. Note 17: VTTL is decoupled to ground with 0.1 µF, VEE is decoupled to ground with 0.01 µF and VCC is connected to ground. FIGURE 1. TTL-to-ECL AC Test Circuit Switching Waveforms (TTL-to-ECL) DS100306-9 FIGURE 2. TTL to ECL Transition — Propagation Delay and Transition Times 7 www.national.com Test Circuitry (ECL-to-TTL) DS100306-10 Note 18: RT = 50Ω termination resistive load. When an input or output is being monitored by a scope, RTis supplied by the scope’s 50Ω input resistance. When an input or output is not being monitored, an external 50Ω resistance must be applied to serve as RT. Note 19: The TTL TRI-STATE pull-up switch is connected to +7V only for ZL and LZ tests. Note 20: TTL and ECL force signals are brought to the DUT via 50Ω coax lines. Note 21: VTTL is decoupled to ground with 0.1 µF, VEE is decoupled to ground with 0.01 µF and VCC is connected to ground. FIGURE 3. ECL-to-TTL AC Test Circuit Switching Waveforms (ECL-to-TTL) DS100306-11 Note: DIR is LOW, OE is HIGH FIGURE 4. ECL-to-TTL Transition — Propagation Delay and Transition Times www.national.com 8 Switching Waveforms (ECL-to-TTL) (Continued) DS100306-12 Note: DIR is LOW FIGURE 5. ECL-to-TTL Transition, OE to TTL Output, Enable and Disable Times DS100306-13 Note: OE is HIGH FIGURE 6. ECL-to-TTL Transition, DIR to TTL Output, Disable Time 9 www.national.com Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Ceramic Dual-In-Line Package (0.400" Wide) (D) Package Number J24E 24-Lead Quad Cerpak (F) Package Number W24B www.national.com 10 100329 Low Power Octal ECL/TTL Bidirectional Translator with Register Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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