LM193JAN Low Power Low Offset Voltage Dual Comparators General Description Advantages The LM193 series consists of two independent precision voltage comparators with an offset voltage specification as low as 2.0 mV max for two comparators which were designed specifically to operate from a single power supply over a wide range of voltages. Operation from split power supplies is also possible and the low power supply current drain is independent of the magnitude of the power supply voltage. These comparators also have a unique characteristic in that the input common-mode voltage range includes ground, even though operated from a single power supply voltage. n n n n n n Application areas include limit comparators, simple analog to digital converters; pulse, squarewave and time delay generators; wide range VCO; MOS clock timers; multivibrators and high voltage digital logic gates. The LM193 series was designed to directly interface with TTL and CMOS. When operated from both plus and minus power supplies, the LM193 series will directly interface with MOS logic where their low power drain is a distinct advantage over standard comparators. High precision comparators Reduced VOS drift over temperature Eliminates need for dual supplies Allows sensing near ground Compatible with all forms of logic Power drain suitable for battery operation Features n Wide supply — Voltage range: 5.0VDC to 36VDC ± 2.5VDC to ± 18VDC — Single or dual supplies: n Very low supply current drain (0.4 mA) — independent of supply voltage n Low input biasing current: 25 nA typ ± 3 nA typ n Low input offset current: n Maximum offset voltage +5mV Max @ 25˚C n Input common-mode voltage range includes ground n Differential input voltage range equal to the power supply voltage n Low output saturation voltage,: 250 mV at 4 mA typ n Output voltage compatible with TTL, DTL, ECL, MOS and CMOS logic systems Ordering Information NS Part Number JAN Part Number NS Package Number Package Description JL193BGA JL193BPA JM38510/11202BGA H08C 8LD T0-99 Metal Can JM38510/11202BPA J08A 8LD CERDIP Squarewave Oscillator Non-Inverting Comparator with Hysteresis 20143209 20143238 © 2005 National Semiconductor Corporation DS201432 www.national.com LM193JAN Low Power Low Offset Voltage Dual Comparators May 2005 LM193JAN Schematic and Connection Diagrams 20143202 Metal Can Package 20143203 Dual-In-Line Package 20143201 www.national.com 2 LM193JAN Absolute Maximum Ratings (Note 1) Supply Voltage, V+ 36VDC or ± 18VDC Differential Input Voltage (Note 5) 36V Output Voltage 36V Input Voltage −0.3VDC to +36VDC Input Current (VIN < −0.3VDC) (Note 4) 50 mA Power Dissipation (Note 2), CERDIP 400 mW @ TA = 125˚C Metal Can 330 mW @ TA = 125˚C Maximum Junction Temperature (TJmax 175˚C Output Short-Circuit to Ground (Note 3) Continuous Operating Temperature Range −55˚C ≤ TA ≤ +125˚C Storage Temperature Range −65˚C ≤ TA ≤ +150˚C Thermal Resistance θJA Metal Can (Still Air) 174˚C/W Metal Can (500LF/Min Air flow) 99˚C/W CERDIP (Still Air) 146˚C/W CERDIP (500LF/Min Air flow) 85˚C/W θJC Metal Can 44˚C/W CERDIP 33˚C/W Lead Temperature (Soldering, 10 seconds) 260˚C ESD Tolerance (Note 6) 500V Quality Conformance Inspection Mil-Std-883, Method 5005 - Group A Subgroup Description Temp˚C 1 Static tests at 25 2 Static tests at 125 3 Static tests at -55 4 Dynamic tests at 25 5 Dynamic tests at 125 6 Dynamic tests at -55 7 Functional tests at 25 8A Functional tests at 125 8B Functional tests at -55 9 Switching tests at 25 10 Switching tests at 125 11 Switching tests at -55 12 Settling time at 25 13 Settling time at 125 14 Settling time at -55 3 www.national.com LM193JAN LM193 JAN Electrical Characteristics DC Parameters Symbol Parameter Conditions VIO Input Offset Voltage IIO ± IIB CMRR Input offset Current Input Bias Current Input Voltage Common Mode Rejection Notes Subgroups Min Max Unit +VCC = 30V, -VCC = 0V, VO = 15V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 +VCC = 2V, -VCC = -28V, VO = -13V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 +VCC = 5V, -VCC = 0V, VO = 1.4V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 +VCC = 2V, -VCC = -3V, VO = -1.6V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 +VCC = 30V, -VCC = 0V, VO = 15V, RS = 20KΩ (Note 7) -25 25 nA 1, 2 (Note 7) -75 75 nA 3 +VCC = 2V, -VCC = -28V, VO = -13V, RS = 20KΩ (Note 7) -25 25 nA 1, 2 (Note 7) -75 75 nA 3 +VCC = 5V, -VCC = 0V, VO = 1.4V, RS = 20KΩ (Note 7) -25 25 nA 1, 2 (Note 7) -75 75 nA 3 +VCC = 2V, -VCC = -3V, VO = -1.6V, RS = 20KΩ (Note 7) -25 25 nA 1, 2 (Note 7) -75 75 nA 3 +VCC = 30V, -VCC = 0V, VO = 15V, RS = 20KΩ (Note 7) -100 +0.1 nA 1, 2 (Note 7) -200 +0.1 nA 3 +VCC = 2V, -VCC = -28V, VO = -13V, RS = 20KΩ (Note 7) -100 +0.1 nA 1, 2 (Note 7) -200 +0.1 nA 3 +VCC = 5V, -VCC = 0V, VO = 1.4V, RS = 20KΩ (Note 7) -100 +0.1 nA 1, 2 (Note 7) -200 +0.1 nA 3 +VCC = 2V, -VCC = -3V, VO = -1.6V, RS = 20KΩ (Note 7) -100 +0.1 nA 1, 2 (Note 7) -200 +0.1 nA 3 2V ≤ +VCC ≤ 30V, -28V ≤ -VCC ≤ 0V, -13V ≤ VO ≤ 15V 76 dB 1, 2, 3 2V ≤ +VCC ≤ 5V, -3V ≤ -VCC ≤ 0V, -1.6V ≤ VO ≤ 1.4V 70 dB 1, 2, 3 1.0 µA 1, 2, 3 ICEX Output Leakage Current +VCC = 30V, -VCC = 0V, VO = +30V +IIL Input Leakage Current +VCC = 36V, -VCC = 0V, +VI = 34V, -VI = 0V -500 500 nA 1, 2, 3 -500 1, 2, 3 -IIL Input Leakage Current +VCC = 36V, -VCC = 0V, +VI = 0V, -VI = 34V 500 nA VOL Logical "0" Output Voltage +VCC = 4.5V, -VCC = 0V, IO = 4mA 0.4 V 1 0.7 V 2, 3 +VCC = 4.5V, -VCC = 0V, IO = 8mA 1.5 V 1 2.0 V 2, 3 +VCC = 5V, -VCC = 0V, VID = 15mV 2.0 mA 1, 2 3.0 mA 3 +VCC = 30V, -VCC = 0V, VID = 15mV 3.0 mA 1, 2 4.0 mA 3 ICC ∆IO / ∆T Power Supply Current Temperature Coefficient of Input Offset Voltage www.national.com 25˚C ≤ TA ≤ +125˚C (Note 9) -25 25 µV/˚C 2 -55˚C ≤ TA ≤ 25˚C (Note 9) -25 25 µV/˚C 3 4 DC Parameters (Continued) (Continued) Notes Min Max Unit Subgroups 25˚C ≤ TA ≤ +125˚C (Note 9) -300 300 pA/˚C 2 -55˚C ≤ TA ≤ 25˚C (Note 9) -400 400 pA/˚C 3 (Note 8) 50 V/mV 4 (Note 8) 25 V/mV 5, 6 0.4 V 9 Max Unit Subgroups 7, 8B Symbol Parameter Conditions ∆IIO / ∆T Temperature Coefficient of Input Offset Current AVS Open Loop Voltage Gain +VCC = 15V, -VCC = 0V, RL = 15KΩ, 1V ≤ VO ≤ 11V VLat Voltage Latch (Logical "1" Input) +VCC = 5V, -VCC = 0V, VI = 10V, IO = 4mA AC Parameters The following conditions apply, unless otherwise specified. +VCC = 5V, −VCC = 0V Symbol Parameter Conditions tRLH Response Time VI = 100mV, RL = 5.1KΩ, VOD = 5mV 5.0 µS 7.0 µS 8A VI = 100mV, RL = 5.1KΩ, VOD = 50mV 0.8 µS 7, 8B 1.2 µS 8A VI = 100mV, RL = 5.1KΩ, VOD = 5mV 2.5 µS 7, 8B 3.0 µS 8A VI = 100mV, RL = 5.1KΩ, VOD = 50mV 0.8 µS 7, 8B 1.0 µS 8A tRHL CS Response Time Channel Separation Notes Min +VCC = 20V, -VCC = -10V, A to B 80 dB 7 +VCC = 20V, -VCC = -10V, B to A 80 dB 7 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. Note 3: Short circuits from the output to V+ can cause excessive heating and eventual destruction. When considering short circuits to ground, the maximum output current is approximately 20 mA independent of the magnitude of V+. Note 4: This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the comparators to go to the V+ voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This is not destructive and normal output states will re-establish when the input voltage, which was negative, again returns to a value greater than −0.3VDC. Note 5: Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode range, the comparator will provide a proper output state. The low input voltage state must not be less than −0.3V (or 0.3V below the magnitude of the negative power supply, if used). Note 6: Human body model, 1.5KΩ in series with 100pF. Note 7: S/S RS = 20KΩ, tested with RS = 100KΩ for better resolution Note 8: K in datalog is equivalent to V/mV. Note 9: Calculated parameter for ∆VIO / ∆T and ∆IIO / ∆T. 5 www.national.com LM193JAN LM193 JAN Electrical Characteristics LM193JAN Typical Performance Characteristics Supply Current Input Current 20143225 20143226 Response Time for Various Input Overdrives — Negative Transition Output Saturation Voltage 20143228 20143227 Response Time for Various Input Overdrives — Positive Transition 20143229 www.national.com 6 The differential input voltage may be larger than V+ without damaging the device (Note 5). Protection should be provided to prevent the input voltages from going negative more than −0.3 VDC (at 25˚C). An input clamp diode can be used as shown in the applications section. The LM193 series are high gain, wide bandwidth devices which, like most comparators, can easily oscillate if the output lead is inadvertently allowed to capacitively couple to the inputs via stray capacitance. This shows up only during the output voltage transition intervals as the comparator change states. Power supply bypassing is not required to solve this problem. Standard PC board layout is helpful as it reduces stray input-output coupling. Reducing the input resistors to < 10 kΩ reduces the feedback signal levels and finally, adding even a small amount (1.0 to 10 mV) of positive feedback (hysteresis) causes such a rapid transition that oscillations due to stray feedback are not possible. Simply socketing the IC and attaching resistors to the pins will cause input-output oscillations during the small transition intervals unless hysteresis is used. If the input signal is a pulse waveform, with relatively fast rise and fall times, hysteresis is not required. All input pins of any unused comparators should be tied to the negative supply. The output of the LM193 series is the uncommitted collector of a grounded-emitter NPN output transistor. Many collectors can be tied together to provide an output OR’ing function. An output pull-up resistor can be connected to any available power supply voltage within the permitted supply voltage range and there is no restriction on this voltage due to the magnitude of the voltage which is applied to the V+ terminal of the LM193 package. The output can also be used as a simple SPST switch to ground (when a pull-up resistor is not used). The amount of current which the output device can sink is limited by the drive available (which is independent of V+) and the β of this device. When the maximum current limit is reached (approximately 16mA), the output transistor will come out of saturation and the output voltage will rise very rapidly. The output saturation voltage is limited by the approximately 60Ω rSAT of the output transistor. The low offset voltage of the output transistor (1.0mV) allows the output to clamp essentially to ground level for small load currents. The bias network of the LM193 series establishes a drain current which is independent of the magnitude of the power supply voltage over the range of from 2.0 VDC to 30 VDC. It is usually unnecessary to use a bypass capacitor across the power supply line. Typical Applications (V+=5.0 VDC) Basic Comparator Driving CMOS Driving TTL 20143235 20143236 Squarewave Oscillator Pulse Generator 20143237 Crystal Controlled Oscillator 20143238 20143240 20143239 * For large ratios of R1/R2, D1 can be omitted. 7 www.national.com LM193JAN Application Hints LM193JAN Typical Applications (V+=5.0 VDC) (Continued) Two-Decade High Frequency VCO 20143241 V* = +30 VDC +250 mVDC ≤ VC ≤ +50 VDC 700Hz ≤ fo ≤ 100kHz Basic Comparator Non-Inverting Comparator with Hysteresis 20143206 20143209 Inverting Comparator with Hysteresis Output Strobing 20143210 20143211 www.national.com 8 LM193JAN Typical Applications (V+=5.0 VDC) (Continued) AND Gate OR Gate 20143213 20143212 Large Fan-in AND Gate Limit Comparator 20143215 20143214 Comparing Input Voltages of Opposite Polarity ORing the Outputs 20143216 20143217 9 www.national.com LM193JAN Typical Applications (V+=5.0 VDC) (Continued) Zero Crossing Detector (Single Power Supply) One-Shot Multivibrator 20143221 20143222 Bi-Stable Multivibrator One-Shot Multivibrator with Input Lock Out 20143224 20143223 Zero Crossing Detector Comparator With a Negative Reference 20143244 20143243 www.national.com 10 LM193JAN Typical Applications (V+=5.0 VDC) (Continued) Time Delay Generator 20143207 Split-Supply Applications (V+=+15 VDC and V−=−15 VDC) MOS Clock Driver 20143242 11 www.national.com LM193JAN Revision History Section Date Released Revision Section Originator Changes 05/09/05 New Release. Corporate format L. Lytle 1 MDS datasheets converted into one Corp. datasheet format. DC Drift table was deleted due to no JANS product offerings. MJLM193-X Rev 1A1 MDS will be archived. www.national.com A 12 LM193JAN Physical Dimensions inches (millimeters) unless otherwise noted Metal Can Package (H) NS Package Number H08C Ceramic Dual-In-Line Package NS Package Number J08A 13 www.national.com LM193JAN Low Power Low Offset Voltage Dual Comparators Notes National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. 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