DAC121S101QML 12-Bit Micro Power Digital-to-Analog Converter with Railto-Rail Output General Description Features The DAC121S101 is a full-featured, general purpose 12-bit voltage-output digital-to-analog converter (DAC) that can operate from a single +2.7 V to 5.5 V supply and consumes just 177 µA of current at 3.6 V. The on-chip output amplifier allows rail-to-rail output swing and the three wire serial interface operates at clock rates up to 20 MHz over the specified supply voltage range and is compatible with standard SPI™, QSPI, MICROWIRE and DSP interfaces. The supply voltage for the DAC121S101 serves as its voltage reference, providing the widest possible output dynamic range. A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a valid write to the device. A power-down feature reduces power consumption to less than a microWatt. The low power consumption and small packages of the DAC121S101 make it an excellent choice for use in battery operated equipment. The DAC121S101 operates over the extended temperature range of -55°C to +125°C. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Total Ionizing Dose 100 krad(Si) Single Event Latch-up 120 MeV-cm2/mg Guaranteed Monotonicity Low Power Operation Rail-to-Rail Voltage Output Power-on Reset to Zero Volts Output SYNC Interrupt Facility Wide power supply range (+2.7 V to +5.5 V) Small Packages Power Down Feature Key Specifications ■ ■ ■ ■ ■ ■ Resolution 12 bits DNL +0.21, -0.10 LSB (typ) Output Settling Time 12.5 µs (typ) Zero Code Error 2.1 mV (typ) Full-Scale Error −0.04 %FS (typ) Power Dissipation — Normal Mode 0.52 mW (3.6 V) / 1.19 mW (5.5 V) typ 0.014 µW (3.6 V) / 0.033 µW (5.5 V) typ — Pwr Down Mode Applications ■ ■ ■ ■ Battery-Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage & Current Sources Programmable Attenuators Ordering Information NS Part Number DAC121S101WGRQV Flight Part SMD Part Number NS Package Number Package Discription 5962R0722601VZA 100 krad(Si) WG10A 10LD Ceramic SOIC WG10A 10LD Ceramic SOIC DAC121S101WGMPR Pre-flight Prototype DAC121S101CVAL Ceramic Evaluation Board 10LD Ceramic SOIC on Evaluation Board SPI™ is a trademark of Motorola, Inc. © 2010 National Semiconductor Corporation 300180 www.national.com DAC121S101QML 12-Bit Micro Power Digital-to-Analog Converter with Rail-to-Rail Output May 6, 2010 DAC121S101QML Connection Diagrams 10LD Ceramic SOIC 30018001 Top View See NS Package Number WG10A Block Diagram 30018003 www.national.com 2 Operating Ratings (Note 1, Note 2) Operating Temperature Range Supply Voltage, VA Any Input Voltage (Note 6) Output Load SCLK Frequency (Note 1, Note 2) Supply Voltage, VA 6.5 V Voltage on any Input Pin −0.3 V to (VA + 0.3 V) Input Current at Any Pin (Note 3) 10 mA Maximum Output Current (Note 10) 10 mA VOUT Pin in Powerdown Mode 1.0 mA Package Input Current (Note 3) 20 mA Power Dissipation at TA = 25°C See (Note 4) Maximum Junction Temperature 175°C Lead Temperature Ceramic SOIC (Soldering 10 Seconds) 260°C Storage Temperature −65°C to +150°C Package Weight (Typical) Ceramic SOIC 220 mg ESD Tolerance (Note 5) Class 3A (5000 V) −55°C to +125°C +2.7 V to 5.5 V −0.1 V to (VA + 0.1 V) 0 to 1500 pF Up to 20 MHz Package Thermal Resistance Package θJA (Still Air) θJC 10-lead Ceramic SOIC Package on 2 layer, 1oz. PCB 214°C/W 25.7°C/W Quality Conformance Inspection MIL-STD-883, Method 5005 - Group A Subgroup Description 1 Static tests at Temp (° C) +25 2 Static tests at +125 3 Static tests at -55 4 Dynamic tests at +25 5 Dynamic tests at +125 6 Dynamic tests at -55 7 Functional tests at +25 8A Functional tests at +125 8B Functional tests at -55 9 Switching tests at +25 10 Switching tests at +125 11 Switching tests at -55 12 Setting time at +25 13 Setting time at +125 14 Setting time at -55 3 www.national.com DAC121S101QML Absolute Maximum Ratings DAC121S101QML DAC121S101 Electrical Characteristics DC Parameters The following specifications apply for VA = +2.7 V to +5.5 V, RL = ∞, CL = 200 pF to GND, fSCLK = 20 MHz, input code range 48 to 4047. Boldface limits apply for TMIN ≤ TA ≤ TMAX: all other limits TA = 25°C, unless otherwise specified. Symbol Parameter Conditions Notes Typical (Note 8) Min Max Units Subgroups STATIC PERFORMANCE Resolution (Note 9) 12 Monotonicity (Note 9) 12 INL Integral Non-Linearity Over Decimal codes 48 to 4047 DNL Differential Non-Linearity VA = 2.7 V to 5.5 V ZE Zero Code Error IOUT = 0 +2.12 FSE Full-Scale Error IOUT = 0 GE Gain Error All ones Loaded to DAC register ZCED TC GE LSB 1, 2, 3 +1.0 LSB 1, 2, 3 LSB 1, 2, 3 +15 mV 1, 2, 3 −0.04 −1.0 %FSR 1, 2, 3 −0.11 ±1.0 %FSR 1, 2, 3 −0.10 (Note 9) VA = 3 V (Note 9) VA = 5 V Bits 8.0 −8.0 +0.21 Zero Code Error Drift Gain Error Tempco ±2.75 Bits −0.7 −20 µV/°C −0.7 ppm/°C −1.0 ppm/°C OUTPUT CHARACTERISTICS IPD SINK Vout Pin in Powerdown Mode All PD Modes (Note 9) Output Voltage Range ZCO FSO Zero Code Output Full Scale Output Maximum Load Capacitance (Note 9) mA VA V VA = 3 V, IOUT = 10 µA 2.0 6 mV 1, 2, 3 VA = 3 V, IOUT = 100 µA 4 10 mV 1, 2, 3 VA = 5 V, IOUT = 10 µA 2 8 mV 1, 2, 3 VA = 5 V, IOUT = 100 µA 4 9 mV 1, 2, 3 VA = 3 V, IOUT = 10 µA 2.997 2.990 V 1, 2, 3 VA = 3 V, IOUT = 100 µA 2.991 2.985 V 1, 2, 3 VA = 5 V, IOUT = 10 µA 4.994 4.985 V 1, 2, 3 VA = 5 V, IOUT = 100 µA 4.992 4.985 V 1, 2, 3 RL = ∞ (Note 9) RL = 2 kΩ DC Output Impedance www.national.com 0 1.0 1500 1500 8 4 pF pF 16 Ω 1, 2, 3 The following specifications apply for VA = +2.7 V to +5.5 V, RL = ∞, CL = 200 pF to GND, fSCLK = 20 MHz, input code range 48 to 4047. Boldface limits apply for TMIN ≤ TA ≤ TMAX: all other limits TA = 25°C, unless otherwise specified. Symbol Parameter Conditions Notes Typical (Note 8) Min Max Units Subgroups 6 −200 LOGIC INPUT IIN VIL Input Current Input Low Voltage VIH Input High Voltage CIN Input Capacitance +200 nA 1, 2, 3 VA = 5 V 0.8 V 1, 2, 3 VA = 3 V 0.5 V 1, 2, 3 VA = 5 V 2.4 V 1, 2, 3 VA = 3 V 2.1 V 1, 2, 3 (Note 9) 5 pF POWER REQUIREMENTS IA PC IOUT / IA Supply Current (output unloaded) Power Consumption (output unloaded) Power Efficiency Normal Mode fSCLK = 20 MHz 5.5 V 216 270 µA 1, 2, 3 3.6 V 145 200 µA 1, 2, 3 Normal Mode fSCLK = 10 MHz 5.5 V 185 230 µA 1, 2, 3 3.6 V 132 175 µA 1, 2, 3 Normal Mode fSCLK = 0 5.5 V 150 190 µA 1, 2, 3 3.6 V 115 160 µA 1, 2, 3 All PD Modes, fSCLK = 20 MHz 5.5 V 22 60 µA 1, 2, 3 3.6 V 12 30 µA 1, 2, 3 All PD Modes, fSCLK = 10 MHz 5.5 V 12 40 µA 1, 2, 3 3.6 V 6 20 µA 1, 2, 3 All PD Modes, fSCLK = 0 5.5 V .006 1.0 µA 1, 2, 3 3.6 V .004 1.0 µA 1, 2, 3 Normal Mode fSCLK = 20 MHz 5.5 V 1.19 1.49 mW 0.52 .72 mW Normal Mode fSCLK = 10 MHz 5.5 V 1.02 1.27 mW 0.47 .63 mW Normal Mode fSCLK = 0 5.5 V 0.82 1.05 mW 0.41 .58 mW All PD Modes, fSCLK = 20 MHz 5.5 V 0.12 .33 mW 0.07 .11 mW All PD Modes, fSCLK = 10 MHz 5.5 V 0.04 .22 mW All PD Modes, fSCLK = 0 5.5 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V ILOAD = 2 mA (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) 5 0.02 .08 mW 0.033 5.5 µW 0.014 3.6 µW 91 % 94 % www.national.com DAC121S101QML DC Parameters (Continued) DAC121S101QML AC and Timing Characteristics The following specifications apply for VA = +2.7 V to +5.5 V, RL = ∞, CL = 200 pF to GND, fSCLK = 20 MHz, input code range 48 to 4047. Boldface limits apply for TMIN ≤ TA ≤ TMAX: all other limits TA = 25°C, unless otherwise specified. Symbol fSCLK Parameter SCLK Frequency Conductions ts Output Voltage Settling Time change, RL = ∞ 00Fh to FF0h code change, RL = ∞ SR 1/fSCLK Wake-Up Time Max Units Subgroups 20 MHz 9, 10, 11 12.5 15 µs 9, 10, 11 CL = 500 pF 12.5 15 µs 9, 10, 11 CL ≤ 200 pF 12.5 15 µs 9, 10, 11 CL = 500 pF 12.5 15 µs 9, 10, 11 Code change from 800h to 7FFh Digital Feedthrough tWU Min CL ≤ 200 pF Output Slew Rate Glitch Impulse Typical (Note 8) (Note 9) (See Figure 2) FF0 to 00F code Notes VA = 5 V (Note 9) 1 V/µs (Note 9) 12 nV-sec (Note 9) 0.5 nV-sec .65 µs (Note 9) VA = 3 V 1.1 µs SCLK Cycle Time (See Figure 2) 50 ns 9, 10, 11 tH SCLK High time (See Figure 2) 20 ns 9, 10, 11 tL SCLK Low Time (See Figure 2) 20 ns 9, 10, 11 tSUCL Set-up Time SYNC to SCLK (See Figure 2) Rising Edge 0 ns 9, 10, 11 tSUD Data Set-Up Time (See Figure 2) 6 ns 9, 10, 11 tDHD Data Hold Time (See Figure 2) 4.5 ns 9, 10, 11 tCS SCLK fall to rise of SYNC VA = 5.5 V (See Figure 2) 10 ns 9, 10, 11 VA = 2.7 V (See Figure 2) 18 ns 9, 10, 11 VA = 5.5 V (See Figure 2) 37 ns 9, 10, 11 VA = 2.7 V (See Figure 2) 36 ns 9, 10, 11 tSYNC SYNC High Time www.national.com 6 (Note 12) The following specifications apply for VA = +2.7 V to +5.5 V, RL = ∞, CL = 200 pF to GND, fSCLK = 20 MHz, input code range 48 to 4047. Symbol Parameter Conditions Min Max Units Subgroups POWER REQUIREMENTS IA Normal Mode fSCLK = 20 MHz 5.5 V 325 µA 1 3.6 V 250 µA 1 Normal Mode fSCLK = 10 MHz 5.5 V 300 µA 1 3.6 V 225 µA 1 Normal Mode fSCLK = 0 5.5 V 275 µA 1 3.6 V 200 µA 1 All PD Modes, fSCLK = 20 MHz 5.5 V 125 µA 1 3.6 V 100 µA 1 All PD Modes, fSCLK = 10 MHz 5.5 V 115 µA 1 3.6 V 95 µA 1 All PD Modes, fSCLK = 0 5.5 V 100 µA 1 3.6 V 100 µA 1 Min Max Units Integral non-linearity ±2 LBS Output voltage settling time ±5 µA ±10 µA Normal Mode, VA = 3.6V fSCLK = 20 MHz ±6 µA Normal Mode, VA = 5.5V fSCLK = 10 MHz ±10 µA Normal Mode, VA = 3.6V fSCLK = 10 MHz ±6 µA Normal Mode, VA = 5.5V fSCLK = 0 ±8 µA Normal Mode, VA = 3.6V fSCLK = 0 ±6 µA All PD Modes, VA = 5.5V fSCLK = 20 MHz ±2 µA All PD Modes, VA = 3.6V fSCLK = 20 MHz ±1 µA All PD Modes, VA = 5.5V fSCLK = 10 MHz ±1 µA Supply Current (output unloaded) Operating Life Test Delta Parameters Symbol INL ts TA @ 25°C Parameter (Note 11) Conditions Normal Mode, VA = 5.5V fSCLK = 20 MHz IA Supply Current (output unloaded) All PD Modes, VA = 3.6V fSCLK = 10 MHz ±1 µA All PD Modes, VA = 5.5V fSCLK = 0 ±0.1 µA All PD Modes, VA = 3.6V fSCLK = 0 ±0.1 µA 7 www.national.com DAC121S101QML Radiation Electrical Characteristics DAC121S101QML Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = 0 V, unless otherwise specified Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than GND, or greater than VA), the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. Note 4: The absolute maximum junction temperature (TJmax) for this device is 175°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms. Note 6: The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not damage this device. However, errors in the conversion result can occur if any input goes above VA or below GND by more than 100 mV. For example, if VA is 2.7 VDC, ensure that −100 mV ≤ input voltages ≤2.8 VDC to ensure accurate conversions. 30018004 Note 7: To guarantee accuracy, it is required that VA be well bypassed. Note 8: Typical figures are at TJ = 25°C, and represent most likely parametric norms. Note 9: This parameter is guaranteed by design and/or characterization and is not tested in production. Note 10: Maximum Output Current may not exceed 10 mA. At VDD = 5.5 V the minimum external resistive load can be no less than 550 Ω, (360 Ω at VDD = 3.6 V). Note 11: These parameters are worse case drift. Deltas are performed at room temperature Post OP Life. All other parameters no Deltas are required. Note 12: Pre and post irradiation limits are identical to those listed in the “DC Parameters” and “AC and Timing Characteristics” tables, except as listed in the “Radiation Electrical Characteristics” table. When performing post irradiation electrical measurements for any RHA level, TA = +25°C. See section 3.0 for dose rate and test conditions. www.national.com 8 DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB, which is VREF / 4096 = VA / 4096. DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the data bus. FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (FFFh) loaded into the DAC and the value of VA x 4095 / 4096. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and FullScale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error. GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register changes. It is specified as the area of the glitch in nanovolt-seconds. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line through the input to output transfer function. The deviation of any given code from this straight line is measured from the center of that code value. The end point method is used. INL for this product is specified over a limited range, per the Electrical Tables. LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value is LSB = VREF / 2n where VREF is the supply voltage for this product, and "n" is the DAC resolution in bits, which is 12 for the DAC121S101. 9 www.national.com DAC121S101QML MAXIMUM LOAD CAPACITANCE is the maximum capacitance that can be driven by the DAC with output stability maintained. MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when the input code increases. MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is 1/2 of VA. POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from the power supply. The difference between the supply and output currents is the power consumed by the device without a load. SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is updated. WAKE-UP TIME is the time for the output to exit power-down mode. This is the time measured from the falling edge of 16th SCLK pulse to when the output voltage deviates from the power-down voltage of 0 V. ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 000h has been entered. Specification Definitions DAC121S101QML Transfer Characteristic 30018005 FIGURE 1. Input / Output Transfer Characteristic Timing Diagram 30018006 FIGURE 2. DAC121S101 Timing www.national.com 10 fSCLK = 20 MHz, TA = 25C, Input Code Range 48 to 4047, unless otherwise stated DNL at VA = 2.7V DNL at VA = 5.5V 30018052 30018053 INL at VA = 2.7V INL at VA = 5.5V 30018054 30018055 DNL vs. VA INL vs. VA 30018022 30018023 11 www.national.com DAC121S101QML Typical Performance Characteristics DAC121S101QML 2.7V DNL vs. fSCLK 5.5V DNL vs. fSCLK 30018050 30018051 2.7V DNL vs. Clock Duty Cycle 5.5V DNL vs. Clock Duty Cycle 30018056 30018057 2.7V DNL vs. Temperature 5.5V DNL vs. Temperature 30018026 www.national.com 30018027 12 DAC121S101QML 2.7V INL vs. fSCLK 5.5V INL vs. fSCLK 30018028 30018029 2.7V INL vs. Clock Duty Cycle 5.5V INL vs. Clock Duty Cycle 30018030 30018031 2.7V INL vs. Temperature 5.5V INL vs. Temperature 30018032 30018033 13 www.national.com DAC121S101QML Zero Code Error vs. fSCLK Zero Code Error vs. Temperature 30018036 30018034 Full-Scale Error vs. fSCLK Full-Scale Error vs. Temperature 30018039 30018037 Supply Current vs. VA Supply Current vs. Temperature 30018045 30018044 www.national.com 14 DAC121S101QML 5V Glitch Response Power-On Reset 30018046 30018047 3V Wake-Up Time 5V Wake-Up Time 30018048 30018049 15 www.national.com DAC121S101QML 1.3 OUTPUT AMPLIFIER The output buffer amplifier is a rail-to-rail type, providing an output voltage range of 0V to VA. All amplifiers, even rail-torail types, exhibit a loss of linearity as the output approaches the supply rails (0V and VA, in this case). For this reason, linearity is specified over less than the full output range of the DAC. The output capabilities of the amplifier are described in the Electrical Tables. 1.0 Functional Description 1.1 DAC SECTION The DAC121S101 is fabricated on a CMOS process with an architecture that consists of switches and a resistor string that are followed by an output buffer. The power supply serves as the reference voltage. The input coding is straight binary with an ideal output voltage of: 1.4 SERIAL INTERFACE The three-wire interface is compatible with SPI, QSPI and MICROWIRE, as well as most DSPs. See the Timing Diagram for information on a write sequence. A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the DIN line is clocked into the 16bit serial input register on the falling edges of SCLK. On the 16th falling clock edge, the last data bit is clocked in and the programmed function (a change in the mode of operation and/ or a change in the DAC register contents) is executed. At this point the SYNC line may be kept low or brought high. In either case, it must be brought high for the minimum specified time before the next write sequence as a falling edge of SYNC can initiate the next write cycle. Since the SYNC and DIN buffers draw more current when they are high, they should be idled low between write sequences to minimize power consumption. VOUT = VA x (D / 4096) where D is the decimal equivalent of the binary code that is loaded into the DAC register and can take on any value between 0 and 4095. 1.2 RESISTOR STRING The simplified resistor string is shown in Figure 3. Conceptually, this string consists of 4096 equal valued resistors with a switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register determines which switch is closed, connecting the proper node to the amplifier. This configuration guarantees that the DAC is monotonic. 1.5 INPUT SHIFT REGISTER The input shift register, Figure 4, has sixteen bits. The first two bits are "don't cares" and are followed by two bits that determine the mode of operation (normal mode or one of three power-down modes). The contents of the serial input register are transferred to the DAC register on the sixteenth falling edge of SCLK. See Timing Diagram, Figure 2. 30018007 FIGURE 3. DAC Resistor String 30018008 FIGURE 4. Input Register Contents www.national.com 16 1.6 POWER-ON RESET The power-on reset circuit controls the output voltage during power-up. Upon application of power the DAC register is filled with zeros and the output voltage is 0 Volts and remains there until a valid write sequence is made to the DAC. 30018009 FIGURE 5. ADSP-2101/2103 Interface 2.1.2 80C51/80L51 Interface A serial interface between the DAC121S101 and the 80C51/80L51 microcontroller is shown in Figure 6. The SYNC signal comes from a bit-programmable pin on the microcontroller. The example shown here uses port line P3.3. This line is taken low when data is to transmitted to the DAC121S101. Since the 80C51/80L51 transmits 8-bit bytes, only eight falling clock edges occur in the transmit cycle. To load data into the DAC, the P3.3 line must be left low after the first eight bits are transmitted. A second write cycle is initiated to transmit the second byte of data, after which port line P3.3 is brought high. The 80C51/80L51 transmit routine must recognize that the 80C51/80L51 transmits data with the LSB first while the DAC121S101 requires data with the MSB first. 1.7 POWER-DOWN MODES The DAC121S101 has four modes of operation. These modes are set with two bits (DB13 and DB12) in the control register. TABLE 1. Modes of Operation Operating Mode DB13 DB12 0 0 Normal Operation 0 1 Power-Down with 5kΩ to GND 1 0 Power-Down with 100kΩ to GND 1 1 Power-Down with Hi-Z When both DB13 and DB12 are 0, the device operates normally. For the other three possible combinations of these bits the supply current drops to its power-down level and the output is pulled down with either a 5kΩ or a 100kΩ resistor, or is in a high impedance state, as described in Table 1. The bias generator, output amplifier, the resistor string and other linear circuitry are all shut down in any of the powerdown modes. Minimum power consumption is achieved in the power-down mode with SCLK disabled and SYNC and DIN idled low. 30018010 FIGURE 6. 80C51/80L51 Interface 2.1.3 68HC11 Interface A serial interface between the DAC121S101 and the 68HC11 microcontroller is shown in Figure 7. The SYNC line of the DAC121S101 is driven from a port line (PC7 in the figure), similar to the 80C51/80L51. The 68HC11 should be configured with its CPOL bit as a zero and its CPHA bit as a one. This configuration causes data on the MOSI output to be valid on the falling edge of SCLK. PC7 is taken low to transmit data to the DAC. The 68HC11 transmits data in 8-bit bytes with eight falling clock edges. Data is transmitted with the MSB first. PC7 must remain low after the first eight bits are transferred. A second write cycle is initiated to transmit the second byte of data to the DAC, after which PC7 should be raised to end the write sequence. 2.0 Applications Information The simplicity of the DAC121S101 implies ease of use. However, it is important to recognize that any data converter that utilizes its supply voltage as its reference voltage will have essentially zero PSRR (Power Supply Rejection Ratio). Therefore, it is necessary to provide a noise-free supply voltage to the device. 2.1 DSP/MICROPROCESSOR INTERFACING Interfacing the DAC121S101 to microprocessors and DSPs is quite simple. The following guidelines are offered to hasten the design process. 2.1.1 ADSP-2101/ADSP2103 Interfacing Figure 5 shows a serial interface between the DAC121S101 and the ADSP-2101/ADSP2103. The DSP should be set to operate in the SPORT Transmit Alternate Framing Mode. It is programmed through the SPORT control register and should be configured for Internal Clock Operation, Active Low Framing and 16-bit Word Length. Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled. 30018011 FIGURE 7. 68HC11 Interface 2.1.4 Microwire Interface Figure 8 shows an interface between a Microwire compatible device and the DAC121S101. Data is clocked out on the rising edges of the SCLK signal. 17 www.national.com DAC121S101QML Normally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the shift register is reset and the write sequence is invalid. The DAC register is not updated and there is no change in the mode of operation or in the output voltage. DAC121S101QML 30018012 FIGURE 8. Microwire Interface 2.2 USING REFERENCES AS POWER SUPPLIES Recall the need for a quiet supply source for devices that use their power supply voltage as a reference voltage. Since the DAC121S101 consumes very little power, a reference source may be used as the supply voltage. The advantages of using a reference source over a voltage regulator are accuracy and stability. Some low noise regulators can also be used for the power supply of the DAC121S101. Listed below are a few power supply options for the DAC121S101. 30018014 FIGURE 10. The LM4050 as a power supply The minimum resistor value in the circuit of Figure 10 should be chosen such that the maximum current through the LM4050 does not exceed its 15 mA rating. The conditions for maximum current include the input voltage at its maximum, the LM4050 voltage at its minimum, the resistor value at its minimum due to tolerance, and the DAC121S101 draws zero current. The maximum resistor value must allow the LM4050 to draw more than its minimum current for regulation plus the maximum DAC121S101 current in full operation. The conditions for minimum current include the input voltage at its minimum, the LM4050 voltage at its maximum, the resistor value at its maximum due to tolerance, and the DAC121S101 draws its maximum current. These conditions can be summarized as 2.2.1 LM4130 The LM4130 reference, with its 0.05% accuracy over temperature, is a good choice as a power source for the DAC121S101. Its primary disadvantage is the lack of 3 V and 5 V versions. However, the 4.096 V version is useful if a 0 to 4.095 V output range is desirable or acceptable. Bypassing the LM4130 VIN pin with a 0.1 µF capacitor and the VOUT pin with a 2.2 µF capacitor will improve stability and reduce output noise. The LM4130 comes in a space-saving 5-pin SOT23. R(min) = ( VIN(max) − VZ(min) / (IA(min) + IZ(max)) and R(max) = ( VIN(min) − VZ(max) / (IA(max) + IZ(min) ) where V Z(min) and VZ(max) are the nominal LM4050 output voltages ± the LM4050 output tolerance over temperature, IZ (max) is the maximum allowable current through the LM4050, IZ(min) is the minimum current required by the LM4050 for proper regulation, IA(max) is the maximum DAC121S101 supply current, and IA(min) is the minimum DAC121S101 supply current. 30018013 FIGURE 9. The LM4130 as a power supply 2.2.3 LP3985 The LP3985 is a low noise, ultra low dropout voltage regulator with a 3% accuracy over temperature. It is a good choice for applications that do not require a precision reference for the DAC121S101. It comes in 3.0V, 3.3V and 5V versions, among others, and sports a low 30 µV noise specification at low frequencies. Since low frequency noise is relatively difficult to filter, this specification could be important for some applications. The LP3985 comes in a space-saving 5-pin SOT23 and 5-bump micro SMD packages. 2.2.2 LM4050 Available with accuracy of 0.44%, the LM4050 shunt reference is also a good choice as a power regulator for the DAC121S101. It does not come in a 3 Volt version, but 4.096 V and 5 V versions are available. It comes in a space-saving 3-pin SOT23. www.national.com 18 DAC121S101QML 30018015 30018017 FIGURE 11. Using the LP3985 regulator FIGURE 13. Bipolar Operation An input capacitance of 1.0µF without any ESR requirement is required at the LP3985 input, while a 1.0µF ceramic capacitor with an ESR requirement of 5mΩ to 500mΩ is required at the output. Careful interpretation and understanding of the capacitor specification is required to ensure correct device operation. The output voltage of this circuit for any code is found to be VO = (VA x (D / 4096) x ((R1 + R2) / R1) - VA x R2 / R1) where D is the input code in decimal form. With VA = 5V and R1 = R2, VO = (10 x D / 4096) - 5V 2.2.4 LP2980 The LP2980 is an ultra low dropout regulator with a 0.5% or 1.0% accuracy over temperature, depending upon grade. It is available in 3.0V, 3.3V and 5V versions, among others. A list of rail-to-rail amplifiers suitable for this application are indicated in Table 2. TABLE 2. Some Rail-to-Rail Amplifiers AMP PKGS Typ VOS Typ ISUPPLY LMC7111 DIP-8 SOT23-5 0.9 mV 25 µA LM7301 SO-8 SOT23-5 0.03 mV 620 µA LM8261 SOT23-5 0.7 mV 1 mA 2.4 LAYOUT, GROUNDING, AND BYPASSING For best accuracy and minimum noise, the printed circuit board containing the DAC121S101 should have separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes. Both of these planes should be located in the same board layer. There should be a single ground plane. A single ground plane is preferred if digital return current does not flow through the analog ground area. Frequently a single ground plane design will utilize a "fencing" technique to prevent the mixing of analog and digital ground current. Separate ground planes should only be utilized when the fencing technique is inadequate. The separate ground planes must be connected in one place, preferably near the DAC121S101. Special care is required to guarantee that digital signals with fast edge rates do not pass over split ground planes. They must always have a continuous return path below their traces. The DAC121S101 power supply should be bypassed with a 10µF and a 0.1µF capacitor as close as possible to the device with the 0.1µF right at the device supply pin. The 10µF capacitor should be a tantalum type and the 0.1µF capacitor should be a low ESL, low ESR type. The power supply for the DAC121S101 should only be used for analog circuits. Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the board. The clock and data lines should have controlled impedances. 30018016 FIGURE 12. Using the LP2980 regulator Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor must be at least 1.0µF over temperature, but values of 2.2µF or more will provide even better performance. The ESR of this capacitor should be within the range specified in the LP2980 data sheet. Surface-mount solid tantalum capacitors offer a good combination of small size and ESR. Ceramic capacitors are attractive due to their small size but generally have ESR values that are too low for use with the LP2980. Aluminum electrolytic capacitors are typically not a good choice due to their large size and have ESR values that may be too high at low temperatures. 2.3 BIPOLAR OPERATION The DAC121S101 is designed for single supply operation and thus has a unipolar output. However, a bipolar output may be obtained with the circuit in Figure 13. This circuit will provide an output voltage range of ±5 Volts. A rail-to-rail amplifier should be used if the amplifier supplies are limited to ±5V. 19 www.national.com DAC121S101QML 3.0 Radiation Environments 3.2 Single Event Latch-Up and Functional Interrupt Careful consideration should be given to environmental conditions when using a product in a radiation environment. One time single event latch-up (SEL) and single event functional interrupt (SEFI) testing was preformed according to EIA/JEDEC Standard, EIA/JEDEC57. The linear energy transfer threshold (LETth) shown in the Key Specifications table on the front page is the maximum LET tested. A test report is available upon request. 3.1 Total Ionizing Dose Radiation hardness assured (RHA) products are those part numbers with a total ionizing dose (TID) level specified in the Ordering Information table on the front page. Testing and qualification of these products is done on a wafer level according to MIL-STD-883G, Test Method 1019.7, Condition A and the “Extended room temperature anneal test” described in section 3.11 for application environment dose rates less than 0.027 rad(Si)/s. Wafer level TID data is available with lot shipments. www.national.com 3.3 Single Event Upset A report on single event upset (SEU) is available upon request. 20 Date Relased Revision Section 05/05/08 A Initial Release 08/14/08 B 07/15/09 05/06/2010 Changes New Product Data Sheet Release Ordering Information Table Removed SMD reference. Added DAC121S101WGMLS NSPN . Revision A will be Archived. C Ordering Information Table, AC and Timing Electrical Characteristics Added SMD reference, removed MLS device. Changed following parameter limits from Max to Min tH, tL, tSUCL tSUD, tDHD, tCS, tSYNC, tSUCL limit from −21 to 0, Added Delta Parameters. Added subgroups to fSCLK, Removed the typical limits. Changed paragraph's 1.7 and 3.0 section. Revision B will be Archived D Added reference to MPR and CVAL NSPN, Ordering Information Table, Note Section, verbiage to Note 12, Per DSCC recommendation Operating Life Test Delta Table and delta limits for Supply Current. Change to para 3.1, Section 3.0 Radiation Environments 0.16 rad(Si)/s to 0.027 rad(Si)/s. Revision C will be Archived 21 www.national.com DAC121S101QML Revision History DAC121S101QML Physical Dimensions inches (millimeters) unless otherwise noted 10-Pin Ceramic SOIC NS Package Number WG10A www.national.com 22 DAC121S101QML Notes 23 www.national.com DAC121S101QML 12-Bit Micro Power Digital-to-Analog Converter with Rail-to-Rail Output Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage References www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Applications & Markets www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise® Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic PLL/VCO www.national.com/wireless www.national.com/training PowerWise® Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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