NSC LMP8358MAX

LMP8358
Zero-Drift, Programmable Instrumentation Amplifier with
Diagnostics
General Description
Features
The LMP8358 is a precision programmable-gain instrumentation amplifier in National's LMP® precision amplifier family.
Its gain can be programmed to 10, 20, 50, 100, 200, 500, or
1000 through an SPI-compatible serial interface or through a
parallel interface. Alternatively, its gain can be set to an arbitrary value using two external resistors. The LMP8358 uses
patented techniques to measure and continuously correct its
input offset voltage, eliminating offset drift over time and temperature and the effect of 1/f noise. Its ground-sensing CMOS
input features a high CMRR and low input bias currents. It is
capable of sensing differential input voltages in a commonmode range that extends from 100mV below the negative
supply to 1.4V below the positive supply, making it an ideal
solution for interfacing with ground-referenced sensors, supply-referenced sensor bridges, and any other application requiring precision and long-term stability. Additionally, the
LMP8358 includes fault detection circuitry to detect open and
shorted inputs and deteriorating connections to the signal
source. Other features that make the LMP8358 a versatile
solution for many applications are its rail-to-rail output, low
input voltage noise and high gain-bandwidth product.
Typical Values unless otherwise noted, TA = 25°C
2.7V to 5.5V
■ Supply voltage
1.8 mA
■ Supply current
0.15%
■ Max gain error
16 ppm/°C
■ Max gain drift
110 dB
■ Min CMRR
10 µV
■ Max offset voltage
50 nV/°C
■ Max offset voltage drift
8 MHz
■ GBW (gain = 10)
100 ppm
■ Max non-linearity
−40°C to 125°C
■ Operating temperature range
■ Input fault detection
■ SPI or pin configurable modes
92 dB
■ EMIRR at 1.8GHz
■ 14-Pin SOIC and 14-Pin TSSOP Package
Applications
■
■
■
■
■
Bridge sensor amplifier
Thermopile amplifier
Portable instrumentation
Medical instrumentation
Precision low-side current sensing
Typical Application
300454g1
LMP® is a registered trademark of National Semiconductor Corporation.
© 2010 National Semiconductor Corporation
300454
www.national.com
LMP8358 Zero-Drift, Programmable Instrumentation Amplifier with Diagnostics
May 5, 2010
LMP8358
Storage Temperature Range
−65°C to 150°C
Junction Temperature (Note 4)
150°C
For soldering specifications:
see product folder at www.national.com and
www.national.com/ms/MS/MS-SOLDERING.pdf
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Tolerance (Note 2)
Human Body Model
Machine Model
Charge Device
VIN Differential (V+IN − V−IN)
Output Short Circuit Duration (Note 3)
Any pin relative to V−
+IN, −IN, OUT Pins
+IN, −IN Pins
2kV
200V
1kV
VS
Operating Ratings
(Note 1)
Temperature Range
Supply Voltage (VS = V+ – V−)
VIN Differential (V+IN − V−IN)
−40°C to 125°C
2.7V to 5.5V
±100mV
Package Thermal Resistance (θJA (Note 4)
14-Pin SOIC
14-Pin TSSOP
6V, −0.3V
V+ +0.3V, V− −0.3V
±10 mA
145°C/W
135°C/W
3.3V Electrical Characteristics
Unless otherwise specified, all limits are guaranteed for TA = 25°C. V+ = 3.3V , V− = 0V, VREF = V+/2, VCM = V+/2, RL = 10 kΩ to
VREF, CL = 10 pF; Serial Control Register: G[2:0] = 110b (Gain = 1000x), COMP[2:0] = 000b, MUX[1:0] = 00b, POL, SHDN, FILT,
PIN = 0b, CUR[2:0] = 000b. Boldface limits apply at the temperature extremes.
Symbol
VOS
TCVOS
Parameter
Input Offset Voltage
Conditions
Min
Typ
Max
(Note 6) (Note 5) (Note 6)
VCM = V+/2
1
10
15
VCM = 0V
1
10
15
Input Offset Voltage Temperature Drift VCM = V+/2
(Note 8)
VCM = 0V
50
50
CMRR
Common Mode Rejection Ratio
V− − 0.1V ≤ VCM ≤ V+ − 1.4V
110
105
CMVR
Common Mode Voltage Range
CMRR ≥ 110 dB
−0.1
+ 0.1V ≤ VREFF ≤
139
V−
PSRR
Power supply Rejection Ratio
2.7V ≤ V+ ≤ 5.5V
EMIRR
Electro Magnetic Interference
Rejection Ratio
+IN / −IN, VRF = 100 mVP, f = 900 MHz
83
+IN / −IN, VRF = 100 mVP, f = 1800 MHz
93
V+
− 1.4V
110
105
145
112
105
138
ZINDM
Differential Input Impedance
50||1
ZINCM
Common Mode Input Impedance
50||1
VINDM
Differential Mode Input Voltage
IB
Input Bias Current
IOS
Input Offset Current
en
Input Voltage Noise Density
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nV/°C
V
dB
dB
dB
MΩ ‖ pF
MΩ ‖ pF
±100
mV
0.006
1.2
2
nA
0.1
112
pA
Gain = 10, f = 1 kHz
27
Gain = 20, f = 1 kHz
31
Gain = 50, f = 1 kHz
28
Gain = 100, f = 1 kHz
27
Gain = 200, f = 1 kHz
28
Gain = 500, f = 1 kHz
28
Gain = 1000, f = 1 kHz
27
Gain = External, f = 1 kHz
27
2
µV
dB
1.9
VREFRR VREF Rejection Ratio
Units
nV/
en
Parameter
Input Voltage Noise
Conditions
Min
Typ
Max
(Note 6) (Note 5) (Note 6)
Gain = 10, 0.1 Hz < f < 10 Hz
0.9
Gain = 20, 0.1 Hz < f < 10 Hz
0.6
Gain = 50, 0.1 Hz < f < 10 Hz
0.6
Gain = 100, 0.1 Hz < f < 10 Hz
0.7
Gain = 200, 0.1 Hz < f < 10 Hz
0.6
Gain = 500, 0.1 Hz < f < 10 Hz
0.6
Gain = 1000, 0.1 Hz < f < 10 Hz
0.6
Units
µVPP
Gain = External, 0.1 Hz < f < 10 Hz
0.6
In
Input Current Noise Density
Gain = 100, f = 1 kHz
0.5
GE
Gain Error
Gain = 10, 20, 50, 100, 200, 500
VOUT = VREF + 1V and VOUT = VREF − 1V
0.03
0.1
0.15
%
GE
Gain Error
Gain = 1000
VOUT = VREF + 1V and VOUT = VREF − 1V
0.03
0.15
0.25
%
GE
Gain Error Contribution from Chip
VOUT = VREF + 1V and VOUT = VREF − 1V
0.03
Gain Error Temperature Coefficient
For all gain settings (internal and
external), VOUT = VREF + 1V and
VOUT = VREF − 1V
3
16
ppm/°C
3.3
100
ppm
NL
Non-Linearity
GBW
Gain Bandwidth
BW
SR
ts
−3 dB Bandwidth
Slew Rate
(Note 7)
0.01% Settling Time
COMP[2:0] =000b, Gain > 10
8
COMP[2:0] = 001b, Gain > 30
24
COMP[2:0] = 010b, Gain > 200
80
COMP[2:0] = 011b, Gain > 300
240
COMP[2:0] = 1xxb, Gain > 1
0.8
Gain = 10, COMP[2:0] = 000b
900
Gain = 10, COMP[2:0] = 1xxb
70
Gain = 20, COMP[2:0] = 000b
400
Gain = 20, COMP[2:0] = 1xxb
37
Gain = 50, COMP[2:0] = 001b
490
Gain = 50, COMP[2:0] = 1xxb
16
Gain = 100, COMP[2:0] = 010b
680
Gain = 100, COMP[2:0] = 1xxb
8
Gain = 200, COMP[2:0] = 010b
195
Gain = 200, COMP[2:0] = 1xxb
4
Gain = 500, COMP[2:0] = 011b
130
Gain = 500, COMP[2:0] = 1xxb
1.5
Gain = 1000, COMP[2:0] = 011b
89
Gain = 1000, COMP[2:0] = 1xxb
0.8
COMP[2:0] = 000b, 10% to 90% of Step,
VOUT = 2 VPP
1.6
COMP[2:0] = 001b, 10% to 90% of Step,
VOUT = 2 VPP
3.8
COMP[2:0] = 010b, 10% to 90% of Step,
VOUT = 2 VPP
6.5
COMP[2:0] = 011b, 10% to 90% of Step,
VOUT = 2 VPP
9.3
COMP[2:0] = 1xxb, 10% to 90% of Step,
VOUT = 2 VPP
0.17
2 V Step, CL = 10 pF, COMP[2:0] = 011b
4
3
pA/
%
MHz
kHz
V/µs
µs
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LMP8358
Symbol
LMP8358
Symbol
VOUT
Parameter
Output Voltage Swing High
Output Voltage Swing Low
IOUT
IS
Conditions
Min
Typ
Max
(Note 6) (Note 5) (Note 6)
RL = 2 kΩ to V+/2
32
40
RL = 10 kΩ to V+/2
12
17
RL > 1 MΩ to V+/2
7
12
RL = 2 kΩ to V+/2
28
38
RL = 10 kΩ to V+/2
12
17
RL > 1 MΩ to V+/2
8
13
PSE
mV from
bottom
rail
VOUT tied to V+/2
21
15
28
Output Current Sinking
VOUT tied to V+/2
32
25
37
Supply Current
Fault detection off, VIN DIFF = 0V
1.8
2.1
mA
Fault detection on, VIN DIFF = 0V
1.9
2.2
mA
0.014
1
µA
Turn-on time from Shutdown
Prescaler Error (Offset + Gain Error)
Fault Detection: Test Current
mA
85
VCM =
V+/2
5
Prescaler Gain Factor
ITEST
mV from
top rail
Output Current Sourcing
in Shutdown
TSD_ON
Units
µs
15
0.02
Setting 1 (CUR[2:0] = 001b), VCM < V+ −
1.15V
10
Setting 2 (CUR[2:0] = 010b), VCM < V+ −
1.15V
100
Setting 3 (CUR[2:0] = 011b), VCM < V+ −
1.15V
1
Setting 4 (CUR[2:0] = 100b), VCM < V+ −
1.15V
10
Setting 5 (CUR[2:0] = 101b), VCM < V+ −
1.15V
100
mV
V/V
nA
nA
µA
µA
µA
5.0V Electrical Characteristics
Unless otherwise specified, all limits are guaranteed for TA = 25°C. V+ = 5.0V , V− = 0V, VREF = V+/2, VCM = V+/2, RL = 10 kΩ to
VREF, CL = 10 pF; Serial Control Register: G[2:0] = 110b (Gain = 1000x), COMP[2:0] = 000b, MUX[1:0] = 00b, POL, SHDN, FILT,
PIN = 0b, CUR[2:0] = 000b. Boldface limits apply at the temperature extremes.
Symbol
VOS
TCVOS
Parameter
Input Offset Voltage
Conditions
Min
Typ
Max
(Note 6) (Note 5) (Note 6)
VCM = V+/2
0.9
10
15
VCM = 0V
0.9
10
15
Input Offset Voltage Temperature Drift VCM = V+/2
(Note 8)
VCM = 0V
50
50
V− − 0.1V ≤ VCM ≤ V+ − 1.4V
116
105
142
VREFRR VREF Rejection Ratio
V− + 0.1V ≤ VREFF ≤ V+ − 1.4V
115
105
150
CMVR
CMRR ≥ 115 dB
−0.1
CMRR
Common Mode Rejection Ratio
Common Mode Voltage Range
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4
Units
µV
nV/°C
dB
dB
3.6
V
Parameter
Conditions
Min
Typ
Max
(Note 6) (Note 5) (Note 6)
PSRR
Power supply Rejection Ratio
2.7V ≤ V+ ≤ 5.5V
EMIRR
Electro Magnetic Interference
Rejection Ratio
+IN / −IN, VRF = 100 mVP, f = 900 MHz
83
+IN / −IN, VRF = 100 mVP, f = 1800 MHz
93
112
105
138
Units
dB
dB
ZINDM
Differential Input Impedance
50||1
MΩ ‖ pF
ZINCM
Common Mode Input Impedance
50||1
MΩ ‖ pF
VINDM
Differential Mode Input Voltage
IB
Input Bias Current
IOS
Input Offset Current
en
Input Voltage Noise Density
en
Input Voltage Noise
±100
mV
0.006
1.2
2
nA
0.2
113
pA
Gain = 10, f = 1 kHz
25
Gain = 20, f = 1 kHz
28
Gain = 50, f = 1 kHz
26
Gain = 100, f = 1 kHz
25
Gain = 200, f = 1 kHz
28
Gain = 500, f = 1 kHz
26
Gain = 1000, f = 1 kHz
25
Gain = External, f = 1 kHz
25
Gain = 10, 0.1 Hz < f < 10 Hz
0.7
Gain = 20, 0.1 Hz < f < 10 Hz
0.7
Gain = 50, 0.1 Hz < f < 10 Hz
0.5
Gain = 100, 0.1 Hz < f < 10 Hz
0.6
Gain = 200, 0.1 Hz < f < 10 Hz
0.6
Gain = 500, 0.1 Hz < f < 10 Hz
0.5
Gain = 1000, 0.1 Hz < f < 10 Hz
0.6
nV/
µVPP
Gain = External, 0.1 Hz < f < 10 Hz
0.6
In
Input Current Noise Density
Gain = 100, f = 1 kHz
0.5
GE
Gain Error
Gain = 10, 20, 50, 100, 200, 500
VOUT = VREF + 1V and VOUT = VREF − 1V
0.03
0.1
0.15
%
GE
Gain Error
Gain = 1000
VOUT = VREF + 1V and VOUT = VREF − 1V
0.03
0.15
0.25
%
GE
Gain Error Contribution from chip
VOUT = VREF + 1V and VOUT = VREF − 1V
0.03
Gain Error Temperature Coefficient
For all gain settings (internal and
external), VOUT = VREF + 1V and
VOUT = VREF − 1V
3
16
ppm/°C
3
100
ppm
NL
Non-Linearity
GBW
Gain Bandwidth
COMP[2:0] = 000b, Gain > 10
8
COMP[2:0] = 001b, Gain > 100
24
COMP[2:0] = 010b, Gain > 200
80
COMP[2:0] = 011b, Gain > 500
240
COMP[2:0] = 1xxb,
Gain => 1
0.8
5
pA/
%
MHz
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LMP8358
Symbol
LMP8358
Symbol
BW
SR
Parameter
−3 dB Bandwidth
Slew Rate
(Note 7)
Conditions
Min
Typ
Max
(Note 6) (Note 5) (Note 6)
Gain = 10, COMP[2:0] = 000b
930
Gain = 10, COMP[2:0] = 1xxb
74
Gain = 20, COMP[2:0] = 000b
385
Gain = 20, COMP[2:0] = 1xxb
37
Gain = 50, COMP[2:0] = 001b
460
Gain = 50, COMP[2:0] = 1xxb
16
Gain = 100, COMP[2:0] = 010b
640
Gain = 100, COMP[2:0] = 1xxb
8
Gain = 200, COMP[2:0] = 010b
195
Gain = 200, COMP[2:0] = 1xxb
4
Gain = 500, COMP[2:0] = 011b
130
Gain = 500, COMP[2:0] = 1xxb
1.5
Gain = 1000, COMP[2:0] = 011b
89
Gain = 1000, COMP[2:0] = 1xxb
0.8
COMP[2:0] = 000b, 10% to 90% of Step,
VOUT = 2 VPP
1.7
COMP[2:0] = 001b, 10% to 90% of Step,
VOUT = 2 VPP
5.0
COMP[2:0] = 010b, 10% to 90% of Step,
VOUT = 2 VPP
9.0
COMP[2:0] = 011b, 10% to 90% of Step,
VOUT = 2 VPP
11.0
COMP[2:0] = 1xxb, 10% to 90% of Step,
VOUT = 2 VPP
0.16
4
kHz
V/µs
ts
0.01% Settling Time
2 V Step, CL = 10 pF, COMP[2:0] = 011b
VOUT
Output Voltage Swing High
RL = 2 kΩ to V+/2
52
62
RL = 10 kΩ to V+/2
22
30
RL > 1 MΩ to V+/2
12
17
RL = 2 kΩ to V+/2
42
55
RL = 10 kΩ to V+/2
16
22
RL > 1 MΩ to V+/2
12
17
Output Voltage Swing Low
IOUT
IS
Units
µs
mV from
top rail
mV from
bottom
rail
Output Current Sourcing
VOUT tied to V+/2
23
16
31
Output Current Sinking
VOUT tied to V+/2
34
30
41
Supply Current
Fault detection off, VIN DIFF = 0V
1.8
2.1
mA
Fault detection on, VIN DIFF = 0V
1.9
2.2
mA
0.006
1
µA
8
mV
in Shutdown
TSD_ON
Turn-on time from Shutdown
PSE
Prescaler Error (Offset + Gain Error)
85
VCM = V+/2
5
Prescaler Gain Factor
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mA
0.02
6
µs
V/V
ITEST
Min
Typ
Max
(Note 6) (Note 5) (Note 6)
Units
Setting 1 (CUR[2:0] = 001b), VCM < V+ −
2.25V
10
nA
Setting 2 (CUR[2:0] = 010b), VCM < V+ −
2.25V
100
nA
Setting 3 (CUR[2:0] = 011b), VCM < V+ −
2.25V
1
µA
Setting 4 (CUR[2:0] = 100b), VCM < V+ −
2.25V
10
µA
Setting 5 (CUR[2:0] = 101b), VCM < V+ −
2.25V
100
µA
Parameter
Fault Detection: Test Current
Conditions
Electrical Characteristics (Serial Interface)
Unless otherwise specified, all limits guaranteed for TA = 25°C, V+ − V− ≥ 2.7V, V+ ≥ VHSER/VLPAR, V− ≤ VLSER/VHPAR, VD =
(VHSER/VLPAR) − (VLSER/VHPAR) ≥ 2.5V.
Symbol
Parameter
Conditions
Min
(Note 6)
Typ
(Note 5)
Max
(Note 6)
Units
0.3 × VD
V
VIL
Input Logic Low Threshold
VIH
Input Logic High Threshold
VOL
Output Logic Low Threshold
ISDO = 2mA
VOH
Output Logic High Threshold
ISDO = 2mA
ISDO
Output Source Current, SDO
VD = 3.3V or 5.0V,
CSB = 0V, VOH = V+ – 0.7V
−2
Output Sink Current, SDO
VD = 3.3V or 5.0V,
CSB = 0V, VOL = 1.0V
2
IOZ
Output Tri-state Leakage Current,
SDO
VD = 3.3V or 5.0V,
CSB = VD = 3.3V or 5V
t1
High Period, SCK
(Note 9)
100
ns
t2
Low Period, SCK
(Note 9)
100
ns
t3
Set Up Time, CSB to SCK
(Note 9)
50
ns
t4
Set Up Time, SDI to SCK
(Note 9)
30
ns
t5
Hold Time, SCK to SDI
(Note 9)
10
t6
Prop. Delay, SCK to SDO
(Note 9)
t7
Hold Time, SCK Transition to CSB (Note 9)
Rising Edge
50
ns
t8
CSB Inactive
(Note 9)
50
ns
t9
Prop. Delay, CSB to SDO Active
(Note 9)
50
ns
t10
Prop. Delay, CSB to SDO Inactive (Note 9)
50
ns
t11
Hold Time, SCK Transition to CSB (Note 9)
Falling Edge
10
tr/tf
Signal Rise and Fall Times
1.5
0.7 × VD
V
0.2
V
VD − 0.2V
mA
±1
ns
60
(Note 9)
µA
ns
ns
5
ns
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but for which specific performance is not guaranteed. For guaranteed specifications and the test conditions, see Electrical Characteristics.
Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22–A115–A (ESD MM std. of JEDEC). FieldInduced Charge-Device Model, applicable std. JESD22–C101–C (ESD FICDM std. of JEDEC).
Note 3: The short circuit test is a momentary test which applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated
ambient temperature can exceed the maximum allowable junction temperature of 150°C.
Note 4: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
Note 5: Typical Values indicate the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will
also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material.
Note 6: All limits are guaranteed by testing or statistical analysis.
7
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LMP8358
Symbol
LMP8358
Note 7: Slew rate is the average of the rising and falling slew rates.
Note 8: The offset voltage average drift is determined by dividing the value of VOS at the temperature extremes by the total temperature change.
Note 9: Load for these tests is shown in the Timing Diagram Test Circuit.
Connection Diagram
14-Pin SOIC/ 14-Pin TSSOP
30045402
Top View
Pin Descriptions
Pin Name
Communication Mode
Serial
Parallel
+IN
Positive Input
−IN
Negative Input
REFS
Reference Sense
REFF
Reference Force
FB
Feedback
OUT
Output
V+
Positive Supply
VHSER/VLPAR
Set High
V−
Set Low
Negative Supply
VLSER/VHPAR
Set Low
Set High
CSB/SHDN
Chip Select
Shutdown (Active High)
SCK/G2
Serial Clock
Gain (MSB)
SDI/G1
Serial Data In
Gain
SDO/G0
Serial Data Out
Gain (LSB)
Ordering Information
Package
14-Pin SOIC
14-Pin TSSOP
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Part Number
LMP8358MA
LMP8358MAX
LMP8358MT
LMP8358MTX
Package Marking
Transport Media
55 Units/Rail
LMP8358MA
2.5k Units Tape and Reel
94 Units/Rail
LMP8358MT
2.5k Units Tape and Reel
8
NSC Drawing
M14A
MTC14
LMP8358
Block Diagram
30045406
14-Pin SOIC/ 14-Pin TSSOP
9
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LMP8358
Timing Diagrams
30045403
SPI Timing Diagram
30045453
Timing Diagram Test Circuit
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10
V+ = 3.3V and TA = 25°C unless otherwise noted.
Gain vs. Frequency for Various COMP Settings
Gain vs. Frequency for Various COMP Settings
300454c2
300454c3
Gain vs. Frequency for Various COMP Settings
Gain vs. Frequency for Various Cap Loads
300454c5
300454c4
Gain vs. Frequency for Various Cap Loads
Gain Error vs. Common Mode Voltage, VS = 5V
300454c6
300454f4
11
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LMP8358
Typical Performance Characteristics
LMP8358
Gain Error vs. Common Mode Voltage, VS = 3.3V
Gain Error Distribution, Gain = 10, VS = 3.3V
300454g4
300454f5
Gain Error Distribution, Gain = 100, VS = 3.3V
Gain Error Distribution, Gain = 1000, VS = 3.3V
300454g5
300454g6
VOS Distribution, VS = 3.3V
VOS Distribution, VS = 5.0V
300454g2
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300454g3
12
LMP8358
TCVOS Distribution, VS = 3.3V
TCVOS Distribution, VS = 5V
300454g7
300454g8
VOS vs. VCM, VS = 3.3V
VOS vs. VCM, VS = 3.3V
300454e6
300454e5
VOS vs. VCM, VS = 5.0V
VOS vs. VCM, VS = 5.0V
300454e7
300454e8
13
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LMP8358
VOS vs. VREF, VS = 3.3V
CMRR vs. Frequency
300454d3
300454g9
CMRR vs. Frequency
PSRR vs. Frequency
300454d8
300454d9
Voltage Noise vs. Time
Voltage Noise vs. Frequency
300454d2
300454c9
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14
Small Signal Step Response for Various COMP Settings
300454d4
300454d5
Large Signal Step Response for Various COMP Settings
Large Signal Step Response for Various COMP Settings
300454d6
300454d7
Positive Overshoot vs. CLOAD
Supply Current vs. Supply Voltage
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LMP8358
Small Signal Step Response for Various COMP Settings
LMP8358
Input Bias Current vs. VCM, VS = 3.3V
Input Bias Current vs. VCM, VS = 5.0V
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THD+N vs. Frequency
THD+N vs. VOUT
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ITEST1 vs. VCM
ITEST2 vs. VCM
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16
LMP8358
ITEST3 vs. VCM
ITEST4 vs. VCM
300454f8
300454f7
ITEST5 vs. VCM
Output Swing High vs. Supply Voltage
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Output Swing Low vs. Supply Voltage
EMIRR IN+ vs. Frequency
300454f3
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LMP8358
auto-zeroed the other stage provides the path between the
input pins and the output. The auto-zeroing decreases offset,
offset drift, and 1/f noise while the ping-pong architecture provides a continuous path between the input and the output. As
with all devices that use auto-zeroing, care must be taken with
the signal frequency used with the device. On-chip continuous auto-zero correction circuitry eliminates the 1/f noise and
significantly reduces the offset voltage and offset voltage drift;
all of which are very low-frequency events. For slow-changing
sensor signals, below 2kHz, this correction is transparent.
Higher-frequency signals as well as fast changing edges will
show a settling and ramping time lasting about 1μs. Like all
auto-zeroing devices, if the input frequency is above the autozero frequency, aliasing will occur. This can occur both at the
auto-zeroing frequency of about 12kHz and the ping-pong
frequency of about 50kHz. If needed, a low-pass filter should
be placed on the output of the LMP8358 to filter out this disturbance.
Application Information
INTRODUCTION
The LMP8358 is a precision programmable gain instrumentation amplifier. Its gain can be programmed to 10, 20, 50,
100, 200, 500 or 1000 through an SPI-compatible serial interface or through a parallel interface. Alternatively, its gain
can be set to an arbitrary value using external resistors. Note
that at low gains the dynamic range is limited by the maximum
input differential voltage of ±100mV. The LMP8358 uses
patented techniques to measure and continuously correct its
input offset voltage, eliminating offset drift over time and temperature, and the effect of 1/f noise. Its ground sensing CMOS
input features a high CMRR and low input bias currents. It is
capable of sensing differential input voltages in a commonmode range that extends from 100 mV below the negative
supply to 1.4V below the positive supply, making it an ideal
solution for interfacing with ground-referenced sensors, supply-referenced sensor bridges, and any other application requiring precision and long term stability. Additionally, the
LMP8358 includes fault detection circuitry, so open and shorted inputs can be detected, as well a deteriorating connection
to the signal source. Other features that make the LMP8358
a versatile solution for many applications are: its rail-to-rail
output, low input voltage noise and high gain-bandwidth product.
COMMUNICATION WITH THE PART AND REGISTER
DESCRIPTION
The LMP8358 supports a serial and a parallel digital interface
mode as shown in Figure 1.
Parallel user mode Gain is set using G0, G1 and G2 pins.
The shutdown mode can be activated by
asserting SHDN. Fault detection features are unavailable.
Serial user mode The part is SPI-programmable through
SDI, SCK, SDO and CSB. All features
are available.
TRANSIENT RESPONSE TO FAST INPUTS
The LMP8358 is a current-feedback instrumentation amplifier
that consists of two auto-zeroed input stages. These two input
stages are operated in a ping-pong fashion: as one stage is
30045410
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LMP8358
300454a5
FIGURE 1. (A) Communication with LMP8358 in Parallel Mode (B) Communication with LMP8358 in Serial Mode
Communication Mode Selection
The interface mode is determined by the two interface level
pins VLSER/VHPAR and VHSER/VLPAR.
VLSER/VHPAR < VHSER/
Serial Interface. VLSER=
VLPAR
Logic low level, VHSER =
Logic high level.
VLSER/VHPAR > VHSER/
Parallel interface. VLPAR =
VLPAR
Logic low level, VHPAR =
Logic high level.
Table 1. Function of Digital IO Pins, Parallel Mode
The levels applied to the VLSER/VHPAR and VHSER/VLPAR pins should be between the V+ and V− levels as shown
in Figure 2.
Pin Name
Description
G0
Gain setting (LSB)
G1
Gain setting
G2
Gain setting (MSB)
SHDN
Shutdown (Active High)
VHPAR
Positive logic level
VLPAR
Negative logic level
Table 2. Pin Levels for Setting Gain, Parallel Mode
30045409
FIGURE 2. Communication Mode Selection.
PARALLEL CONTROL INTERFACE MODE
The LMP8358 is put into Parallel Mode by setting VLSER/
VHPAR > VHSER/VLPAR. The register in the LMP8358 does
not control the settings of the LMP8358 in this mode. Gain
and shutdown are set by placing a high or low logic level on
pins 11 (SHDN), 12 (G2), 13 (G1), and 14 (G0), as shown in
Table 1. Function of Digital IO Pins, Parallel Mode and Table
2. Pin Levels for Setting Gain, Parallel Mode. The logic high
and low levels are defined by the voltages on the VLSER/
VHPAR and VHSER/VLPAR pins. See the START UP AND
POWER ON RESET section for power on requirements when
using the parallel mode.
G2
G1 G0 Gain Setting
Bandwidth Compensation
Setting
(Automatically
Set)
0
0
0
10x (power-up
default)
930 kHz
000b
0
0
1
20x
385 kHz
000b
0
1
0
50x
460 kHz
001b
0
1
1
100x
640 kHz
010b
1
0
0
200x
195 kHz
010b
1
0
1
500x
130 kHz
011b
1
1
0
1000x
89 kHz
011b
1
1
1
User defined
800 kHz
1xxb
SERIAL CONTROL INTERFACE MODE
The LMP8358 is put into Serial Mode by setting VLSER/VHPAR < VHSER/VLPAR. In the Serial Mode the LMP8358 can
be programmed by using pins 11 – 14 as shown in Table 3.
Function of Digital IO Pins, Serial Mode and the SPI Timing
Diagram. The LMP8358 contains a 16 bit register which controls the performance of the part. These bits can be changed
using the Serial Mode of communication. The register of the
LMP8358 is shown in Table 4. LMP8358 Register Description, Serial Mode. Immediately after power on the register
should be written with the value needed for the application.
See the START UP AND POWER ON RESET section.
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LMP8358
Table 3. Function of Digital IO Pins, Serial Mode
Bit No
Name
Description
Pin Name
Description
11
PIN
Fault detection pin selection
SDO
Serial Data Out
12
CUR0
Fault detection current setting (LSB)
SDI
Serial Data In
13
CUR1
Fault detection current setting
SCK
Serial Clock
14
CUR2
Fault detection current setting (MSB)
CSB
Chip Select
15
N/A
Unused, set to 0
VLSER
Negative Logic level
VHSER
Positive Logic Level
Serial Control Interface Operation
The LMP8358 gain, bandwidth compensation, shutdown, input options, and fault detection are controlled by an on board
programmable register. Data to be written into the control
register is first loaded into the LMP8358 via the serial interface. The serial interface employs an 16-bit double-buffered
register for glitch-free transitions between settings. Data is
loaded through the serial data input, SDI. Data passing
through the shift register is output through the serial data output, SDO. The serial clock, SCK controls the serial loading
process. All sixteen data bits are required to correctly program
the amplifier. The falling edge of CSB enables the shift register to receive data. The SCK signal must be high during the
falling and rising edge of CSB. Each data bit is clocked into
the shift register on the rising edge of SCK. Data is transferred
from the shift register to the holding register on the rising edge
of CSB. Operation is shown in the SPI Timing Diagram.
The serial control pins can be connected in one of two ways
when two or more LMP8358s are used in an application.
Table 4. LMP8358 Register Description, Serial Mode
Bit No
Name
Description
0
G0
Gain setting (LSB)
1
G1
Gain setting
2
G2
Gain setting (MSB)
3
COMP0
Frequency compensation setting (LSB)
4
COMP1
Frequency compensation setting
5
COMP2
Frequency compensation setting (MSB)
6
MUX0
Input multiplexer selection (LSB)
7
MUX1
Input multiplexer selection (MSB)
8
POL
Input polarity switch
9
SHDN
Shutdown Enable
10
FILT
Enable filtering using external cap
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300454a3
FIGURE 3. Star Configuration for Writing the Same Value Into Each Register
300454a4
FIGURE 4. Star Configuration for Writing Different Values Into Each Register
tions are shown in Figure 5. In this configuration the SDO pin
of each LMP8358 is connected to the SDI pin of the following
LMP8358.
Daisy Chain Configuration
This configuration can be used to program the same or different values in the register of each LMP8358. The connec-
300454a5
FIGURE 5. Daisy Chain Configuration
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LMP8358
After the microcontroller writes, all registers will have the
same value. Using multiple CSB lines as shown in Figure 4
allows different values to be written into each register.
Star Configuration
The configuration shown in Figure 3 can be used if each
LMP8358 will always have the same value in each register.
LMP8358
The following two examples show how the registers are written in the Daisy Chain Configuration.
Tabel 5. If all three LMP8358s need a gain of 100 with a compensation level of 010. (0000 0000 0001 0011)
Register of LMP8358 #1 Register of LMP8358 #2 Register of LMP8358 #3 Notes
Power on
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Default power on state
After first two bytes are 0000 0000 0001 0011
sent
0000 0000 0000 0000
0000 0000 0000 0000
After second two bytes 0000 0000 0001 0011
are sent
0000 0000 0001 0011
0000 0000 0000 0000
After third two bytes
are sent
0000 0000 0001 0011
0000 0000 0001 0011
The data in the register of
LMP8358 #1 is shifted
into the register of
LMP8358 #2, the data in
the register of LMP8358
#2 is shifted into the
register of LMP8358 #3.
0000 0000 0001 0011
Table 6. If LMP8358 #1 needs a gain of 20 (0000 0000 0000 0001), LMP8358 #2 needs a gain of 1000 with a compensation
level of 011 (0000 0000 0001 1110), and LMP8358 #3 needs a gain of 100 with a compenstation level of 010 (0000 0000 0001
0011).
Register of LMP8358 #1 Register of LMP8358 #2 Register of LMP8358 #3 Notes
Power on
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Default power on state
After first two bytes are 0000 0000 0001 0011
sent
0000 0000 0000 0000
0000 0000 0000 0000
After second two bytes 0000 0000 0001 1110
are sent
0000 0000 0001 0011
0000 0000 0000 0000
After third two bytes
are sent
0000 0000 0001 1110
0000 0000 0001 0011
The data in the register of
LMP8358 #1 is shifted
into the register of
LMP8358 #2, the data in
the register of LMP8358
#2 is shifted into the
register of LMP8358 #3
0000 0000 0000 0001
When G[2:0] = 111b in either serial or parallel mode switch
S1 is open and S2 is closed and the LMP8358 gain is set by
external resistors as shown in Figure 6. The gain is:
LMP8358 SETTINGS
Gain (Serial, Parallel)
When the LMP8358 is in Parallel Mode the gain can be set
by applying a high or low level to pins 12 (G2), 13 (G1), and
14 (G0), as shown in Table 2. Pin Levels for Setting Gain,
Parallel Mode. The Frequency Compensation bits are automatically set as shown in Table 2. Pin Levels for Setting Gain,
Parallel Mode to optimize the bandwidth. In Serial Mode the
gain is determined by setting G[2:0] as shown in Table 7. Gain
Setting (Register bits 2:0) and the bandwidth can be changed
using the Frequency Compensation bits in the register.
GAIN = 1 + (Z1/Z2)
When the gain is set by external resistors and COMP[2:0] =
1xxb, a capacitor can be used to implement a noise reduction
low pass filter. See the Filter and External Filter Capacitor
(Serial) section. R1and CFILTER are placed between the OUT
and FB pins. R2 is placed between the FB and REFS pins.
Table 7. Gain Setting (Register bits 2:0)
G2
G1
G0
Gain Setting
0
0
0
10x (power-up default)
0
0
1
20x
0
1
0
50x
0
1
1
100x
1
0
0
200x
1
0
1
500x
1
1
0
1000x
1
1
1
User Defined
300454a6
FIGURE 6. External Gain Set Resistors and Filter
Capacitor
When G[2:0] = 000b to 110b switch S1 is closed and switch
S2 is open as shown in the Block Diagram.
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Table 8. Frequency Compensation (Register bits 5:3)
Bandwidth
Gain\COMP [2:0]
000
001
010
011
1xx
10
930 kHz
n/a
n/a
n/a
74 kHz
20
385 kHz
n/a
n/a
n/a
37 kHz
50
160 kHz
460 kHz
n/a
n/a
16 kHz
100
80 kHz
225 kHz
640 kHz
n/a
8 kHz
200
38 kHz
95 kHz
195 kHz
n/a
4 kHz
500
16 kHz
40 kHz
85 kHz
130 kHz
1.5 kHz
1000
8 kHz
22 kHz
50 kHz
89 kHz
0.8 kHz
User Defined Gain
GBW Product
> 10x
8 MHz
> 30x
24 MHz
> 100x
80 MHz
> 300x
240 MHz
> 1x
0.8 MHz
(For external filter cap)
states shown in Table 9. Input Multiplexer and Polarity (Register bits 8:6).
Input Multiplexer and Polarity Switch (Serial)
The Input Multiplexer Selection bits MUX[1:0] and Polarity bit
POL can be used to set the inputs of the LMP8358 to the
Table 9. Input Multiplexer and Polarity (Register bits 8:6)
MUX1
MUX0
0
0
0
1
1
0
1
1
Diff Input for POL = 0
Diff Input for POL = 1
for example, to compensate for thermocouple voltages, residual offset of the LMP8358, or offsets of the sensor or ADC.
Short Inputs
When MUX[1:0] = 01b and POL = 0b both inputs are connected to the +IN pin of the LMP8358. The –IN pin is left
Polarity Reversal
When MUX[1:0] = 00b and POL = 0b the LMP8358 has the
input of a normal instrumentation amplifier. The input for the
LMP8358 is defined as Gain × (V+IN − V−IN). When POL = 1b,
the input for the LMP8358 is defined as Gain × (V−IN – V+IN).
Polarity reversal can be used to do system level calibration,
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LMP8358
at the selectable gain and compensation settings. Note that
for gains 10X and 20X, the recommended compensation setting is 000b. For the gain setting 50X, compensation settings
may be 000b and 001b. Gain settings 100X and 200X may
use the three bandwidth compensation settings 000b, 001b,
and 010b. At gains of 500X and 1000X, all bandwidth compensation ranges may be used. Note that for lower gains, it is
possible to under compensate the amplifier into instability.
Frequency Compensation (Serial)
The gain-bandwidth compensation is set to one of five levels
under program control. The amount of compensation can be
decreased to maximize the available bandwidth as the gain
of the amplifier is increased. The compensation level is selected by setting bits COMP[2:0] of the control register with
000b, 001b, 010b, 011b, or 1xxb. Table 8. Frequency Compensation (Register bits 5:3) shows the bandwidths achieved
LMP8358
floating. When MUX[1:0] = 01b and POL = 1b both inputs are
connected to the -IN pin of the LMP8358. The +IN pin is left
floating.
Compare Input to VWhen MUX[1:0] = 10b or 11b one external input of the
LMP8358 is floating. The other external input is divided by 50
as shown in Table 9. Input Multiplexer and Polarity (Register
bits 8:6). The internal instrumentation amplifier input that is
not connected to the external pin is connected to V−. With a
scale factor of 1/50 this gives an overall gain of 0.2x, 0.4x, 1x,
2x, 4x, 10x, or 20x depending on what the gain is set to with
G[2:0] bits as shown in Table 10. Overall Gain using G[2:0],
MUX[1:0] and POL.
Table 13. RFILTER Value
Table 10. Overall Gain using G[2:0], MUX[1:0] and POL
G[2:0]
MUX[1:0]
POL = 1b
000b
10b or 11b
0.2
−0.2
001b
10b or 11b
0.4
−0.4
010b
10b or 11b
1
−1
011b
10b or 11b
2
−2
100b
10b or 11b
4
−4
101b
10b or 11b
10
−10
110b
10b or 11b
20
−20
Mode
Active mode
1
Shutdown mode
18.5 kΩ
20
112 kΩ
50
168 kΩ
100
187 kΩ
200
1.12 MΩ
500
1.68 MΩ
1000
1.87 MΩ
User-Defined Gain
External Resistor R1
Table 14. Pin Current Source (Register bit 11)
PIN
Current source is connected to
0
+IN pin
1
−IN pin
The Fault Detection Current bit, CUR[2:0] controls the amount
of current that sent to the input pin as shown in Table 15. Fault
Detection Current Source (Register bits 14:12).
Table 11. Shutdown (Register bit 9)
0
10
Fault Detection Pin and Current Setting (Serial)
The LMP8358 has an internal current source that can be used
to detect faults in the overall system. See the FAULT DETECTION METHODS Section. When PIN = 0b this current
source is connected to the +IN pin. When PIN = 1b the current
source is connected to the −IN pin.
Shutdown Enable (Serial, Parallel)
When the SHDN bit of the LMP8358 register is set to 1b the
part is put into shutdown mode. It will use less than 1μA in this
state.
SHDN
RFILTER Value
The tolerance of the RFILTER value for the pre-defined gains
is about ±3%. If an external filter cap is not used FILT should
be set to 0b to prevent errors related to leakage currents on
the FB pin.
Overall System Gain
POL = 0b
Gain
Table 15. Fault Detection Current Source (Register bits
14:12)
CUR2 CUR1 CUR0
Filter and External Filter Capacitor (Serial)
The FILT bit controls the state of switch S2 shown in the Block
Diagram. When G[2:0] = 000b to 110b, switch S2 will be open
if FILT = 0b and S2 will be closed if FILT = 1b. When G[2:0]
= 111b switch S2 is always closed and does not depend on
the value in the FILT bit.
When FILT = 1b and COMP[2:0] = 1xxb the LMP8358 is unitygain stable and an external filter cap can be applied as shown
in Figure 6. The corner filter of the filter is:
0
0
0
disconnected and powered down *
0
0
1
10 nA
0
1
0
100 nA
0
1
1
1 μA
1
0
0
10 µA
1
0
1
100 µA
1
1
0
disconnected, but powered *
F-3dB = 1/(2πRFILTERCFILTER)
1
1
1
Do Not Use
* Leaving the fault detection current source powered allows it
to switch between current levels faster, particularly when supplying currents less than 1 µA.
RFILTER depends on the gain of the part and is shown inTable
13. RFILTER Value.
Table 12. Filter (Register bit 10)
FILT
Mode
0
No external filter cap used
1
External filter cap used
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300454b5
FIGURE 7. Bridge Connected to the LMP8358 With No Problems
mode voltage at the input pins, use the 1/50 feature by setting
MUX[1:0] to 10b to test the +IN pin or to 11b to test the −IN
pin, POL to 0b, and G[2:0] to 010b for a gain of 50 (0082x or
00C2x). This will give an overall gain of 1 and the output will
read 4V for either MUX setting.
Common Mode Out of Range
Figure 8 shows an example of a degraded connection between the bottom of the bridge and ground. This fault is shown
by the 1.5 kΩ resistor placed between the bridge and ground.
This will raise the common mode at the inputs of the LMP8358
to 4V, which is out of the CMVR. To determine the common
300454b6
FIGURE 8. Degraded Connection Between the Bottom of the Bridge and Ground
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LMP8358
Figure 7 which shows a bridge sensor connected through
some cabling to a supply and the LMP8358. The fault detection methods are described below.
FAULT DETECTION METHODS
Using the Multiplexer, Polarity, and Current features the end
user can detect faults in the system between the sensor and
the LMP8358. These examples will use the set up shown in
LMP8358
of 50, and inject 100µA current by setting CUR[2:0] = 101b
(5082x or 58C2x). Since the input is open the input pin will be
pulled to V+. With an overall gain of 1 the output will read 5V
for open input.
Open Input
Figure 9 shows an example of an open input fault. To sense
this type of fault use the 1/50 feature by setting MUX[1:0] to
10b to test the +IN pin or to 11b to test the −IN pin, POL to
0b, PIN to 1b to test the −IN pin, and G[2:0] to 010b for a gain
300454b7
FIGURE 9. Open Input
POL to 0b, and G[2:0] to 010b for a gain of 50 (0082x or
00C2x). This will give an overall gain of 1 and the output will
read either V+ or V− depending on whether the input pin is
shorted to V+ or V−.
Input Shorted to V+ or V−
Figure 10 shows an example of an input pin shorted to V+ or
V−. To sense this fault, use the 1/50 feature by setting MUX
[1:0] to 10b to test the +IN pin or to 11b to test the −IN pin,
300454b8
FIGURE 10. Input Shorted to V+ or V−
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300454b9
FIGURE 11. Shorted Inputs
to 010b for a gain of 50. This will give an overall gain of 1. Set
CUR[2:0] = 101b to inject a 100µA current and read the output
voltage (5082x). Next set MUX[1:0] to 11b and PIN to 1b to
test the −IN pin as shown in Figure 13 and read the output
(58C2x). If the voltages of these two measurements are different a degraded input fault exists.
Degraded Input Line
Figure 12 shows an example of a degraded connection between the bridge and the +IN pin of the LMP8358. This fault
is shown by the 1 kΩ resistor placed between the bridge and
the LMP8358. To detect this fault use the 1/50 feature by setting MUX[1:0] to 10b to test the +IN pin, POL to 0b, and G[2:0]
300454c0
FIGURE 12. Degraded Input Line, Step 1
300454c1
FIGURE 13. Degraded Input Line, Step 2
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LMP8358
cause of the voltage drop across the internal ESD resistor,
which has a value between 60Ω to 90Ω. If the gain is set to
100× with an injected current of 100µA the output will be about
0.7V.
Shorted Inputs
Figure 11 shows the inputs of the LMP8358 shorted. To detect
this fault set CUR[2:0] = 101b to inject a 100µA current and
set the gain to 10× (5000x). The LMP8358 is set up with normal differential inputs. The output will read about 0.07V be-
LMP8358
Matrix. If the circuit shown in Figure 7 is used the values
shown in column 2 of Table 16. Fault Detection Matrix would
show that the system is working correctly, the values in the
columns under the Possible Faults heading would show that
there is a potential problem and that operator attention is
needed.
Fault Detection Example
Using the fault detection features of the LMP8358 an end
product, such as a scale, can periodically test that no damage
has occurred to the system. A routine can be written that
could, for example, run on start up, that will step through the
fault detection features shown above and compare the output
voltage to a table like that shown in Table 16. Fault Detection
Table 16. Fault Detection Matrix
No Faults
Possible Faults
LMP8358
Register
VOUT
VOUT
Possible Cause
VOUT
Possible Cause
00 82x
2.5V
VOUT < CMVR or
VOUT > CMVR
Input is out of
CMVR
V+
+IN shorted to V+ 0V
+IN shorted to
GND
00 C2x
2.5V
VOUT < CMVR or
VOUT > CMVR
Input is out of
CMVR
V+
−IN shorted to V+ 0V
−IN shorted to
GND
50 00x
0.61V
V+
+IN Open
0.07V
Inputs shorted
50 03x
4.97V
V+
−IN
0.7V
Inputs shorted
50 82x
2.55V
2.65V*
Degraded +IN
line
58 C2x
2.55V
2.55V*
Degraded +IN
line
50 82x
2.55V
2.55V*
Degraded −IN
line
58 C2x
2.55V
2.65V*
Degraded −IN
line
* The values shown for a degraded input line will vary depending on the resistance in the line. This table uses the value
in Figure 12 and Figure 13, 1kΩ.
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VOUT
Possible Cause
DIFFERENTIAL BRIDGE SENSOR
Non-amplified differential bridge sensors, which are used in
a variety of applications, typically have a very small differential
output signal. This small signal needs to be accurately amplified before it can be used by an ADC.
The high DC performance of the LMP8358 makes it a good
choice for use with a differential bridge sensor. This performance includes low input offset voltage, low input offset voltage drift, and high CMRR. The on chip EMI rejection filters
available on the LMP8358 help remove the EMI interference
introduced to the signal as shown in Figure 14 and improves
the overall system performance.
The circuit in Figure 14 shows a signal path solution for a typical bridge sensor using the LMP8358. The typical output
voltage of a resistive load cell is 2mV/V. If the bridge sensor
is using a 5V supply the maximum output voltage will be 2mV/
V × 5V = 10mV. The bridge voltage in this example is the
same as the LMP8358 and ADC161S626 supply voltage of
+5V. This 10mV signal must be accurately amplified by the
LMP8358 to best match the dynamic range of the ADC. This
is done by setting the gain of the LMP8358 to 200 which will
give an output from the LMP8358 of 2V. To use the complete
range of the ADC161S626 the VREF of the ADC should be set
to half of the input or 1V. This is done by the resistor divider
on the VREF pin of the ADC161S626. The negative input of
the ADC and the REFF and REFS pins of the LMP8358 can
be set to +2.5V to set the signal at the center of the supply. A
resistor divider supplies +2.5V to the positive input of an
LMP7701 set up in a buffer configuration. The LMP7701 acts
as a low impedance source for the REFF pin. The VIOand
VHSER/VLPAR pins should all be set to the same voltage as
the microcontroller, +3.3V in this example. The VLSER/VHPAR pin should be connected to ground. The resistor and
capacitor between the LMP8358 and the ADC161S626 serve
a dual purpose. The capacitor is a charge reservoir for the
sampling capacitor of the ADC. The resistor provides isolation
for the LMP8358 from the capacitive load. The values listed
in the ADC161S626 datasheet are 180Ω for the resistor and
the 470pF for the capacitor. These two components also form
a low pass filter of about 1.9MHz. If a filter is needed to attenuate disturbance from the internal auto−zeroing at 12kHz
and the ping−pong frequency at 50kHz of the LMP8358 these
values could be changed to 7870Ω and 0.01µF which will
make a filter with a corner of about 2kHz.
LAYOUT
The LMP8358 is a precision device that contains both analog
and digital sections as shown in the Block Diagram. The PCB
should be carefully designed to minimize the interaction between the analog and digital sections and to maximize the
performance of the part. This should include the following:
0.1µF ceramic capacitors should be placed as close as possible to each supply pin. If a digital supply pin is tied to an
analog pin only one 0.1µF capacitor is needed for both pins.
A larger 1µF or 10µF capacitor should be located near the part
for each supply.
Digital and analog traces should be kept away from each other. Analog and digital traces should not run next to each other,
if they do the digital signal can couple onto the analog line.
The LMP8358 pinout is set up to simplify layout by not having
analog, power, and digital pins mixed together. Pins 1 — 6
are the analog signals, pins 7 — 10 are the power pins, and
pins 11 — 14 are the digital signals.
Be aware of the signal and power return paths. The return
paths of the analog, digital, and power sections should not
cross each other and the return path should be underneath
the respective signal or power path. The best PCB layout is if
the bottom plane of the PCB is a solid plane.
The REFF and REFS pins are connected to the bottom side
of the gain resistors of the LMP8358 as shown in the Block
Diagram. Any impedance on these pins will change the specified gain. If the REFF and REFS pins are to be connected to
ground they should be tied directly to the ground plane and
not through thin traces that can add impedance. If the REFF
and REFS pins are to be connected to a voltage, the voltage
source must be low impedance. This can be done by adding
an op amp, such as the LMP7701, set up in a buffer configu-
29
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LMP8358
ration with the LMP7701 output connected to REFF, the
negative input of the op amp connected to REFS, and the
desired reference voltage connected to the positive input of
the op amp as shown in Figure 14.
START UP AND POWER ON RESET
During power on, 50µs after V+ − V− > 1V the LMP8358 resets
the internal register to 0000x. If the digital supplies and inputs
are undefined after the Power On Reset transients could occur which can cause erroneous data to be written over the
default values in the register. The following should be done to
prevent this from happening:
• Bring all supplies up at the same time. All power supplies,
analog and digital, should be brought up together within 40µs
so that the supplies are not undefined after the Power On
Reset at 50µs. This is easiest done by tying the VHSER/VLPAR and VLSER/VHPAR pins to the analog supplies. —
Parallel Mode
• Immediately after power on, write to the register the value
needed for the application. (This is always recommended.) —
Serial Mode
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30
FIGURE 14. Differential Bridge Sensor
300454e4
LMP8358
LMP8358
Physical Dimensions inches (millimeters) unless otherwise noted
14-Pin SOIC
NS Package Number M14A
14–Pin TSSOP
NS Package Number M14MT
31
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LMP8358 Zero-Drift, Programmable Instrumentation Amplifier with Diagnostics
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