ICs for TV AN2526NFH Automotive LCD TV signal processor IC ■ Overview Unit: mm 12.00±0.20 10.00±0.20 48 • Supply voltage: 5 V/7.5 V • Built-in LCD's 5 V-source driving power supply • Low consumption power (typ. 260 mW) • Supporting NTSC and PAL • Supporting composite, component and color differential signal input • Video signal， analog RGB (2 systems) One is for OSD (analog/digital). • Each mode setting is possible with 3-wire or I2C Bus control. • Electronic volume (D/A converter) built in • Contrast/Brightness/γ correction circuit built in • Horizontal and vertical display position adjustment are possible by serial control. • Package: QFP-64HP10L (10 × 10 × 1.95 mm) • Difference from the AN2526FH Compared to the AN2526FH, the sync. system gain is increased in no signal input. This may cause the picture on the screen to be swaying horizontally. So we cannot recommend this IC to be used in the set with no-signal input mode. 32 (1.25) 10.00±0.20 12.00±0.20 64 1 16 0.50 +0.10 0.18−0.05 +0.10 (1.25) 17 0.15−0.05 1.95±0.20 ■ Features 33 49 0.10±0.10 The AN2526NFH is a video signal processing IC with an LCD's 5 V-source driving power supply for TFT color LCD (normally white type), and it supports NTSC and PAL systems. The main circuitry of this IC includes videosignal processing circuit, color signal processing circuit, interface circuit, synchronizing circuit and many color quality adjusting circuits. This IC converts the composite video signal or separated Y/C signal or RGB signals into RGB signals available for TFT color LCD. Seating plane (1.00) 0° to 10° 0.50±0.20 QFP064-P-1010 Note) The package of this product will be changed to lead-free type (QFP064-P-1010A). See the new package dimensions section later of this datasheet. ■ Applications • 4 inches to 7 inches middle size TFT LCD equipment of normally white, of such as in-car TV, an LCD monitor for car navigation system. Publication date: November 2001 SDB00080AEB 1 Composite signal 2 SDB00080AEB B−Y in R−Y in 2 1 1 µF GCA 1 µF 3 15 µF VREF GCA ctl. Delay Delay 1 µF Matrix GCA Int./Ext. SW LPF Demod. CLMP Color-ctl. Int./Ext. SW CLP BGP Contrast Contrast ctl. Det. Gamma ctl. White peak ctl. POL Logic Logic Logic COMON voltage YS 15 14 13 12 11 10 9 8 7 6 5 4 VD HD 17 18 19 20 21 22 23 24 25 26 27 28 29 2.2 µF 15 µF 82 kΩ 330 pF 200 kΩ B-out G-out VCC2 47 µH (7.5 V) 50 kB GND1 R-out VCOM TMODE Test CLK 0.01 µF VCC1 2.2 µF 2.2 µF Field 30 C-sync. 31 32 82 kΩ 330 pF 100 kΩ VCC1 • C coupling input in an analog OSD mode. • Connect to GND in case of no use in a digital OSD mode. Bright-ctl. WB-ctl. Bright Gamma Amp. AVE det. VCOM adj. Logic PWM 2.2 µF 16 15 µF 47 µH GCA YAP ctl. Tint-ctl. to φ4 Gene. 41 VCC1 (5.0 V) 64 63 62 61 60 Trap φ1 Tint PAL 1/2 CW/SW Line I-det. 1/n PH-CMP 37 B−Y out R−Y out 4.7 µF GND 3 59 58 CLMP (BGP) VXO APC det. Kill det. f-det. Sync.DRP Logic 36 NTSC 39 pF PAL 27 pF 47 µH 57 56 55 54 53 HH-KIL VCO DAC 35 1 µF 5.1 kΩ NTSC 3.58 MHz PAL 4.43 MHz 0.1 µF 0.1 µF ACC det. 43 1 MΩ 0.02 µF Logic ACC amp. 47 52 48 HPF 46 51 S-data V-C/D 44 0.02 µF 45 DAC 42 LATCH NRGB 0.1 µF SCLCK 40 BUSCH GND2 39 50 DAC mon. 38 Reg. Clamp Logic VSS Sync. sepa. POL 34 0.1 µF BUSCH DEC 15 µF PONR Shift res. 3.3 kΩ 1 000 pF 33 49 180 kΩ 10 kΩ 0.022 µF 100 kΩ PWM LD 1 000 pF 470 Ω 1.0 µF 0.47 µF AN2526NFH ■ Application Circuit Examples 1. Composite signal input BLAK B-in 2 G-in 2 R-in 2 B-in 1 G-in 1 R-in 1 Dec. B-out Dec. G-out Dec. R-out Lumi. + Sync. signal SDB00080AEB B−Y in R−Y in 2 1 1 µF 1 µF 3 15 µF GCA 1 µF Matrix GCA Int./Ext. SW LPF Demod. CLMP Color-ctl. Int./Ext. SW CLP BGP PH-CMP Contrast Contrast ctl. Det. Gamma ctl. White peak ctl. POL Logic Logic Logic COMON voltage VD HD 17 18 19 20 21 22 23 24 25 26 27 28 29 2.2 µF 15 µF 82 kΩ 330 pF 200 kΩ 82 kΩ 330 pF B-out G-out VCC2 47 µH (7.5 V) 50 kB GND1 R-out VCOM TMODE Test CLK 0.01 µF VCC1 2.2 µF 2.2 µF Field 30 C-sync. 31 32 100 kΩ VCC1 2. Component signal input YS 15 14 13 12 11 10 9 8 7 6 • C coupling input in an analog OSD mode. • Connect to GND in case of no use in a digital OSD mode. Bright-ctl. WB-ctl. Bright Gamma Amp. AVE det. VCOM adj. Logic PWM 2.2 µF 16 15 µF 47 µH VREF GCA ctl. Delay Delay CW/SW PAL 1/2 1/n 41 VCC1 (5.0 V) 64 63 62 61 60 YAP ctl. Tint-ctl. to φ4 Gene. GCA φ1 Tint Line I-det. f-det. Sync.DRP 37 B−Y out R−Y out 4.7 µF 59 Trap CLMP (BGP) VXO APC det. Kill det. HH-KIL Logic 36 GND 3 58 57 56 55 54 53 Logic ACC det. VCO DAC 35 1 µF 5.1 kΩ NTSC 3.58 MHz PAL 4.43 MHz 0.1 µF 1 MΩ 0.02 µF 52 47 ACC amp. 43 0.1 µF 48 HPF 46 51 S-data V-C/D 44 0.02 µF 45 DAC 42 LATCH NRGB Chroma 0.1 µF signal SCLCK 40 BUSCH GND2 39 50 DAC mon. 38 Reg. Clamp Logic VSS Sync. sepa. POL 34 0.1 µF BUSCH DEC 15 µF PONR Shift res. 3.3 kΩ 1 000 pF 33 49 180 kΩ 10 kΩ 0.022 µF 100 kΩ PWM LD 1 000 pF 470 Ω 1.0 µF 0.47 µF AN2526NFH ■ Application Circuit Examples (continued) BLAK B-in 2 G-in 2 R-in 2 B-in 1 G-in 1 R-in 1 Dec. B-out Dec. G-out Dec. R-out 5 4 3 Composite signal 4 SDB00080AEB GND 3 1 15 µF GCA Matrix CLMP Color-ctl. 8 2.2 MΩ 4.7 µF 10 4.7 µF Contrast Contrast ctl. 11 2.2 MΩ 9 4.7 µF Int./Ext. SW CLP BGP PH-CMP Det. Gamma ctl. White peak ctl. POL Logic Logic Logic PWM COMON voltage YS 15 14 13 12 7 6 5 4 3 2 VD HD 17 18 19 20 21 22 23 24 25 26 27 28 29 2.2 µF 15 µF 82 kΩ 330 pF 200 kΩ 82 kΩ 330 pF B-out G-out VCC2 47 µH (7.5 V) 50 kB GND1 R-out VCOM TMODE Test CLK 0.01 µF VCC1 2.2 µF 2.2 µF Field 30 C-sync. 31 32 100 kΩ VCC1 • C coupling input in an analog OSD mode. • Connect to GND in case of no use in a digital OSD mode. Bright-ctl. WB-ctl. Bright Gamma Amp. AVE det. VCOM adj. Logic 16 15 µF 47 µH VREF GCA ctl. GCA Int./Ext. SW LPF Demod. 1/n 41 VCC1 (5.0 V) 64 63 Delay Delay CW/SW PAL 1/2 f-det. Sync.DRP 37 62 61 60 Tint-ctl. to φ4 Gene. GCA YAP ctl. Trap CLMP (BGP) φ1 Tint Line I-det. HH-KIL Logic 36 59 58 57 VXO APC det. Kill det. ACC det. VCO DAC 35 56 55 54 48 Logic 47 ACC amp. 46 HPF 43 53 S-data V-C/D 44 52 45 DAC 42 LATCH NRGB 51 SCLCK 40 BUSCH GND2 39 50 DAC mon. 38 Reg. Clamp Logic VSS 34 Sync. sepa. 2.2 µF 33 LD BUSCH DEC 15 µF 1 000 pF 100 kΩ PWM Shift res. 3.3 kΩ POL 49 180 kΩ 10 kΩ 0.022 µF PONR 1 000 pF 470 Ω 1.0 µF 0.47 µF AN2526NFH ■ Application Circuit Examples (continued) 3. Analog RGB signal input BLAK B-in 2 G-in 2 R-in 2 2.2 MΩ B-in 1 G-in 1 R-in 1 AN2526NFH ■ Pin Descriptions Pin No. Description Pin No. Description 1 VCC1 (5.0 V) 33 PWM output pin 2 Reference voltage pin 34 Power-on reset detection pin 3 R-ch. clamp detection pin 35 Vertical synchronous signal input pin 4 G-ch. clamp detection pin 36 1H reverse signal input pin 5 B-ch. clamp detection pin 37 Clock-system GND (VSS) 6 R-ch. decoder output pin 38 Clamp pulse input pin 7 G-ch. decoder output pin 39 DAC monitor pin 8 B-ch. decoder output pin 40 Clock-system power supply (3.0 V) 9 R-ch. analog signal input pin 41 GND 2 10 G-ch. analog signal input pin 42 Analog imposing control signal input pin 11 B-ch. analog signal input pin 43 AFC loop filter connecting pin 12 R-ch. analog/character signal input pin 44 VCO frequency adjustment pin 13 G-ch. analog/character signal input pin 45 Synchronous signal input pin 14 B-ch. analog/character signal input pin 46 Serial/I2C Bus switching pin 15 Black level indication control signal input pin 47 Serial data shift clock input pin 16 Character picking up pulse input pin 48 Serial data input pin 17 B-ch. output pin 49 Serial data write pulse input pin 18 B-ch. output DC feedback detection pin 50 ACC detection pin 19 G-ch. output pin 51 ACC input pin 20 VCC2 (7.5 V) 52 Horizontal clock detection pin 21 Drive output reference potential input pin 53 Chroma killer detection pin 22 GND 1 54 APC detection pin 23 G-ch. output DC feedback detection pin 55 VXO input pin 24 R-ch. output pin 56 VXO output pin 25 R-ch. output DC feedback detection pin 57 Y-system clamp detection pin 26 Common reverse signal output pin 58 Chroma trap filter connection pin 27 Testing pulse input pin 59 GND 3 28 Testing clock input pin 60 Luminance signal input pin 29 Field identification signal output pin 61 R-Y output pin 30 Composite synchronous signal output pin 62 B-Y output pin 31 Vertical synchronous signal output pin 63 R-Y input pin 32 Horizontal synchronous signal output pin 64 B-Y input pin SDB00080AEB 5 AN2526NFH ■ Absolute Maximum Ratings Parameter Supply voltage Symbol Rating Unit VCC1 5.5 V VCC2 8.5 ICC mA PD 423 mW Topr −30 to +85 °C Tstg −55 to +150 °C Supply current Power dissipation *2 Operating ambient temperature Storage temperature *1 *1 Note) *1: Except for the operating ambient temperature and storage temperature, all ratings are for Ta = 25°C. *2: The power dissipation shown is the value in free air for Topr = 85°C. ■ Recommended Operating Range Parameter Supply voltage Symbol Range Unit VCC1 4.7 to 5.3 V VCC2 7.0 to 8.0 ■ Electrical Characteristics at Ta = 25°C Parameter Symbol Conditions Min Typ Max Unit VCC1-system current consumption ITOTAL1 29 43 mA VCC2-system current consumption ITOTAL2 6.0 14.0 mA Pin 2 voltage V2 1.8 2.2 V Pin 40 voltage V40 2.7 3.3 V GRY SG3 (Yy = −17 dB, Ys = 0 V[p-p], NTSC), ch.1 = "C0" 9.5 14.5 dB GRYGY SG3 (Yy = −17 dB, Ys = 0 V[p-p], NTSC), ch.1 = "C0" −8.0 −4.0 dB GBY SG3 (Yy = −17 dB, Ys = 0 V[p-p], NTSC), ch.1 = "C0" 9.5 14.5 dB B-Y/G-Y relative gain GBYGY SG3 (Yy = −17 dB, Ys = 0 V[p-p], NTSC), ch.1 = "C0" −20.5 −12.5 dB High-level APC pull-in APH SG5 (4.43 MHz + 520 Hz, PAL) 500 540 Hz Low-level APC pull-in APL SG5 (4.43 MHz − 520 Hz, PAL) −540 −500 Hz DC Chroma system R-Y standard gain R-Y/G-Y relative gain B-Y standard gain 6 ACC output characteristic 1 GACC1 SG5 (0 dB, 6 dB, NTSC), ch.1 = "80" −1.0 1.0 dB ACC output characteristic 2 GACC2 SG5 (0 dB, 6 dB, NTSC), ch.1 = "80" −1.0 1.0 dB Chroma killer characteristic 1 VKILL1 SG5 (−30 dB, NTSC) ch.1 = "80", ch.2 = "80", ch.5 = "FF" 400 mV[p-p] Chroma killer characteristic 2 VKILL2 SG5 (−50 dB, NTSC) ch.1 = "80", ch.2 = "80", ch.5 = "FF" 600 mV[p-p] SDB00080AEB AN2526NFH ■ Electrical Characteristics at Ta = 25°C (continued) Parameter Symbol Conditions Min Typ Max Unit Y-system Sharpness control characteristic GSH SG1 (2 MHz, NTSC) ch.1 = "80", ch.9 = "80"/"FF" 1.0 dB Sharpness frequency characteristic 1 fSH1 SG1 (100 kHz/2 MHz, NTSC) ch.1 = "80" 3.5 dB R-ch. contrast adjustment range 1 CTRR1 SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12/13/14 = "FF" ch.8/10/11 adjustment ch.15 = "C0"/"FF" 1.5 dB G-ch. contrast adjustment range 1 CTRG1 SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12/13/14 = "FF" ch.8/10/11 adjustment ch.15 = "C0"/"FF" 1.5 dB B-ch. contrast adjustment range 1 CTRB1 SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12/13/14 = "FF" ch.8/10/11 adjustment ch.15 = "C0"/"FF" 1.5 dB R-ch. contrast adjustment range 2 CTRR2 SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12/13/14 = "FF" ch.8/10/11 adjustment ch.15 = "C0"/"80" −5.2 dB G-ch. contrast adjustment range 2 CTRG2 SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12/13/14 = "FF" ch.8/10/11 adjustment ch.15 = "C0"/"80" −5.2 dB B-ch. contrast adjustment range 2 CTRB2 SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12/13/14 = "FF" ch.8/10/11 adjustment ch.15 = "C0"/"80" −5.2 dB VPEDRmin SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12/13/14 = "FF" ch.8/10/11 adjustment, ch.8 = "FF" ch.15 = "C0" 2.0 V[p-p] G-ch. pedestal amplitude minimum VPEDGmin SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12/13/14 = "FF" ch.8/10/11 adjustment, ch.8 = "FF" ch.15 = "C0" 2.0 V[p-p] VPEDBmin SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12/13/14 = "FF" ch.8/10/11 adjustment, ch.8 = "FF" ch.15 = "C0" 2.0 V[p-p] R-ch. pedestal amplitude minimum B-ch. pedestal amplitude minimum SDB00080AEB 7 AN2526NFH ■ Electrical Characteristics at Ta = 25°C (continued) Parameter Symbol Conditions Min Typ Max Unit R-ch. pedestal amplitude maximum VPEDRmax SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12/13/14 = "FF" ch.8/10/11 adjustment, ch.8 = "00" ch.15 = "C0" 3.0 V[p-p] G-ch. pedestal amplitude maximum VPEDGmax SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12/13/14 = "FF" ch.8/10/11 adjustment, ch.8 = "00" ch.15 = "C0" 3.0 V[p-p] B-ch. pedestal amplitude maximum VPEDBmax SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12/13/14 = "FF" ch.8/10/11 adjustment, ch.8 = "00" ch.15 = "C0" 3.0 V[p-p] SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11 adjustment, ch.15 = "C0" 2.2 2.5 V[p-p] Y-system (continued) G-ch. output DC voltage 8 VGDC R-ch. gamma characteristic 1 GGAMR1 SG3 (NTSC), ch.1 = "E0", ch.2 = "40" −8.5 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment −3.5 dB G-ch. gamma characteristic 1 GGAMG1 SG3 (NTSC), ch.1 = "E0", ch.2 = "40" −8.5 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment −3.5 dB B-ch. gamma characteristic 1 GGAMB1 SG3 (NTSC), ch.1 = "E0", ch.2 = "40" −8.5 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment −3.5 dB R-ch. gamma characteristic 2 GGAMR2 SG3 (NTSC), ch.1 = "E0", ch.4 = "40" −8.2 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment ch.13 = "80"/"FF" dB G-ch. gamma characteristic 2 GGAMG2 SG3 (NTSC), ch.1 = "E0", ch.4 = "40" −8.2 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment ch.13 = "80"/"FF" dB B-ch. gamma characteristic 2 GGAMB2 SG3 (NTSC), ch.1 = "E0", ch.4 = "40" −8.2 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment ch.13 = "80"/"FF" dB R-ch. gamma characteristic 3 GGAMR3 SG3 (NTSC), ch.1 = "E0", ch.2 = "40" −3.5 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment ch.13 = "80"/"60" 0.5 dB SDB00080AEB AN2526NFH ■ Electrical Characteristics at Ta = 25°C (continued) Parameter Symbol Conditions Min Typ Max Unit Y-system (continued) G-ch. gamma characteristic 3 GGAMG3 SG3 (NTSC), ch.1 = "E0", ch.2 = "40" −3.5 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment ch.13 = "80"/"60" 0.5 dB B-ch. gamma characteristic 3 GGAMB3 SG3 (NTSC), ch.1 = "E0", ch.2 = "40" −3.5 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment ch.13 = "80"/"60" 0.5 dB R-ch. white limiter low-level VWRRL SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "00", ch.14 = "40" ch.8/10/11/15 adjustment ch.15 = "FF" 3.0 V[p-p] G-ch. white limiter low-level VWRGL SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "00", ch.14 = "40" ch.8/10/11/15 adjustment ch.15 = "FF" 3.0 V[p-p] B-ch. white limiter low-level VWRBL SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "00", ch.14 = "40" ch.8/10/11/15 adjustment ch.15 = "FF" 3.0 V[p-p] R-ch. white limiter high-level VWRRH SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment ch.15 = "FF" 3.2 V[p-p] G-ch. white limiter high-level VWRGH SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment ch.15 = "FF" 3.2 V[p-p] B-ch. white limiter high-level VWRBH SG3 (NTSC), ch.1 = "E0", ch.2 = "40" 3.2 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment ch.15 = "FF" V[p-p] R-ch. black limiter low-level VBRRL SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.7 = "80", ch.12 = "FF" ch.14 = "40", ch.8/10/11/15 adjustment ch.8 = "00" 3.0 V G-ch. black limiter low-level VBRGL SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.7 = "80", ch.12 = "FF" ch.14 = "40", ch.8/10/11/15 adjustment ch.8 = "00" 3.0 V SDB00080AEB 9 AN2526NFH ■ Electrical Characteristics at Ta = 25°C (continued) Parameter Symbol Conditions Min Typ Max Unit B-ch. black limiter low-level VBRBL SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.7 = "80", ch.12 = "FF" ch.14 = "40", ch.8/10/11/15 adjustment ch.8 = "00" 3.0 V R-ch. black limiter high-level VBRRH SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF" ch.8/10/11/15 adjustment, ch.7 = "FF" ch.8 = "00", ch.14 = "40" 1.2 V G-ch. black limiter high-level VBRGH SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF" ch.8/10/11/15 adjustment, ch.7 = "FF" ch.8 = "00", ch.14 = "40" 1.2 V B-ch. black limiter high-level VBRBH SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF" ch.8/10/11/15 adjustment, ch.7 = "FF" ch.8 = "00", ch.14 = "40" 1.2 V R-ch. YS threshold 1 VtYSR1 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 16 = 1 V 0.8 V[p-p] G-ch. YS threshold 1 VtYSG1 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 16 = 1 V 0.8 V[p-p] B-ch. YS threshold 1 VtYSB1 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 16 = 1 V 0.8 V[p-p] R-ch. YS threshold 2 VtYSR2 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 16 = 2.2 V 0.5 V[p-p] G-ch. YS threshold 2 VtYSG2 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 16 = 2.2 V 0.5 V[p-p] B-ch. YS threshold 2 VtYSB2 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 16 = 2.2 V 0.5 V[p-p] R-ch. black level CHRRB SG2 (NTSC), ch.1 = "E0", ch.2 = "40" − 0.6 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 16 = SG7 0.6 V G-ch. black level CHRGB SG2 (NTSC), ch.1 = "E0", ch.2 = "40" − 0.6 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 16 = SG7 0.6 V B-ch. black level CHRBB SG2 (NTSC), ch.1 = "E0", ch.2 = "40" − 0.6 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 16 = SG7 0.6 V Y-system (continued) 10 SDB00080AEB AN2526NFH ■ Electrical Characteristics at Ta = 25°C (continued) Parameter Symbol Conditions Min Typ Max Unit R-ch. black level width WCHRRB SG2 (NTSC), ch.1 = "E0", ch.2 = "40" 2.25 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 16 = SG7 3.75 µs G-ch. black level width WCHRGB SG2 (NTSC), ch.1 = "E0", ch.2 = "40" 2.25 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 16 = SG7 3.75 µs B-ch. black level width WCHRBB SG2 (NTSC), ch.1 = "E0", ch.2 = "40" 2.25 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 16 = SG7 3.75 µs Y-system (continued) R-ch. CHR threshold 1 VtCHR1 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 12 = 1 V 1.5 V[p-p] G-ch. CHR threshold 1 VtCHG1 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 13 = 1 V 1.5 V[p-p] B-ch. CHR threshold 1 VtCHB1 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 14 = 1 V 1.5 V[p-p] R-ch. CHR threshold 2 VtCHR2 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 12 = 2.2 V 3.0 V[p-p] G-ch. CHR threshold 2 VtCHG2 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 13 = 2.2 V 3.0 V[p-p] B-ch. CHR threshold 2 VtCHB2 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 14 = 2.2 V 3.0 V[p-p] R-ch. white level CHRRW SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 12 = SG7 2.0 V[p-p] G-ch. white level CHRGW SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 13 = SG7 2.0 V[p-p] B-ch. white level CHRBW SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 14 = SG7 2.0 V[p-p] R-ch. white level width WCHRRW SG2 (NTSC), ch.1 = "E0", ch.2 = "40" 2.25 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 12 = SG7 3.75 µs G-ch. white level width WCHRGW SG2 (NTSC), ch.1 = "E0", ch.2 = "40" 2.25 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 13 = SG7 3.75 µs SDB00080AEB 11 AN2526NFH ■ Electrical Characteristics at Ta = 25°C (continued) Parameter Symbol Conditions Min Typ Max Unit WCHRBW SG2 (NTSC), ch.1 = "E0", ch.2 = "40" 2.25 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 14 = SG7 3.75 µs Y-system (continued) B-ch. white level width R-ch. RGB2 relative amplitude VRGB2R SG2 (NTSC), ch.1 = "A0" − 0.45 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, ch.3 = "40" ch.6 = "40", Pin 42 = 2.2 V 0.45 V[p-p] B-ch. RGB2 relative amplitude VRGB2B SG2 (NTSC), ch.1 = "A0" − 0.45 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, ch.3 = "40" ch.6 = "40", Pin 42 = 2.2 V 0.45 V[p-p] Synchronous system Horizontal sync. pulse low-level VHDL 0.4 V Horizontal sync. pulse amplitude VHD 4.0 V[p-p] Horizontal sync. pulse width tHD 4.86 6.86 µs Vertical sync. pulse low-level VVDL 0.4 V Vertical sync. pulse amplitude VVD 4.0 V[p-p] Horizontal sync. separation pulse high-level VHSSH SG2 (NTSC) 4.0 V Horizontal sync. separation pulse amplitude VHSS SG2 (NTSC) 4.0 V[p-p] Horizontal sync. separation pulse width tHSS SG2 (NTSC) 3.8 5.8 µs Horizontal sync. pulse free-run frequency fHD 15.434 16.034 kHz ■ Terminal Equivalent Circuits Pin No. Equivalent circuit Description Voltage · Waveform 1 VCC1: 5.0 V-system power supply pin Supply current 40 mA typ. VREF: Reference voltage output pin 2.0 V typ. 2 Pin 1 VCC1 60 Ω 2 1 kΩ 26 kΩ 200 Ω 12 30 kΩ Pin 59 GND SDB00080AEB AN2526NFH ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit 3 1 kΩ Description Pin 1 1 kΩ VCC1 3 Voltage · Waveform R-ch. det.: R-ch. clamping capacitor coupling pin G-ch. det.: G-ch. clamping capacitor coupling pin B-ch. det.: B-ch. clamping capacitor coupling pin 500 Ω HSS Pin 22 GND 4 1 kΩ Pin 1 1 kΩ VCC1 4 500 Ω HSS Pin 22 GND 5 1 kΩ Pin 1 1 kΩ VCC1 5 500 Ω HSS Pin 22 GND 6 Pin 1 VCC1 6 Dec.R-out: Output pin of R signal demodulated from video signal 150 Ω 150 Ω Pin 22 GND SDB00080AEB 13 AN2526NFH ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit 7 7 Description Pin 1 VCC1 Dec.G-out: Output pin of G signal demodulated from video signal Pin 1 VCC1 Dec.B-out: Output pin of B signal demodulated from video signal Voltage · Waveform 150 Ω 150 Ω Pin 22 GND 8 8 150 Ω 150 Ω Pin 22 GND 9 R-in 1: Analog R signal input Pin 1 VCC1 Analog R signal 0.7 V[p-p] typ. 5 kΩ 9 BGP Pin 2 VREF 10 Pin 22 GND G-in 1: Analog G signal input Pin 1 VCC1 Analog G signal 0.7 V[p-p] typ. 10 BGP 5 kΩ Pin 2 VREF 14 Pin 22 GND SDB00080AEB AN2526NFH ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit 11 Description B-in 1: Analog B signal input Pin 1 VCC1 Voltage · Waveform Analog B signal 0.7 V[p-p] typ. 5 kΩ 11 BGP Pin 2 VREF 12 Pin 22 GND R-in 2: Character insertion signal input for R-ch., supporting analog and digital OSD. Pin 1 VCC1 Analog OSD 0.7 V[p-p] typ. Digital OSD 5 kΩ 12 BGP GND Pin 2 VREF 13 VCC1 Pin 22 GND G-in 2: Character insertion signal input for G-ch., supporting analog and digital OSD. Pin 1 VCC1 Analog OSD 0.7 V[p-p] typ. Digital OSD 5 kΩ 13 BGP GND Pin 2 VREF 14 VCC1 Pin 22 GND B-in 2: Character insertion signal input for B-ch., supporting analog and digital OSD. Pin 1 VCC1 Analog OSD 0.7 V[p-p] typ. Digital OSD 14 BGP 5 kΩ VCC1 GND Pin 2 VREF Pin 22 GND SDB00080AEB 15 AN2526NFH ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit 15 15 Description Voltage · Waveform BLAK: Black level indication control signal input pin 5 kΩ 49.3 kΩ VCC1 GND VSS 16 16 YS: Character picking up signal input 5 kΩ 49.3 kΩ VCC1 GND VSS 17 100 kΩ Pin 18 200 Ω Pin 20 VCC2 B-out: B signal output pin 26 kΩ 17 2 kΩ Pin 22 GND 18 100 kΩ 18 Pin 20 VCC2 Pin 17 2 kΩ 8 kΩ 19 100 kΩ Pin 18 200 Ω B-ch.AVE det.: B-ch. output DC feedback detection pin Pin 22 GND Pin 20 VCC2 G-out: G signal output pin 26 kΩ 19 2 kΩ Pin 22 GND 20 16 VCC2: 7.5 V system power supply Supply current 12 mA typ. SDB00080AEB AN2526NFH ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit 21 Pin 20 VCC2 200 kΩ Description Voltage · Waveform AVE : R,G,B output DC reference voltage pin GND 2: Drive circuit system GND G-ch.AVE det.: G-ch. output DC feedback detection pin 21 2 kΩ 200 kΩ 8 kΩ Pin 22 GND 22 23 100 kΩ 23 Pin 20 VCC2 Pin 17 2 kΩ 8 kΩ 24 100 kΩ Pin 18 200 Ω Pin 22 GND Pin 20 VCC2 R-out: R signal output pin 26 kΩ 24 2 kΩ Pin 22 GND 25 100 kΩ 25 Pin 20 VCC2 Pin 17 2 kΩ 8 kΩ R-ch.AVE det.: R-ch. output DC feedback detection pin Pin 22 GND SDB00080AEB 17 AN2526NFH ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description 26 Pin 19 VCC2 200 Ω Common out: Voltage output pin for common. Output impedance; Approx. 150 Ω 15 kΩ 26 Voltage · Waveform ch.3 ch.3 100 kΩ Pin 22 GND 27 Pin 40 VDD 27 10 kΩ Test mode: Logic test mode start signal input pin; "Open" or "GND" normally High or Low Test CLK: Logic test pulse input pin; "Open" or "GND" normally High or Low Field: Field identifying signal output pin Output waveform 39.8 kΩ Pin 37 VSS 28 Pin 40 VDD 28 5 kΩ 44.8 kΩ Pin 37 VSS 29 Pin 1 VCC1 VCC1 29 Pin 40 VDD 0V Field Pin 37 VSS 30 Pin 1 VCC1 HSS: Composite synchronous signal output pin 30 Pin 40 VDD VCC1 0V HSS Pin 37 VSS 18 Output waveform SDB00080AEB AN2526NFH ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit 31 Pin 1 VCC1 Description Voltage · Waveform VD: Vertical synchronous signal output pin Output waveform VCC1 31 Pin 40 VDD 0V VD Pin 37 VSS 32 Pin 1 VCC1 HD : Horizontal synchronous signal output pin Output waveform VCC1 32 Pin 40 VDD 0V HD Pin 37 VSS 33 Pin 1 VCC1 PWM: PWM signal output pin Output waveform VCC1 33 Pin 40 VDD 0V PWM Pin 37 VSS 34 5 kΩ 34 500 Ω Pin 1 VCC1 100 kΩ RST: Capacitor coupling pin for power-on reset VDB in: Vertical synchronous pulse input pin High or Low 50 kΩ Pin 37 VSS 35 Pin 40 VDD 35 10 kΩ 45.2 kΩ Pin 37 VSS SDB00080AEB 19 AN2526NFH ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit 36 Pin 40 VDD 36 Description Voltage · Waveform Ext. pol.: 1H reverse signal input pin High or Low 5 kΩ 50.2 kΩ Pin 37 VSS 37 VSS : MOS system GND 38 Pin 40 VDD 38 5 kΩ 50.2 kΩ Clamp in: Clamp pulse input pin Valid only in the external clamp mode. Positive polarity input. High or Low DAC mon.: DAC DC voltage output pin DC VDD: Capacitor connection pin for MOS part power supply. 3.0 V typ. GND 3: Pulse system GND PRGB: Analog OSD signal input Mode start-up signal input pin Valid only in the analog OSD mode High = Analog OSD start up High or Low Pin 37 VSS 39 Pin 1 VCC1 1.5 pF 39 200 Ω 2 kΩ 25 kΩ 20 kΩ 40 41 Pin 59 GND Pin 40 VDD 42 42 5 kΩ 53.8 kΩ Pin 37 VSS 20 SDB00080AEB AN2526NFH ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit 43 Description Pin 1 VCC1 2 kΩ AFC det.: AFC filter connection pin Input impedance; 100 kΩ or more 1 kΩ 43 Voltage · Waveform 1H 1 kΩ 2 kΩ Pin 59 GND 44 10 kΩ Pin 1 VCC1 10 kΩ 5 pF 44 H fO: VCO oscillation frequency adjusting resistor connection pin HSS in: H-sync. input pin Separates a sync signal from luminance signal (video signal) Input signal example: Video signal Bus-ch: Switching pin for serial threewire control/I2C Bus control High = I2C Bus Open or Low = Serial threewire control High or Low 2 kΩ Pin 59 GND 45 8.4 kΩ Pin 1 VCC1 Pin 2 VREF 45 20 kΩ 46 20 kΩ Pin 59 GND Pin 40 VDD 46 4 kΩ 50 kΩ Pin 37 VSS 47 Pin 40 VDD 47 DAC: Serial clock input pin 4 kΩ 50 kΩ Pin 37 VSS SDB00080AEB 21 AN2526NFH ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description 48 Pin 40 VDD 50 Ω 4 kΩ DAT: Serial data input pin 500 Ω ACK 48 Pin 37 VSS 49 Pin 59 GND Pin 48 VDD 49 Voltage · Waveform 4 kΩ 50 kΩ Pin 41 VSS 50 1 kΩ 1 kΩ Pin 1 VCC1 2 kΩ LEN: Load pulse input pin, also works as the slave address conversion pin in the I 2 C mode. High = "88" Low = "8A" High or Low ACC det.: ACC capacitor connecting pin, adjusting the amplitude of a burst signal automatically C in: Chroma signal input pin Input chroma signal (video signal) Input signal example: Video signal L.det.: Capacitor coupling pin for the horizontal unlock detecting circuit 1 kΩ 50 5 kΩ 5 kΩ 1 kΩ Pin 59 GND 51 Pin 1 VCC1 51 50 kΩ Pin 59 GND 52 Pin 1 VCC1 200 Ω 60 Ω 52 10 kΩ 60 Ω 12 kΩ Pin 59 GND 22 SDB00080AEB AN2526NFH ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit 53 Pin 1 VCC1 72 kΩ 53 1.5 kΩ 90 kΩ 54 Pin 1 VCC1 41 kΩ 54 Voltage · Waveform Kill det.: Killer capacitor coupling pin. To prevent degradation of image in a small amplitude of a burst signal, this pin stops a chroma signal and the mode changes to black and white mode. APC det.: APC capacitor coupling pin. Matching the phase of a crystal oscillation to that of burst signal. Pin 59 GND 31 kΩ 1 kΩ 1 kΩ Description 5 kΩ 50 kΩ 5 kΩ 100 kΩ 2 kΩ 1 kΩ 50 kΩ 2 kΩ 45 kΩ Pin 59 GND 55 26 kΩ Pin 1 VCC1 VXOI : Xtal connecting pin The pair with pin 56 NTSC 3.58 MHz PAL 4.43 MHz VXOO : Xtal connecting pin The pair with pin 55 Output impedance; Approximately 100 Ω NTSC 3.58 MHz PAL 4.43 MHz 6 kΩ 55 400 Ω 5 kΩ 26 kΩ 15 pF 56 500 Ω Pin 59 GND Pin 1 VCC1 56 500 Ω Pin 59 GND SDB00080AEB 23 AN2526NFH ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit 57 1 kΩ Pin 1 VCC1 1 kΩ Description Voltage · Waveform Y-det.: Capacitor coupling pin for luminance signal clamping Trap: Trap connecting pin Trapping a chroma signal by connecting external inductor and capacitor. Not necessary in case that an input signal is a component. GND 3: GND for chroma and luminance signal process blocks Y-in: Luminance signal input pin Input luminance signal (video signal) Input signal example: Video signal R-Y out: R-Y signal output pin, demodulated from a video signal R-Y signal 57 2 kΩ Pin 59 GND 58 Pin 1 VCC1 2 kΩ 58 1 kΩ 50 Ω 60 2 kΩ 2 kΩ Pin 59 GND 59 60 Pin 1 VCC1 20 kΩ 60 50 Ω 2 kΩ 2 kΩ 1 kΩ 58 2 kΩ Pin 59 GND 61 1 kΩ Pin 1 VCC1 61 1H 1 kΩ 24 Pin 59 GND SDB00080AEB AN2526NFH ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit 62 Pin 1 VCC1 1 kΩ Description Voltage · Waveform B-Y out : B-Y signal output pin, demodulated from a video signal B-Y signal 62 1H 1 kΩ Pin 59 GND 63 5 kΩ 2 kΩ 5 kΩ 5 kΩ 2 kΩ 5 kΩ Pin 59 GND Pin 1 VCC1 B-Y in : B-Y signal input pin in a color difference mode and standard PAL. B-Y signal 17.5 kΩ 64 5 kΩ Pin 2 VREF R-Y signal 1H 64 5 kΩ R-Y in: R-Y signal input pin in a color difference mode and standard PAL. 17.5 kΩ 63 5 kΩ Pin 2 VREF Pin 1 VCC1 5 kΩ 1H 5 kΩ 5 kΩ Pin 59 GND ■ Usage Notes • You are required to study adequately before using it in PAL. • If the duty of PWM output is set to other than 0% to 100%, the jitter of the HD out put increases. So, confirm the horizontal jitter amount on the screen of the set you introduce the PWM function into. SDB00080AEB 25 AN2526NFH ■ Technical Data Serial data control In addition to its serial control by the conventional three-wire method, the AN2526NFH can be controlled by the I2C Bus. The transmission method is selected by the voltage to be applied to Pin 46. Three-wire control mode: Pin 46 = Low-level (connect to GND) I2C Bus mode: Pin 46 = High-level (Pin 41: connect to VDD ) It is recommended that the serial data is transferred during a vertical blanking period. 1. Three-wire control mode A serial data is of three-line system transmitting three kinds of signals of data, shift clock and load pulse independently. The data to be transmitted is made up by 12 bits in total of address (4 bits) and data (8 bits). The DAC is composed of four blocks of serial-parallel conversion, address decoder, data latch and ladder resistors, enabling to control 16 channels in total. Further, the mode setting such as the input signal switching is done by a serial data to reduce the pin count. 1) Serial data format D11 D10 D9 D8 D7 D6 D5 D4 Address block D3 D2 D1 Data block 2) Serial data input timing chart Pin 48 S-data D11 D10 D2 D1 D0 Pin 47 SCLK Pin 49 LD Timing chart expanded diagram tCKH tcf Pin 47 SCLK tcr tCKL tLDC Pin 48 S-data Pin 49 LD 26 tLDH tDCH tCHD tCHL SDB00080AEB D0 AN2526NFH ■ Technical Data (continued) 1. Three-wire control mode (continued) 2) Serial data input timing chart (continued) Parameter Symbol Min Max Unit Clock low-level pulse width tCKL 500 ns Clock high-level pulse width tCKH 500 ns Clock rise time tcr 20 ns Clock fall time tcf 20 ns Data setup time tDCH 30 ns Data hold time tCHD 60 ns Load setup time tCHL 200 ns Load hold time tLDC 100 ns Load high-level pulse width tLDH 500 ns 3) Serial-data control contents D11 D10 D9 D8 Selection-ch. EVR control function Number of bit 0 0 0 0 0 Vertical sync. signal output position 3 1 0 0 0 1 Horizontal sync. signal output position 5 0 1 0 0 2 PWM duty 6 1 1 0 0 3 Common pulse amplitude 7 0 0 1 0 4 Y-gain 8 1 0 1 0 5 Color gain 7 0 1 1 0 6 Hue 7 1 1 1 0 7 Black-limiter level 8 0 0 0 1 8 Bright 8 1 0 0 1 9 Y-aperture gain 8 0 1 0 1 10 R-ch. sub brightness 8 1 1 0 1 11 B-ch. sub brightness 8 0 0 1 1 12 White peak limiter level 8 1 0 1 1 13 Gamma-1 Knee level 8 0 1 1 1 14 Gamma-2 Knee level 8 1 1 1 1 15 RGB contrast 7 A variety of mode-settings for the channel for 8 bits or less is made by using the data stored in the data block. The contents of each mode setting are shown next. SDB00080AEB 27 AN2526NFH ■ Technical Data (continued) 1. Three-wire control mode (continued) 4) Mode setup channel bit-map. • ch.0: Vertical sync. output position adjustment D11 D10 D9 D8 D7 D6 D5 D4 to D3 D2 D1 D0 EXCHF FIXHD BOSC Hor. PLL start position adjustment 0 0 0 0 0 Automatic switching 1 263H/313H fixed (NTSC/PAL) 0 HD/VD output timing is serially variable 1 HD/VD output timing fixed 0 Odd number field: Advanced phase 1 Even number field: Advanced phase • Vertical sync. output timing adjusting range Composite sync. signal odd number field Pin 35 input Pin 31 output odd number field FIXHD = "0" 8H 2H to 9H(D0 to D2) Pin 31 output odd number field FIXHD = "1" 3Η Composite sync. signal even number field Pin 31 output EXCHF = "1" FIXHD = "0" Pin 31 output EXCHF = "1" FIXHD = "1" Pin 31 output EXCHF = "0" FIXHD = "1" 8H 1.5H to 8.5H(D0 to D2) 3Η 8H 2.5H to 9.5H (D0 to D2) The above timing chart indicates (D2,D1,D0) = "101". For (D2,D1,D0) = "000", the pin 31 output width is 9H. Pin 31 output EXCHF = "0" FIXHD = "1" 3Η The pin 31 timing is synchronous with the pin 35 input timing. The above timing chart is just for your reference. 28 SDB00080AEB AN2526NFH ■ Technical Data (continued) 1. Three-wire control mode (continued) 4) Mode setup channel bit-map. (continued) • Horizontal PLL start position adjustment range 0-line Composite sync. signal odd number field 1 2 3 Pin 35 input 6H to 9H (D3 to D4) Horizontal PLL off Odd number field Horizontal PLL on Composite sync. signal even number field 5.5H to 8.5H (D3 to D4) EXCHF = "1" Horizontal PLL off EXCHF = "0" Horizontal PLL off Horizontal PLL on 6.5H to 9.5H (D3 to D4) Horizontal PLL on • ch.1: Horizontal sync. output position adjustment D11 1 D10 0 D9 0 D8 0 Composite sync. signal input (video signal) Pin 30 Composite sync. signal output Pin 32 Horizontal sync. signal output (D4,D3,D2,D1,D0) = (00000) Pin 32 Horizontal sync. signal output (D4,D3,D2,D1,D0) = (11111) Pin 32 Horizontal sync. signal output ch.0 (D6) = "1" The above timing chart indicates (D4,D3) = "01". PLL stop line number: 254-line (NTSC) 302-line (PAL) D7 V Mode D6 YUV D5 RGB 0 Video signal input display mode 1 Analog RGB input display mode 0 Chroma signal input mode 1 Color-difference signal input mode 0 PAL 1 NTSC D4 D3 D2 D1 D0 Sync. sepa. delay time (Approximately 1 µs) 32fy 31fy 32fy 1 (NTSC/PAL) 347fh Delay time (Approximately 400 ns) fh: Horizontal sync. frequency 18fy 1fy = The delay time of pin 30 output to video signal is likely to vary according to an external constant connected to pin 45. For an external constant, you are required to evaluate adequately the characteristics in weak electric field. Though the horizontal sync signal output adjustment range is designed by referring to the center of pin 30 output pulse, there would be some error according to VCO free-run frequency. SDB00080AEB 29 AN2526NFH ■ Technical Data (continued) 1. Three-wire control mode (continued) 4) Mode setup channel bit-map. (continued) • ch.2: PWM duty adjustment D11 0 D10 1 D9 0 D8 0 D7 D6 P mode YC mode D5 D4 D3 D2 D1 D0 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 0 Composite input mode 1 Component input mode 0 STD PAL mode 1 Quasi PAL/NTSC mode 0 to 58H fh : (NTSC/PAL) 58 Note that adjustment characteristics come to discontinuation around max. Duty. (D5,D4,D3,D2,D1,D0) = (000000): tw = 1H = (000001): tw = 3H = (000010): tw = 4H = (110110): tw = 56H = (110111): tw = 56H = (111000): tw = 0H = (111001): tw = 58H • ch.3: Common pulse amplitude adjustment D11 D10 D9 D8 D7 OSD D6 D5 D4 D3 1 1 0 0 0 Analog OSD signal input mode 1 Digital OSD signal input mode • ch.5: Color gain adjustment D11 D10 D9 D8 D7 HTS D6 D5 D4 1 0 1 0 0 1H reverse inhibit mode 1 1H reverse mode • ch.6: Hue adjustment D11 D10 D9 D8 D7 CP 0 1 1 0 0 External clamp pulse input mode 1 Internal clamp (pedestal) mode 30 D6 D5 SDB00080AEB D4 AN2526NFH ■ Technical Data (continued) 1. Three-wire control mode (continued) 4) Mode setup channel bit-map. (continued) • ch.9: Y-aperture gain adjustment D11 D10 D9 D8 1 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 D5 D4 D3 D2 D1 D0 00h, 01h: Test mode • ch.15: RGB contrast adjustment D11 D10 D9 D8 D7 POL mode D6 1 1 1 1 0 Internal POL 1H reverse mode 1 External POL 1H reverse mode 2. I2C control mode A serial data is capable of transferring 9-bit unit of 8-bit transfer data and 1-bit answering data using two kinds of signal lines of data and shift clock. When a slave address after setting a start condition matches the address on the IC side, you can receive the data to be transmitted from then. Once the stop condition is set up, the next transmitting data will be ignored until the start condition is set up. There are two kinds of transfer mode: an auto-increment mode which does not transmit sub-address, and data upgrade mode which transmits sub-address + data by 2 bites. The typical models of transmitting sequence are shown below: 1) Start condition When the S data changes from high-level to low-level at SCLK = high-level, a data receiving mode becomes available. 2) Slave address transfer The slave address of the AN2526NFH is 88h at pin 49 = high-level and 8Ah at pin 49 = low-level. Pin 48 S-data 1 2 3 4 5 6 7 8 9 1 2 Pin 47 SCLK Sub address transfer Start condition Acknowledge bit 3) Sub address transfer When a data transfer mode bit is 0, all the serial data columns transferred until a stop condition is set is regarded as the data block. Pin 48 S-data 8 9 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 1 2 Pin 47 SCLK Data transfer Slave address transfer Data transfer mode bit "1": Data update mode "0": Auto increment mode SDB00080AEB Acknowledge bit 31 AN2526NFH ■ Technical Data (continued) 2. I2C control mode (continued) 4) Data transfer Pin 48 S-data 8 9 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 1 2 Pin 47 SCLK Acknowledge bit At auto increment mode: Data transfer At data update mode: Sub address transfer 5) Stop condition When S-data changes from low-level to high-level at SCLK = high-level, data reception is halted. 6) Pulse timing Timing chart expanded diagram Pin 48 S-data tBUF tHDDAT tLOW tf Pin 47 SCLK tSUSTO tHDSTA tr tHIGH Parameter tSUDAT Symbol Min Typ Max Unit SCLK clock frequency tSCL 0 400 kHz Bus free-time for stop condition and start condition tBUF 1.3 µs tHDSTA 0.6 µs SCLK clock low-state hold time tLOW 1.3 µs SCLK clock high-state hold time tHIGH 0.6 µs Data hold time tHDDAT 0 µs Data setup time tSUDAT 100 ns S-data, SCLK signal rise time tr 300 ns S-data, SCLK signal fall time tf 300 ns tSUSTO 0.6 µs Hold time start condition Stop condition setup time 32 SDB00080AEB AN2526NFH ■ Technical Data (continued) 2. I2C control mode (continued) 6) Pulse timing (continued) D7 D6 to D4 Mode Don't Care D3 D2 D1 D0 Selection channel Number of bit 0 0 0 0 0 Vertical sync. signal output position 3 0 0 0 1 1 Horizontal sync. signal output position 5 0 0 1 0 2 PWM duty 6 0 0 1 1 3 Common pulse amplitude 7 0 1 0 0 4 Y-gain 8 0 1 0 1 5 Color gain 7 0 1 1 0 6 Hue 7 0 1 1 1 7 Black-limiter level 8 1 0 0 0 8 Bright 8 1 0 0 1 9 Y-aperture gain 8 1 0 1 0 10 R-ch. sub bright 8 1 0 1 1 11 B-ch. sub bright 8 1 1 0 0 12 White peak limiter 8 1 1 0 1 13 Gamma-1 Knee level 8 1 1 1 0 14 Gamma-2 Knee level 8 1 1 1 1 15 RGB contrast 7 EVR control function In case that the ch. has 8 bits or less of data bit number, the data in the data block is used to set various modes. The content of each mode setting is same as three-wire control mode 3. Recommended Operating Conditions Parameter Symbol Range Min Typ Max Unit Composite video input signal YIN Sync. chip - white 0.9 1.0 1.1 V[p-p] Y-input signal voltage YIN Pedestal - white 0.6 0.7 0.8 V[p-p] C-input signal voltage CIN Burst signal amplitude 200 300 400 mV[p-p] 0 0.8 V 2.3 *1 V 0.2 0.3 0.4 V[p-p] 1.0 MHz 0.6 0.7 0.8 V[p-p] MOS input signal low-level voltage VMOSL MOS input signal high-level voltage VMOSH Synchronous signal input Serial data transfer frequency Analog RGB input signal HSYNC Pedestal - sync. chip fSD RGBIN Pedestal - white Note) *: Set it lower than VCC1 (Pin 1 voltage). SDB00080AEB 33 AN2526NFH ■ Technical Data (continued) 4. PD Ta curves of QFP064-P-1010 PD T a 1.600 1.576 Mounted on standard board (glass epoxy: 75 × 75 × t0.8mm3) Rth(j-a) = 79.3°C/W 1.400 Power dissipation PD (W) 1.200 1.000 0.814 0.800 0.600 Independent IC without a heat sink Rth(j-a) = 153.5°C/W 0.400 0.200 0.000 0 50 25 75 100 125 150 Ambient temperature Ta (°C) ■ New Package Dimensions (Unit: mm) • QFP064-P-1010A (Lead-free package) 12.00±0.20 10.00±0.20 48 33 1 16 0.18±0.05 0.50 0.10 Seating plane 0.15±0.05 (1.00) 0° to 10° 0.50±0.20 34 SDB00080AEB 0.10 M 1.95±0.20 17 0.10±0.10 (1.25) 12.00±0.20 (1.25) 64 10.00±0.20 32 49 Request for your special attention and precautions in using the technical information and semiconductors described in this material (1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuit examples of the products. It does not constitute the warranting of industrial property, the granting of relative rights, or the granting of any license. (3) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: • Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. • Any applications other than the standard applications intended. (4) The products and product specifications described in this material are subject to change without notice for reasons of modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, redundant design is recommended, so that such equipment may not violate relevant laws or regulations because of the function of our products. (6) When using products for which dry packing is required, observe the conditions (including shelf life and after-unpacking standby time) agreed upon when specification sheets are individually exchanged. (7) No part of this material may be reprinted or reproduced by any means without written permission from our company. Please read the following notes before using the datasheets A. These materials are intended as a reference to assist customers with the selection of Panasonic semiconductor products best suited to their applications. Due to modification or other reasons, any information contained in this material, such as available product types, technical data, and so on, is subject to change without notice. Customers are advised to contact our semiconductor sales office and obtain the latest information before starting precise technical research and/or purchasing activities. B. Panasonic is endeavoring to continually improve the quality and reliability of these materials but there is always the possibility that further rectifications will be required in the future. Therefore, Panasonic will not assume any liability for any damages arising from any errors etc. that may appear in this material. C. These materials are solely intended for a customer's individual use. Therefore, without the prior written approval of Panasonic, any other use such as reproducing, selling, or distributing this material to a third party, via the Internet or in any other way, is prohibited. 2001 MAR