W19B160BT/B DATA SHEET -Table of Contents1. GENERAL DESCRIPTION ......................................................................................................... 4 2. FEATURES ................................................................................................................................. 4 3. PIN CONFIGURATIONS ............................................................................................................ 6 4. BLOCK DIAGRAM ...................................................................................................................... 7 5. PIN DESCRIPTION..................................................................................................................... 8 6. FUNCTIONAL DESCRIPTION ................................................................................................... 9 6.1 6.2 6.3 DEVICE BUS OPERATION............................................................................................ 9 6.1.1 Word/Byte Configuration ..................................................................................................9 6.1.2 Reading Array Data ..........................................................................................................9 6.1.3 Writing Commands/Command Sequences.......................................................................9 6.1.4 Program and Erase Operation Status...............................................................................9 6.1.5 Standby Mode ..................................................................................................................9 6.1.6 Automatic Sleep Mode ...................................................................................................10 6.1.7 #RESET: Hardware Reset Pin........................................................................................10 6.1.8 Output Disable Mode......................................................................................................10 6.1.9 Auto-select Mode............................................................................................................10 6.1.10 Sector Protection and Un-protection.............................................................................11 6.1.11 Temporary Sector Unprotect ........................................................................................11 6.1.12 Hardware Data Protection ............................................................................................11 6.1.13 Write Pulse “Glitch” Protection .....................................................................................11 6.1.14 Logical Inhibit ...............................................................................................................11 6.1.15 Power-Up Write Inhibit..................................................................................................11 COMMAND DEFINITIONS ........................................................................................... 12 6.2.1 Reading Array Data ........................................................................................................12 6.2.2 Reset Command.............................................................................................................12 6.2.3 Auto-select Command Sequence ...................................................................................12 6.2.4 Byte/Word Program Command Sequence......................................................................13 6.2.5 Chip Erase Command Sequence ...................................................................................13 6.2.6 Sector Erase Command Sequence ................................................................................13 6.2.7 Unlock Bypass Command Sequence .............................................................................14 WRITE OPERATION STATUS..................................................................................... 14 6.3.1 DQ7: #Data Polling.........................................................................................................14 6.3.2 RY/#BY: Ready/#Busy ...................................................................................................15 6.3.3 DQ6: Toggle Bit..............................................................................................................15 -1- Publication Release Date:Apr. /20/2009 Revision A9 W19B160BT/B DATA SHEET 6.3.4 Reading Toggle Bits DQ6/DQ2 ......................................................................................15 6.3.5 DQ3: Sector Erase Timer ...............................................................................................16 6.3.6 DQ5 : Exceeded Timing Limits .......................................................................................16 7. SPECIAL CHARACTERISTIC .................................................................................................. 16 8. TABLE OF OPERATION MODES ............................................................................................ 17 9. 10. 8.1 Device Bus Operations ................................................................................................. 17 8.2 Sector Address Table (Top Boot Block) ....................................................................... 18 8.3 Sector Address Table (Bottom Boot Block) .................................................................. 19 8.4 CFI Query Identification String...................................................................................... 20 8.5 System Interface String ................................................................................................ 20 8.6 Device Geometry Definition .......................................................................................... 21 8.7 Primary Vendor-Specific Extended Query.................................................................... 22 8.8 Command Definitions ................................................................................................... 23 8.9 Write Operation Status ................................................................................................. 24 8.10 Temporary Sector Unprotect Algorithm ........................................................................ 25 8.11 In-System Sector Protect/Unprotect Algorithms........................................................... 26 8.12 Program Algorithm........................................................................................................ 27 8.13 Erase Algorithm (Polling) .............................................................................................. 27 8.14 Erase Algorithm (Toggle).............................................................................................. 28 8.15 Data Polling Algorithm .................................................................................................. 29 8.16 Toggle Bit Algorithm ..................................................................................................... 30 ELECTRICAL CHARACTERISTICS......................................................................................... 31 9.1 Absolute Maximum Ratings .......................................................................................... 31 9.2 Operating Ranges......................................................................................................... 31 9.3 DC CHARACTERISTICS.............................................................................................. 32 9.4 AC CHARACTERISTICS.............................................................................................. 33 9.4.1 Test Condition ................................................................................................................33 9.4.2 AC Test Load and Waveforms .......................................................................................33 9.4.3 Read-Only Operations....................................................................................................34 9.4.4 Read-Only Operations....................................................................................................34 9.4.5 Hardware Reset (#RESET) ............................................................................................35 9.4.6 Word/Byte Configuration (#BYTE)..................................................................................35 9.4.7 Erase and Program Operation........................................................................................36 9.4.8 Temporary Sector Unprotect ..........................................................................................36 9.4.9 Alternate #CE Controlled Erase and Program Operation ...............................................37 TIMING WAVEFORMS ............................................................................................................. 38 10.1 AC Read Waveform...................................................................................................... 38 -2- W19B160BT/B DATA SHEET 10.2 Reset Waveform ........................................................................................................... 38 10.3 #BYTE Waveform for Read Operation ......................................................................... 39 10.4 #BYTE Waveform for Write Operation ......................................................................... 39 10.5 Programming Waveform............................................................................................... 40 10.6 Chip/Sector Erase Waveform ....................................................................................... 40 10.7 #Data Polling Waveform (During Embedded Algorithms) ............................................ 41 10.8 Toggle Bit Waveform (During Embedded Algorithms) ................................................. 41 10.9 Temporary Sector Unprotect Timing Diagram.............................................................. 42 10.10 Sector Protect and Unprotect Timing Diagram ........................................................ 42 10.11 Alternate #CE Controlled Write (Erase/Program) Operation Timing ....................... 43 11. LATCHUP CHARACTERISTICS .............................................................................................. 44 12. CAPACITANCE......................................................................................................................... 44 13. ORDERING INFORMATION .................................................................................................... 45 Quality: Grade & Green H: Extended (-20℃ ~85 ℃ )with Green package M:Industrial (-40℃ ~85 ℃ )with Green package SPEEDOPTION 7 : 70 ~ 79ns 9 : 90 ~ 99ns PACKAGE TYPE T = 48 - Pin TSOP Package, 12 x 20mm BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION W19B160B 16 Megabit (2M x-8Bit/ 1 M x 16- Bit) CMOS Flash Memory PACKAGE DIMENSIONS ..................................................................................................................... 45 PACKAGE DIMENSIONS ..................................................................................................................... 46 14. VERSION HISTORY ................................................................................................................. 47 -3- Publication Release Date Apr,20, 2009 Revision A9 W19B160BT/B DATA SHEET 1. GENERAL DESCRIPTION The W19B160B is a 16Mbit, 2.7~3.6 volt CMOS flash memory organized as 2M × 8 or 1M × 16 bits. For flexible erase capability, the 16Mbits of data are divided into one 16Kbyte, two 8Kbyte, one 32Kbyte, and thirty-one 64Kbyte sectors. The word-wide (× 16) data appears on DQ15-DQ0, and byte-wide (× 8) data appears on DQ7−DQ0. The device can be programmed and erased in-system with a standard 2.7~3.6V power supply. A 12-volt VPP is not required. The unique cell architecture of the W19B160B results in fast program/erase operations with extremely low current consumption. The device can also be programmed and erased by using standard EPROM programmers. 2. FEATURES Performance • 2.7~3.6-volt write (program and erase) operations • Fast write operation − Sector erase time: 0.7s (Typical) − Chip erases time: 25 s (Typical) − Byte/Word programming time: 5/7 µs (Typical) • Read access time: 70 ns • Typical program/erase cycles: − 100K • Twenty-year data retention • Ultra low power consumption − Active current (Read): 9mA (Typical) − Active current (Program/erase): 20mA (Typical) − Standby current: 0.2 μA (Typical) Architecture • Sector erases architecture − One 16Kbyte, two 8Kbyte, one 32Kbyte, and thirty-one 64Kbyte sectors − Top or bottom boot block configurations available − Supports full chip erase • JEDEC standard byte-wide and word-wide pin-outs TTL compatible I/O • Manufactured on WinStack-S 0.13µm process technology • Available packages: 48-pin TSOP Software Features • Compatible with common Flash Memory Interface (CFI) specification − Flash device parameters stored directly on the device − Allows software driver to identify and use a variety of different current and future Flash products • End of program detection -4- W19B160BT/B DATA SHEET • − Software method: Toggle bit/Data polling Unlock bypass program command − Allows the system to program bytes or words to device faster than standard program command. Hardware Features • Ready/#Busy output (RY/#BY) − Detect program or erase cycle completion • Hardware reset pin (#RESET) − Reset the internal state machine to the read mode • Sector Protection − Sectors can be locked in-system or via programmer − Temporary Sector Unprotect allows changing data in protected sectors in-system Temperature range • Extended temperature range (-20℃ to 85 ℃) • Industrial devices ambient temperature(-40℃ to +85℃) -5- Publication Release Date Apr,20, 2009 Revision A9 W19B160BT/B DATA SHEET 3. PIN CONFIGURATIONS -6- W19B160BT/B DATA SHEET 4. BLOCK DIAGRAM -7- Publication Release Date Apr,20, 2009 Revision A9 W19B160BT/B DATA SHEET 5. PIN DESCRIPTION SYMBOL PIN NAME A0−A19 Address Inputs DQ0−DQ14 Data Inputs/Outputs DQ15/A-1 Word mode DQ15 is Data Inputs/Outputs Byte mode A-1 is Address input #CE Chip Enable #OE Output Enable #WE Write Enable #BYTE Byte Enable Input #RESET Hardware Reset RY/#BY Ready/Busy Status VDD Power Supply VSS Ground NC No Connection -8- W19B160BT/B DATA SHEET 6. FUNCTIONAL DESCRIPTION 6.1 6.1.1 DEVICE BUS OPERATION Word/Byte Configuration The #BYTE pin controls the device data I/O pins operate whether in the byte or word configuration. When the #BYTE pin is ‘1’, the device is in word configuration; DQ15-DQ0 are active and controlled by #CE and #OE. When the #BYTE pin is ‘0’, the device is in byte configuration, and only data I/O pins DQ7-DQ0 are active and controlled by #CE and #OE. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. 6.1.2 Reading Array Data To read array data from the outputs, the #CE and #OE pins must be set to VIL. #CE is the power control and used to select the device. #OE is the output control gates array data to the output pins. #WE should stay at VIH. The #BYTE pin determines the device outputs array data whether in words or bytes. The internal state machine is set for reading array data when device power-up, or after hardware reset. This ensures that no excess modification of the memory content occurs during the power transition. In this mode there is no command necessary to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are changed. 6.1.3 Writing Commands/Command Sequences In writhing a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive #WE and #CE to VIL, and #OE to VIH. For program operations, the #BYTE pin determines the device accepts program data whether in bytes or in words. Refer to “Word/Byte Configuration” for more information. The erase operation can erase a sector, multiple sectors, even the entire device. The “sector address” is the address bits required to solely select a sector. 6.1.4 Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7 – DQ0. Refer to “Write Operation Status” and “AC Characteristics” for more information. 6.1.5 Standby Mode When the system is not reading or writing to the device, the device will be in a standby mode. In this mode, current consumption is greatly reduced, and the outputs are in the high impedance state, independent from the #OE input. When the #CE and #RESET pins are both held at VDD ± 0.3V, the device enters into the CMOS standby mode (note that this is a more restricted voltage range than VIH.) When #CE and #RESET are -9- Publication Release Date Apr,20, 2009 Revision A9 W19B160BT/B DATA SHEET held at VIH, but not within VDD ± 0.3V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. When the device is deselected during erasing or programming, the device initiates active current until the operation is completed. 6.1.6 Automatic Sleep Mode The automatic sleep mode minimizes device's energy consumption. When addresses remain stable for tACC +30 nS, the device will enable this mode automatically. The automatic sleep mode is independent from the #CE, #WE, and #OE control signals. Standard address access timings provide new data when addresses are changed. In sleep mode, output data is latched and always available to the system. 6.1.7 #RESET: Hardware Reset Pin The #RESET pin provides a hardware method to reset the device to reading array data. When the #RESET pin is set to low for at least a period of tRP, the device will immediately terminate every operations in progress, tri-states all output pins, and ignores all read/write commands for the duration of the #RESET pulse. The device also resets the internal state machine to reading array data mode. To ensure data integrity, the interrupted operation needs to be reinitiated when the device is ready to accept another command sequence. Current is reduced for the duration of the #RESET pulse. When #RESET is held at Vss ± 0.3V, the device initiates the CMOS standby current (ICC4). If #RESET is held at VIL but not within Vss ± 0.3V, the standby current will be greater. The #RESET pin may be tied to the system-reset circuitry. Thus the system reset would also reset the device, enabling the system to read the boot-up firmware from the device. If #RESET is asserted during the program or erase operation, the RY/#BY pin will be at “0” (busy) until the internal reset operation is complete. If #RESET is asserted when a program or erase operation is not processing (RY/#BY pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). After the #RESET pin returns to VIH, the system can read data tRH. 6.1.8 Output Disable Mode When the #OE input is at VIH, output from the device is disabled. The output pins are set in the high impedance state. 6.1.9 Auto-select Mode The auto select mode offers manufacturer and device identification, as well as sector protection verification, through identifier codes output on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the auto select codes can also be accessed in-system through the command register. When using programming equipment, the auto select mode requires VID (8.5 V to 11.5 V) on address pins A9. Address pins A6, A1, and A0 must be as shown in auto select table. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. - 10 - W19B160BT/B DATA SHEET To access the auto select codes in-system, the host system can issue the auto select command through the command register. This method does not require VID. Also refer to the auto select Command Sequence section for more information. 6.1.10 Sector Protection and Un-protection The sector protection feature will disable both program and erase operations in any sectors. The sector un-protection feature will re-enables both program and erase operations in previously protected sectors. Sector protection / un-protection can be implemented through two methods. The primary method requires VID on the #RESET pin, and can be implemented either in-system or through programming equipment. This method uses standard microprocessor bus cycle timing. The alternate method intended only for programming equipment requires VID on address pin A9 and #OE It is possible to determine whether a sector is protected or unprotected. See the auto select Mode section for details. 6.1.11 Temporary Sector Unprotect This feature allows temporary un-protection of previously protected sectors to change data in-system. When the #RESET pin is set to VID, the Sector Unprotect mode is activated. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. What if VID is removed from the #RESET pin, all the previously protected sectors are protected again. 6.1.12 Hardware Data Protection The command sequence requirements of unlock cycles for programming or erasing provides data protection against negligent writes. In addition, the following hardware data protection measures prevent inadvertent erasure or programming, which might be caused by spurious system level signals during VDD power-up and power-down transitions, or from system noise. 6.1.13 Write Pulse “Glitch” Protection Noise pulses, which is less than 5nS (typical) on #OE, #CE or #WE, do not initiate a write cycle. 6.1.14 Logical Inhibit Write cycles are inhibited by holding any one of #OE = VIL, #CE = VIH or #WE = VIH. #CE and #WE must be a logical zero while #OE is a logical one to initiate a write cycle. 6.1.15 Power-Up Write Inhibit During power up, if #WE = #CE = VIL and #OE = VIH, the device does not accept commands on the rising edge of #WE. The internal state machine is automatically reset to the read mode on power-up. - 11 - Publication Release Date Apr,20, 2009 Revision A9 W19B160BT/B DATA SHEET 6.2 COMMAND DEFINITIONS The device operation can be initiated by writing specific address and data commands or sequences into the command register. The device will be reset to reading array data when writing incorrect address and data values or writing them in the improper sequence. The addresses will be latched on the falling edge of #WE or #CE, whichever happens later; while the data will be latched on the rising edge of #WE or #CE, whichever happens first. Please refer to timing waveforms. 6.2.1 Reading Array Data After device power-up, it is automatically set to reading array data. There is no commands are required to retrieve data. After completing an Embedded Program or Embedded Erase algorithm, the device is ready to read array data. The system must initiate the reset command to return the device to read mode if DQ5 goes high during an active program or erase operation; otherwise, the device is in the auto select mode. See Reset Command section and Requirements for Reading Array Data in the Device Bus Operations section for more information. 6.2.2 Reset Command The device will be to the read when writing the reset command. For this command, the address bits are Don’t Care. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device, to which the system was writing to the read mode. The reset command may be written between the sequence cycles in an auto select command sequence. When in the auto select mode, the reset command must be written to return to the read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode. 6.2.3 Auto-select Command Sequence The auto select command sequence provides the host system to access the manufacturer and device codes, and determine whether a sector is protected or not. This is an alternative method, which is intended for PROM programmers and requires VID on address pin A9. The auto select command sequence may be written to an address within the device that is in the read mode. When the device is actively programming or erasing, the auto select command may not be written. The first writing two unlock cycles initiate the auto select command sequence. This is followed by a third write cycle that contains the auto select command. The device then enters into the auto select mode. The system may read at any address without initiating another auto select command sequence: • A read cycle at address XX00h returns the manufacturer code. • A read cycle at address XX01h in word mode (or XX02h in byte mode) returns the device code. • A read cycle to an address containing a sector address (SA), and the address 02h on A7-A0 in word mode (or the address 04h in byte mode) returns 01h if the sector is protected, or 00h if it is unprotected. - 12 - W19B160BT/B DATA SHEET To return to read mode and exit the auto select mode, the system must write the reset command. 6.2.4 Byte/Word Program Command Sequence The device can be programmed either by word or byte, which depending on the state of the #BYTE pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program setup command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Once the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/#BY. Please refer to the Write Operation Status section for bits' information. Any commands written to the device during the Embedded Program Algorithm are ignored. Please note that a hardware reset will immediately stop the program operation. The program command sequence should be reinitiated when the device has returned to the read mode, in order to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to “1.” If trying to do so may cause that device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate that the operation is successful. However, a succeeding read will show that the data is still “0.” Only erase operations can change “0” to “1.” 6.2.5 Chip Erase Command Sequence Chip erase is a six-bus cycle operation. Writing two unlock cycles initiates the chip erase command sequence, which is followed by a set-up command. After chip erase command, two additional unlock write cycles are then followed, which in turn invokes the Embedded Erase algorithm. The system preprogram is not required prior to erase. Before electrical erase, the Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern. Any controls or timings during these operations is not required in system. As the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or RY/#BY. Please refer to the Write Operation Status section for information on these status bits. Any commands written during the chip erase operation will be ignored. However, a hardware reset shall terminate the erase operation immediately. If this happens, to ensure data integrity, the chip erase command sequence should be reinitiated when the device has returned to reading array data. 6.2.6 Sector Erase Command Sequence Sector erase is a six-bus cycle operation. Writing two unlock cycles initiates the sector erase command sequence, which is followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. The device does not require the system to preprogram before erase. Before electrical erase, the Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern. Any controls or timings during these operations is not required in system. - 13 - Publication Release Date Apr,20, 2009 Revision A9 W19B160BT/B DATA SHEET As the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Please refer to the Write Operation Status section for information on these status bits. However, a hardware reset shall terminate the erase operation immediately. If this occurs, to ensure data integrity, the sector erase command sequence should be reinitiated once the device has returned to reading array data. 6.2.7 Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device enters the unlock bypass command mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Command Definitions shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-pass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data. Program/Erase operation refer Program Algorithm and Erase Algorithm illustration. 6.3 WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ5, DQ6, and DQ7. Each of DQ7 and DQ6 provides a method for determining whether a program or erase operation is complete or in progress. The device also offers a hardware-based output signal, RY/#BY, to determine whether an Embedded Program or Erase operation is in progress or has been completed. 6.3.1 DQ7: #Data Polling The #Data Polling bit, DQ7, indicates whether an Embedded Program or Erase algorithm is in progress or completed. Data Polling is valid after the rising edge of the final #WE pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 and the complement of the data programmed to DQ7. When the Embedded Program algorithm is complete, the device outputs the data programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, #Data Polling on DQ7 is active for about 1µS, and then the device returns to the read mode. During the Embedded Erase algorithm, #Data Polling produces “0” on DQ7.Once the Embedded Erase algorithm has completed, #Data Polling produces “1” on DQ7. An address within any of the sectors selected for erasure must be provided to read valid status information on DQ7. - 14 - W19B160BT/B DATA SHEET After an erase command sequence is written, if all sectors selected for erasing are protected, #Data Polling on DQ7 is active for about 100µS, and then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just before the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ0-DQ6 while Output Enable (#OE) is set to low. That is, the device may change from providing status information to valid data on DQ7. Depending on when it samples the DQ7 output, the system may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ0-DQ6 may be still invalid. Valid data on DQ7-DQ0 will appear on successive read cycles. 6.3.2 RY/#BY: Ready/#Busy The RY/#BY is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/#BY status is valid after the rising edge of the final #WE pulse in the command sequence. Since RY/#BY is an open-drain output, several RY/#BY pins can be tied together in parallel with a pull-up resistor to VDD. When the output is low (Busy), the device is actively erasing or programming. When the output is high (Ready), the device is in the read mode. 6.3.3 DQ6: Toggle Bit Toggle Bit on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete. Toggle Bit may be read at any address, and is valid after the rising edge of the final #WE pulse in the command sequence (before the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either #OE or #CE to control the read cycles. Once the operation has completed, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for about 100µS, and then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors which are protected. If a program address falls within a protected sector, DQ6 toggles for about 1 μs after the program command sequence is written, and then returns to reading array data. 6.3.4 Reading Toggle Bits DQ6/DQ2 Whenever the system initially starts to read toggle bit status, it must read DQ0−DQ7 at least twice in a row to determine whether a toggle bit is toggling or not. Typically, the system would note and store the value of the toggle bit after the first read. While after the second read, the system would compare the new value of the toggle bit with the first one. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ0−DQ7 on the following read cycle. However, if after the initial two read cycles, the system finds that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high or not(see the section on DQ5). If DQ5 is - 15 - Publication Release Date Apr,20, 2009 Revision A9 W19B160BT/B DATA SHEET high, the system should then determine again whether the toggle bit is toggling or not, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation, and the system must write the reset command to return to reading array data. Then the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, and determines the status as described in the previous paragraph. Alternatively, the system may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm while it returns to determine the status of the operation. 6.3.5 DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether erasure has begun or not. (The sector erase timer does not apply to the chip erase command.) The entire time-out applies after each additional sector erase command if additional sectors are selected for erasure. Once the timeout period has completed, DQ3 switches from “0” to “1.” If the time between additional sector erase commands from the system can be assumed to be less than 50 μS, the system need not monitor, DQ3 does not need to be monitored. Please also refer to Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (#Data Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is“1,” the Embedded Erase algorithm has begun; all further commands are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. The system software should check the status of DQ3 before and following each subsequent sector erase command to ensure the command has been accepted. If DQ3 is high on the second status check, the last command might not have been accepted. 6.3.6 DQ5 : Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. DQ5 produces “1” under these conditions which indicates that the program or erase cycle was not successfully completed. The device may output “1” on DQ5 if the system tries to program “1” to a location that was previously programmed to “0.” Only the erase operation can change “0” back to “1.” Under this condition, the device stops the operation, and while the timing limit has been exceeded, DQ5 produces “1.” 7. SPECIAL CHARACTERISTIC The W19B160B provides a good performance in the wireless products. It is concerned with access speed. If the access speed is quick to meet the demand of specification (70nS), the system’s application is widely and performance is better than other low speed products. - 16 - W19B160BT/B DATA SHEET 8. TABLE OF OPERATION MODES 8.1 Device Bus Operations MODE #CE #OE #WE #RESET ADDRESS (1) DQ8-DQ15 DQ0DQ7 BYTE =VIH BYTE =VIL DQ8DQ14=High-Z Read L L H H AIN DOUT DOUT Write L H L H AIN DIN DIN VDD ± 0.3V X X VDD ± 0.3V X High-Z High-Z High-Z Output Disable L H H H X High-Z High-Z High-Z Reset X X X L X High-Z High-Z High-Z Sector Protect (2) L H L VID SA, A6=L, A1=H, A0=L DIN X X Sector Unprotect (2) L H L VID SA, A6=H, A1=H, A0=L DIN X X Temporary Sector Unprotect X X X VID AIN DIN DIN High-Z Standby DQ15=A-1 Legend： L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5-11.5V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes： 1. Addresses are A19:A0 in word mode (#BYTE = VIH), A19:A-1 in byte mode (#BYTE = VIL). 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the” Sector Protection and Unprotect ion” section.Auto-select Codes (High Voltage Method) DESCRIPTION A19 #CE #OE #WE TO A12 A11 TO A10 A9 A8 TO A7 A6 A5 TO A2 A1 A0 DQ8 TO DQ7 TO DQ0 DQ15 X Manufacturer ID: 0 Winbond 0 1 X X VID X 0 X 0 0 Device ID: W19B160BT (Top Boot Block) 0 0 1 X X VID X 0 X 0 1 Device ID: W19B160BB (Bottom Boot Block) 0 0 1 X X VID X 0 X 0 1 Sector Protection Verification 0 0 1 SA X VID X 0 X 1 0 22h (Word ) 22h (Word ) X DAh C4h 49h 01h (protected) 00h (unprotected) Legend : SA= Sector Address, X= Don't Care , VID = 8.5-11.5V , L = Logic 0 = VIL , H = Logic 1 = VIH. - 17 - Publication Release Date Apr,20, 2009 Revision A9 W19B160BT/B DATA SHEET 8.2 Sector Address Table (Top Boot Block) SECTOR SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SECTOR ADDRESS A19-A12 00000XXX 00001XXX 00010XXX 00011XXX 00100XXX 00101XXX 00110XXX 00111XXX 01000XXX 01001XXX 01010XXX 01011XXX 01100XXX 01101XXX 01110XXX 01111XXX 10000XXX 10001XXX 10010XXX 10011XXX 10100XXX 10101XXX 10110XXX 10111XXX 11000XXX 11001XXX 11010XXX 11011XXX 11100XXX 11101XXX 11110XXX 111110XX 11111100 11111101 1111111X SECTOR SIZE (KBYTES/KWORDS) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 32/16 8/4 8/4 16/8 (X8) ADDRESS RANGE 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1F9FFFh 1FA000h-1FBFFFh 1FC000h-1FFFFFh (X16) ADDRESS RANGE 00000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-37FFFh 38000h-3FFFFh 40000h-47FFFh 48000h-4FFFFh 50000h-57FFFh 58000h-5FFFFh 60000h-67FFFh 68000h-6FFFFh 70000h-77FFFh 78000h-7FFFFh 80000h-87FFFh 88000h-8FFFFh 90000h-97FFFh 98000h-9FFFFh A0000h-A7FFFh A8000h-AFFFFh B0000h-B7FFFh B8000h-BFFFFh C0000h-C7FFFh C8000h-CFFFFh D0000h-D7FFFh D8000h-DFFFFh E0000h-E7FFFh E8000h-EFFFFh F0000h-F7FFFh F8000h-FBFFFh FC000h-FCFFFh FD000h-FDFFFh FE000h-FFFFFh Note : The address range is [A19: A-1] in byte mode (#BYTE =VIL) or [A19:A0] in word mode (#BYTE =VIH ). - 18 - W19B160BT/B DATA SHEET 8.3 Sector Address Table (Bottom Boot Block) SECTOR SECTOR ADDRESS SECTOR SIZE A19-A12 (KBYTES/KWORDS) SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 0000000X 00000010 00000011 000001XX 00001XXX 00010XXX 00011XXX 00100XXX 00101XXX 00110XXX 00111XXX 01000XXX 01001XXX 01010XXX 01011XXX 01100XXX 01101XXX 01110XXX 01111XXX 10000XXX 10001XXX 10010XXX 10011XXX 10100XXX 10101XXX 10110XXX 10111XXX 11000XXX 11001XXX 11010XXX 11011XXX 11100XXX 11101XXX 11110XXX 11111XXX 16/8 8/4 8/4 32/16 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (X8) ADDRESS RANGE 000000h-003FFFh 004000h-005FFFh 006000h-007FFFh 008000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh (X16) ADDRESS RANGE 00000h-01FFFh 02000h-02FFFh 03000h-03FFFh 04000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-37FFFh 38000h-3FFFFh 40000h-47FFFh 48000h-4FFFFh 50000h-57FFFh 58000h-5FFFFh 60000h-67FFFh 68000h-6FFFFh 70000h-77FFFh 78000h-7FFFFh 80000h-87FFFh 88000h-8FFFFh 90000h-97FFFh 98000h-9FFFFh A0000h-A7FFFh A8000h-AFFFFh B0000h-B7FFFh B8000h-BFFFFh C0000h-C7FFFh C8000h-CFFFFh D0000h-D7FFFh D8000h-DFFFFh E0000h-E7FFFh E8000h-EFFFFh F0000h-F7FFFh F8000h-FFFFFh Note: The address range is [A19:A-1] in byte mode (#BYTE =VIL) or [A19:A0] in word mode (#BYTE =VIH ). - 19 - Publication Release Date Apr,20, 2009 Revision A9 W19B160BT/B DATA SHEET 8.4 CFI Query Identification String ADDRESS DESCRIPTION (WORD MODE) Query-unique ASCII string "QRY" Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h=none exists) Address for Alternate OEM Extended Table (00h=none exists) 8.5 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah DATA 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h ADDRESS (BYTE MODE) 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h System Interface String ADDRESS DESCRIPTION (WORD MODE) VDD Min. (write/erase) DATA ADDRESS (BYTE MODE) 1Bh 0027h 36h 1Ch 0036h 38h VPP Min. voltage (00h=no Vpp pin present) 1Dh 0000h 3Ah VPP Max. voltage (00h=no Vpp pin present) 1Eh 0000h 3Ch Typical timeout per single byte/word write 2N S 1Fh 0004h 3Eh Typical timeout for Min. size buffer write 2N S (00h=not supported) 20h 0000h 40h Typical timeout per individual block erase 2N mS 21h 000Ah 42h Typical timeout for full chip erase 2 mS (00h=not supported) 22h 0000h 44h Max. timeout for byte/word write 2N times typical 23h 0005h 46h Max. timeout for buffer write 2N times typical 24h 0000h 48h Max. timeout per individual block erase 2 times typical 25h 0004h 4Ah Max. timeout full chip erase 2N times typical ( 00h = not supported) 26h 0000h 4Ch D7-D4: volt , D3-D0: 100 mV VDD Max. (write/erase) D7-D4: volt , D3-D0: 100 mV N N - 20 - W19B160BT/B DATA SHEET 8.6 Device Geometry Definition ADDRESS DESCRIPTION (WORD MODE) DATA ADDRESS (BYTE MODE) Device size =2 bytes 27h 0015h 4Eh Flash device interface description (refer to CFI publication 100) 28h 0002h 50h 29h 0000h 52h Max. number of bytes in multi-byte write=2N (00h=not supported) 2Ah 0000h 54h 2Bh 0000h 56h Number Of Erase Block Regions Within Devices 2Ch 0004h 58h 2Dh 0000h 5Ah Erase block region 1 information 2Eh 0000h 5Ch (refer to the CFI specification or CFI publication 100 ) 2Fh 0040h 5Eh 30h 0000h 60h 31h 0001h 62h 32h 0000h 64h 33h 0020h 66h 34h 0000h 68h 35h 0000h 6Ah 36h 0000h 6Ch 37h 0080h 6Eh 38h 0000h 70h 39h 001Eh 72h 3Ah 0000h 74h 3Bh 0000h 76h 3Ch 0001h 78h N Erase Block Region 2 Information Erase Block Region 3 Information Erase Block Region 4 Information - 21 - Publication Release Date Apr,20, 2009 Revision A9 W19B160BT/B DATA SHEET 8.7 Primary Vendor-Specific Extended Query ADDRESS DESCRIPTION (WORD MODE) DATA ADDRESS ( BYTE MODE) 40h 0050h 80h 41h 0052h 82h 42h 0049h 84h Major version number, ASCII 43h 0031h 86h Minor version number, ASCII 44h 0030h 88h 45h 0000h 8Ah 46h 0000h 8Ch 47h 0001h 8Eh 48h 0001h 90h 49h 0001h 92h 4Ah 0000h 94h 4Bh 0000h 96h 4Ch 0000h 98h Query-unique ASCII string "PRI" Address sensitive unlock 0 = Required, 1 = Not required Erase Suspend 00 = Not supported, 01=Supported Sector protect 0 = Not supported, X=number of sectors in per group Sector Temporary Unprotect 00 = Not supported, 01=Supported Sector protect/unprotect scheme 00 = Not supported, 01=Supported Simultaneous operation 00 = Not supported, 01=Supported Burst mode type 00 = Not supported, 01=Supported Page mode type 00 = Not Supported, 01=4 Word Page, 02=8 Word Page - 22 - W19B160BT/B DATA SHEET 8.8 Command Definitions BUS CYCLES (2-5) COMMAND SEQUENCE CYCLE (1) FIRST 1 RA RD Reset (note 7) 1 XXX F0 Chip Erase Sector Erase Unlock pass Word Byte Word Byte Word Byte Word Byte 4 6 6 3 555 AAA 555 AAA 555 AAA 555 AAA AA AA AA AA 2AA 555 2AA 555 2AA 555 2AA 555 55 55 55 55 2 XXX A0 PA PD Unlock bypass reset 2 XXX 90 XXX 00 AUTOSELECT(note8) Unlock bypass program Manufacturer Word Code Byte Device Code Sector Protect Verify (note 9) Common Flash Interface (CFI) Query (note 10) THIRD FOURTH FIFTH SIXTH ADDR DATA ADDR DATA ADDR DATA ADDR DATA ADDR DATA ADDR DATA Read (note 6) Normal Program SECOND Word Byte 4 4 555 AAA 555 AAA Word Byte Byte AA 555 4 Word AA 2AA 555 2AA 555 AAA 55 AA 55 2AA AA 1 55 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 80 80 PA 555 AAA 555 AAA PD AA AA 2AA 555 2AA 555 55 55 555 AAA SA 10 30 20 90 90 555 55 555 A0 X00 DA X01 (note11 ) x02 (SA) X02 90 AAA (SA) X04 XX00 XX01 00 01 98 Legend: X = Don’t Care RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the #WE or #CE pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of #WE or #CE pulse, whichever happens first. RD = Data read from location RA during read operation. SA = Address of the sector to be verified (in auto select mode) or erased. Address bits A19-A12 uniquely select any sector. Notes: 1. See Bus Operations Table for details. 2. All values are in hexadecimal. 3. Except for the read cycle and the fourth cycle of the auto select command sequence, all bus cycles are write cycles. 4. Data bits DQ15-DQ8 are don’t care for unlock and command cycle. 5. Unless otherwise noted, address bits A19-A11 are don’t cares for unlock and command cycles. 6. No unlock or command cycles required when reading array data. 7. When device is in the auto select mode, the reset command is required to return to reading array data, or if DQ5 goes high (while the device is providing status data). 8. The fourth cycle of the auto select command sequence is a read cycle. - 23 - Publication Release Date Apr,20, 2009 Revision A9 W19B160BT/B DATA SHEET 9. The data is 00h for an unprotected sector and 01h for a protected sector. 10. Command is valid when device is ready to read array data or when device is in auto select mode. 11. See Auto-select Codes table for device ID information. 8.9 Write Operation Status STATUS Standard Embedded Program Algorithm Mode Embedded Erase Algorithm DQ7 (NOTE 2) DQ6 DQ5 (NOTE1) DQ3 DQ2 RY/#BY (NOTE 2) #DQ7 Toggle 0 N/A No toggle 0 0 Toggle 0 1 Toggle 0 Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 requires a valid address when reading status information. Please refer to related sections for details. - 24 - W19B160BT/B DATA SHEET 8.10 Temporary Sector Unprotect Algorithm START #RESET = VID (Note 1) Perform Erase or Program Operations #RESET = VIH Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors unprotected. 2. All previously protected sectors are protected once again - 25 - Publication Release Date Apr,20, 2009 Revision A9 W19B160BT/B DATA SHEET 8.11 In-System Sector Protect/Unprotect Algorithms START START PLSCNT=1 #RESET=V ID Wait 1 μ s No Temporary Sector Unprotect Mode Protect all sectors The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address PLSCNT=1 #RESET=V Wait 1 μ s First Write Cycle=60h? First Write Cycle=60h? Yes Yes Set up first sector address Wait 150 μ s Sector Unrotect: Write 60h to sector address with A6=1,A1=1,A0=0 Reset PLSCNT=1 Wait 15 mS Increment PLSCNT A1=1,A0=0 Verity Sector Unprotect: Write 40h to sector address with A6=1, Read from sector address with A6=0, A1=1,A0=0 No A1=1,A0=0 Read from sector address with A6=1, A1=1,A0=0 No PLSCNT =25? Yes Device failed Data=01h? Yes Protect another sector? No PLSCNT =1000? Yes Remove V ID from #RESET Data=00h? Yes No Device failed Write reset command Sector Protect complete No Set up next sector address Yes No Sector Protect Algorithm Temporary Sector Unprotect Mode All sector protected? No Sector Protect: Write 60h to sector address with A6=0,A1=1,A0=0 Verity Sector Protect:Write 40h to sector address with A6=0, No Yes Set up sector address Increment PLSCNT ID Sector Unprotect Algorithm Last sector verified? Yes Remove V ID from #RESET Write reset command Sector Unprotectt complete - 26 - W19B160BT/B DATA SHEET 8.12 Program Algorithm START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Yes No Increment Address Last Address? Yes Programming Completed 8.13 Erase Algorithm (Polling) S TA R T W rite E ras e Com m an d S equ enc e Data P oll from S y s tem E m bed ded E ras e algorith m in prog res s No Data= FFh ? Y es E ras e Co m plete d - 27 - Publication Release Date Apr,20, 2009 Revision A9 W19B160BT/B DATA SHEET 8.14 Erase Algorithm (Toggle) START Erase Command 100us Delay Embedded erase algorithm in progress Yes DQ6 toggle? No STOP - 28 - W19B160BT/B DATA SHEET 8.15 Data Polling Algorithm START Read DQ7-DQ0 Addr=VA Yes DQ7=Data? No No DQ5=1? Yes Read DQ7-DQ0 Addr=VA DQ7=Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation; a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. - 29 - Publication Release Date Apr,20, 2009 Revision A9 W19B160BT/B DATA SHEET 8.16 Toggle Bit Algorithm START Read DQ7-DQ0 Read DQ7-DQ0 (Note 1) Toggle Bit =Toggle? No Yes No DQ5=1? Yes Read DQ7-DQ0 Twice Toggle Bit =Toggle? (Notes 1, 2) No Yes Program/Erase Operation Not Complete,Write Reset Command Program/Erase Complete Notes: 1. Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to “1.” - 30 - W19B160BT/B DATA SHEET 9. ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Ratings PARAMETER RATING UNIT Storage Temperature Plastic Packages -65 to +150 °C Ambient Temperature with Power Applied -65 to +125 °C Voltage with Respect to Ground , VDD (Note1) -0.5 to +4.0 V A9, #OE, and #RESET (Note 2) -0.5 to VDD (Max.) V All other pins (Note 1) -0.5 to VDD +0.5 V 200 mA Output Short Circuit Current (Note 3) Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to 2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VDD +0.5 V. During voltage transitions, input or I/O pins may overshoot to VDD +2.0 V for periods up to 20 ns. 2. Minimum DC input voltage on pins A9, #OE, and #RESET is -0.5 V. During voltage transitions, A9, #OE, and #RESET may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on pin A9 is VDD (Max.) which may overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage is +9.5 V which may overshoot to +12.0 V for periods up to 20 nS. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 9.2 Operating Ranges PARAMETER Industrial (I) Devices Ambient Temperature (TA ) Commercial Devices Ambient Temperature (TA ) VDD Supply Voltages VDD for standard voltage range RATING UNIT -40 to +85 °C 0 to +70 °C 2.7 to 3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. - 31 - Publication Release Date Apr,20, 2009 Revision A9 W19B160BT/B DATA SHEET 9.3 DC CHARACTERISTICS PARAMETER SYM. LIMITS TEST CONDITIONS MIN. TYP. MAX. UNIT Input Load Current ILI VIN = VSS to VDD, VDD = VDD (Max.) - ± 1.0 μA A9 Input Load Current ILIT VDD = VDD (Max.), A9 = VID (Max.) - 35 μA Output Leakage Current ILO VOUT = VSS to VDD , VDD = VDD (Max.) - ± 1.0 μA 15 25 mA 9 16 mA 1 MHz 2 4 mA 10 MHz 18 25 mA 5 MHz 9 16 mA 1 MHz 2 4 mA #CE = VIL , #OE = VIH VDD Active Read Current (Note 1,2) Byte Mode ICC1 #CE = VIL , #OE = VIH Word Mode VDD Active Current (Note 2,3,4) VDD Standby Current (Note 2,5) VDD Reset Current (Note 2,5) 10 MHz 5 MHz - ICC2 #CE = VIL , #OE = VIH - 20 30 mA ICC3 #RESET , #CE = VDD ± 0.3V - 0.2 5 μA ICC4 #RESET = VSS ± 0.3V - 0.2 5 μA VIH = VDD ± 0.3V, VIL = VSS ± 0.3V 0.2 5 μA - 0.8 V Automatic Sleep Mode Current ICC5 (Note 2,4,5,6) Input Low Voltage VIL -0.5 Input High Voltage VIH 0.7 x VDD - VDD+0.3 V Voltage for Auto-select and VID Temporary Sector Unprotected VDD =3.0V ± 10% 8.5 - 11.5 V Output Low Voltage IOL = 4.0 mA, VDD = VDD (Min.) - - 0.45 V VOH1 IOL = -2.0 mA, VDD = VDD (Min.) 2.4 - - V VOH2 IOH = -100 μA, VDD = VDD (Min.) VDD -0.4 - - V Output High Voltage VOL Notes: 1. 2. 3. 4. The ICC current is typically less than 2 mA/MHz, with #OE at VIH. Typical VDD is 3.0V. Maximum ICC specifications are tested with VDD = VDD max. ICC active while Embedded Erase or Embedded Program is in progress. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. For temperature >70 degree C, Vih(Max.)=Vdd+0.1V and Vil(Min)=Vss-0.1V. 6. Not 100% tested - 32 - W19B160BT/B DATA SHEET 9.4 9.4.1 AC CHARACTERISTICS Test Condition Test Condition 70nS Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 9.4.2 30 90nS Unit 1 TTL gate 100 5 0 - 3.0 1.5 1.5 pF ns V V V AC Test Load and Waveforms V=3.3V Vcc R2= 1.6K ohm C= 0.1uF DUT CL= 30pF D=IN3064 OR EQUIVALENT R1= 6.2K ohm Note: 1. CL=30pF/70nS, CL=100pF/90nS 2. Tr/Tf=5nS 3. In/out reference levels=1.5V 4. Output load: 1 TTL gate - 33 - Publication Release Date Apr,20, 2009 Revision A9 W19B160BT/B DATA SHEET 9.4.3 Read-Only Operations PARAMETER Read Cycle Time SYM. TEST Setup TRC Address to Output Delay TACC #CE = VIL, #OE = VIL #OE = VIL 70nS 90nS Min. Max. Min. Max. Unit 70 - 90 - ns - 70 - 90 ns - 70 - 90 ns Chip Enable to Output Delay TCE Output Enable Access Time TOE - 30 - 35 ns Chip Enable to Output High Z TDF - 25 - 30 ns Output Enable to Output High Z TDF - 25 - 30 ns Output Hold Time From Address. #OE or TOH #CE Whichever Occurs First 0 - 0 - ns 0 - 0 - ns 10 - 10 - ns Output Enable Hold Time Read Toggle and #Data TOEH polling Note : Not 100 % tested 9.4.4 Read-Only Operations Test Condition 70nS Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels Note : Not 100 % tested - 34 - 90nS Unit 1 TTL gate 30 100 5 0 - 3.0 1.5 1.5 pF ns V V V W19B160BT/B DATA SHEET 9.4.5 Hardware Reset (#RESET) PARAMETER SYM. MIN. MAX. UNIT #RESET PIN Low (During Embedded Algorithms) to Read or Write TREADY - 20 us #RESET Pin Low (Not During Embedded Algorithms) to Read or Write TREADY - 500 ns #RESET Pulse Width TRp 500 - ns #RESET High Time Before Read TRH 50 - ns #RESET Low to Standby Mode TRPD 20 - us RY/#BY Recovery Time TRB 0 - ns 70nS 90nS Unit 1 TTL gate 30 100 5 0 - 3.0 1.5 1.5 pF ns V V V Note: Not 100 % tested 9.4.6 Word/Byte Configuration (#BYTE) Test Condition Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels - 35 - Publication Release Date Apr,20, 2009 Revision A9 W19B160BT/B DATA SHEET 9.4.7 Erase and Program Operation PARAMETER SYM. Write Cycle Timing TWC TAS TAH TDS TDH TOES Address setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time Before Write (#OE High to #WE Low) #CE Setup Time TGHWL #CE HOLD Time Write Pulse Width Write Pulse Width High Byte Programming Time Word Sector Erase Time VDD Setup Time (Note 1) Write Recovery Time from RY/#BY Program/Erase Valid to RY/#BY Delay TCS TCH TWP TWPH TPB TPW TSE TVCS TRB TBUSY Min. 70 70nS Typ. - Max. - Min. 90 90nS Typ. - Max. - 0 - 45 - - 0 - - ns - 45 - - ns Unit ns 35 - - 45 - - ns 0 - - 0 - - ns 0 - - 0 - - ns 0 - - 0 - - ns 0 - - 0 - - ns 0 - - 0 - - ns 35 - - 35 - - ns 30 - - 30 - - ns - 5 150 - 5 150 us - 7 210 - 7 210 us - 0.7 10 - 0.7 10 sec 50 - - 50 - - us 0 - - 0 - - ns 30 - 90 - - 90 ns Notes: Not 100 % tested 9.4.8 Temporary Sector Unprotect PARAMETER SYM. MIN. MAX. UNIT VID Rise and Fall Time (See Note) TVIDR 500 - ns #RESET setup Time for Temporary Sector Unprotect TRSP 4 - us #RESET Hold Time from RY/#BY High for Temporary Sector Unprotect TRRB 4 - s Note: Not 100 % tested - 36 - W19B160BT/B DATA SHEET 9.4.9 Alternate #CE Controlled Erase and Program Operation 70nS PARAMETER Write Cycle Time (Note 1) Address Setup Time Address Hold Time Typ (Note 3) Max (Note 4) Min Typ (Note 3) Max (Note 4) Unit TWC TAS TAH TDS TDH TOES 70 - - 90 - - ns 0 - - 0 - - ns 45 - - 45 - - ns - - 45 - - ns 0 - - 0 - - ns 0 - - 0 - - ns TGHEL 0 - - 0 - - ns 0 - - 0 - - ns 0 - - 0 - - ns 35 - - 35 - - ns 30 - - 30 - - ns Byte TWS TWH TCP TCPH TPB - 5 - - 5 - Word TPW - 7 - - 7 - - 0.7 - - 0.7 - sec - 25 - - 25 - sec Byte TSE TCE TCPB - 11 - - 11 - Word TCPW - 7.2 - - 7.2 - Data Hold Time Output Enable Setup Time Read Recover Time Before Write (#OE High to #WE Low) #WE Setup Time #WE Hold Time #CE Pulse Width #CE Pulse Width High Sector Erase Time (Note 2) Chip Erase Time (Note 2) Chip Program Time (Note 5) Min 35 Data Setup Time Programming Time (Note 6) 90nS SYM. us sec Notes : 1. Not 100 % tested. 2. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 3. Typical program and erase time assume the following conditions :25℃,3.0 V VDD, 10,000 cycles .Additionally, programming typicals assume checkerboard pattern. 4. Under worst case conditions of 90℃, VDD =2.7V, 10,000 cycles. 5. The typical chip programming time is considerably less than the maximun chip programming time listed,since most bytes program faster than maximun program times listed. 6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. 7. The device has a minimum erase and program cycle endurance of 10,000 cycles. - 37 - Publication Release Date Apr,20, 2009 Revision A9 W19B160BT/B DATA SHEET 10. TIMING WAVEFORMS 10.1 AC Read Waveform TRC Addresses Stable Address TA CC #CE TO E #OE TDF TOEH #WE T CE TOH High-Z Outp uts Outp ut Vaild #RESET RY/#B Y 0V 10.2 Reset Waveform RY/#BY #OE,#CE TRH #RESET TRP TReady Reset Timing NOT during Embedded Algorithms TReady RY/#B Y TRB #OE,#CE #RESET TRP Reset Timings during Embedded Algorithms - 38 - High-Z W19B160BT/B DATA SHEET 10.3 #BYTE Waveform for Read Operation #CE #OE #BYTE #BYTE Switching from word TELFL Data Output (DQ0-DQ14) DQ0-DQ14 to byte mode Data Output (DQ0-DQ7) DQ15 Output DQ15/A-1 TELFH Address Input TFLQZ #BYTE #BYTE Switching DQ0-DQ14 Data Output (DQ0-DQ7) Data Output (DQ0-DQ14) from byte to word mode DQ15/A-1 Address Input DQ15 Output TFHQV 10.4 #BYTE Waveform for Write Operation #CE The falling edge of the last #WE signal #WE #BYTE T SET (TAS ) THOLD (TAH ) Note: Refer to the Erase /Program Operations table for TAS and TAH Specifications. - 39 - Publication Release Date Apr,20, 2009 Revision A9 W19B160BT/B DATA SHEET 10.5 Programming Waveform Program Command Sequence (last two cycles) TWC Address Read Status Data (last two cycles) TAS 555h PA PA PA TAH #CE TCH #OE TWP #WE TPW TWPH TDH TCS T DS A0h Data Status PD DOUT TBUSY TRB RY/#BY VDD TVCS Notes : 1. PA=program address ,PD=program data,DOUT is the true data at the program address 2. Illustration shows device in word mode 10.6 Chip/Sector Erase Waveform Erase Command Sequence (last two cycles) TWC TAS 2AAh Address Read Status Data VA SA VA 555h for chip erase TAH #CE TCH #OE TWP #WE TCS Data TWPH TDS 55h TSE TDH RY/#BY VDD In Progress 30h 10 for Chip Erase TBUSY Complete TRB TVCS Notes : 1. SA= sector address (for Sector Erase), VA= Valid Address for reading status data (see “Write operation Status”). 2. These waveforms are for the word mode - 40 - W19B160BT/B DATA SHEET 10.7 #Data Polling Waveform (During Embedded Algorithms) TRC Addresses VA VA VA TACC TCE #CE TCH TOE #OE TDF T OEH #WE TOH High Z DQ7 Complement Complement True Valid Data DQ0-DQ6 Status Data Status Data True Valid Data TBUSY High Z RY/#BY Note : VA= Valid Address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. 10.8 Toggle Bit Waveform (During Embedded Algorithms) T RC VA VA Addresses VA VA TACC #CE TCH TCE TOE #OE TOEH TDF #WE TOH High Z DQ6 Valid Status Valid Status Valid Status (first read) (second read) (stop toggling) Valid Status RY/#BY T BUSY Note : VA= Valid address;not requires for DQ6. Illustration shows status cycle after command sequence, last status read cycle, and array data read cycle. - 41 - Publication Release Date Apr,20, 2009 Revision A9 W19B160BT/B DATA SHEET 10.9 Temporary Sector Unprotect Timing Diagram 12V #RESET 0 or 3V TVIDR TVIDR Program or Erase Command Sequence #CE #WE TRSP RY/#BY 10.10 Sector Protect and Unprotect Timing Diagram VID #RESET VIH SA,A6, A1,A0 Valid* Valid* 60h DATA 40h 60h Sector Protect:150μs, Sector Unprotect:15ms #CE Valid* Verify Sector Protect or Unprotect 1μs #WE #OE Note: For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0. - 42 - Status W19B160BT/B DATA SHEET 10.11 Alternate #CE Controlled Write (Erase/Program) Operation Timing #Data Polling Address PA for program 555 for program 2AA for erase 555 for chip erase TWC TWH TGHEL #WE TAS #OE PA SA for sector erase TAH TCP TWS #CE . DATA TRH TCPH TDS TDH A0 for program 55 for erase TPW, TPB, OR T SE TBUSY . #DQ7 D OUT PD for program 30 for sector erase 10 for chip erase #RESET RY/#BY Notes : 1. Firgure indicates last two bus cycles of a program or erase operation. 2. PA= program address, SA= sector address, PD= program data. 3. #DQ7 is the complement of the data written to the device. DOUT is the data written to the device. 4. Waveforms are for the word mode. - 43 - Publication Release Date Apr,20, 2009 Revision A9 W19B160BT/B DATA SHEET 11. LATCHUP CHARACTERISTICS PARAMETER MIN MAX Input voltage with respect to Vss on all pins except I/O pins (including A9, #OE, and #RESET) -1.0 V 11.5 V Input voltage with respect to Vss on all I/O pins -1.0 V VDD +1.0 V -100 mA +100 mA VDD Current Note : Includes all pins except VDD. Test conditions: VDD = 3.0 V, one pin at a time. 12. CAPACITANCE SYM. TEST SETUP TYP MAX UNIT VIN VIN = 0 6 7.5 pF Output Capacitance VOUT VOUT = 0 8.5 12 pF Control Pin Capacitance VIN2 VIN = 0 7.5 9 pF PARAMETER Input Capacitance Notes : 1. 2. Sampled, not 100 % tested. Test condition TA = 25℃, f = 1.0 MHz. - 44 - W19B160BT/B DATA SHEET 13. ORDERING INFORMATION Quality: Grade & Green H: Extended (-20℃ ~85 ℃ )with Green package M:Industrial (-40℃ ~85 ℃ )with Green package SPEEDOPTION 7 : 70 ~ 79ns 9 : 90 ~ 99ns PACKAGE TYPE T = 48 - Pin TSOP Package, 12 x 20mm BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION W19B160B 16 Megabit (2M x-8Bit/ 1 M x 16- Bit) CMOS Flash Memory - 45 - Publication Release Date Apr,20, 2009 Revision A9 W19B160BT/B DATA SHEET PACKAGE DIMENSIONS 48-Pin Standard Thin Small Outline Package (measured in millimeters) 1 48 e E b c D HD A2 θ A L A1 L1 Symbol A A1 A2 D HD E b c e L L1 Y θ MILLIMETER MIN. NOM. MAX. 1.20 0.05 0.95 1.00 1.05 18.5 18.4 18.3 19.8 20.0 20.2 11.9 12.1 12.0 0.17 0.10 0.22 0.27 0.21 MIN. 0.002 0.037 0.720 0.780 0.468 0.007 0.004 0.60 0.80 0.70 0.020 0.041 0.728 0.795 0.476 0.011 0.008 0.024 0.031 0.028 0.004 0.10 0 0.039 0.724 0.787 0.472 0.009 MAX. 0.047 0.020 0.50 0.50 INCH NOM. 0 5 - 46 - 5 Y W19B160BT/B DATA SHEET 14. VERSION HISTORY VERSION DATE PAGE DESCRIPTION A1 April/12/2007 ALL Initial Issued A2 July/17/2007 ALL 48-Pin Standard Thin Small Outline Package/VID Spec to 11.5volt 1. Reduced TBUSY form 90nS to 30nS A3 Oct./01/2007 2. Reduced ICC1 form 30/35mA to 25mA 34-38 3. Removed max of TCPB/ TCPW 4. A4 Oct./17/2007 A5 Dec./20/2007 A6 26,46 Removed max of TPW Updated frame setting and package material as Green 32,36-41 1. Added note of ICC3-5, 90nS/Read only spec, and max. of tPW/Tpb 39 2. Modify AC test load July/21/2008 45 Updated frame setting A7 Nov./04/2008 4,45 A8 Dec./30/2008 A9 Apr./20/2009 Removed TFBGA package type Removed Erase Suspend/Resume feature 29 Add erase algorithm (Toggle) 24 Unlock bypass reset: 2nd command F0 → 00 Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 47 - Publication Release Date Apr,20, 2009 Revision A9