WINBOND W81281

W81281
USB Keyboard/
Device Controller
W81281
W81281 Data Sheet Revision History
Pages
Dates
Version
Version
Main Contents
on Web
1
2
All
09/01/1997
0.50
First published.
12/16/1997
0.51
Update Features
7/12/1999
0.6
Update registers description
3
4
5
6
7
8
9
10
11
Please note that all data and specifications are subject to change without notice. All
the trade marks of products and companies mentioned in this data sheet belong to
their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or
systems where malfunction of these products can reasonably be expected to result
in personal injury. Winbond customers using or selling these products for use in
such applications do so at their own risk and agree to fully indemnify Winbond for
any damages resulting from such improper use or sales.
-I-
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
TABLE OF CONTENT
1.
GENERAL DESCRIPTION ................................................................................................................1
2.
FEATURES .........................................................................................................................................2
3
BLOCK DIAGRAM .............................................................................................................................3
4.
PIN CONFIGURATION ......................................................................................................................4
5.
PIN DESCRIPTION ............................................................................................................................6
5.1
5.2
5.3
40 PIN DIP...........................................................................................................................................6
28-PIN SOP .........................................................................................................................................8
48-PIN LQFP......................................................................................................................................9
6 FUNCTIONAL DESCRIPTION ...............................................................................................................11
6.1
FIRST IN FIRST OUT STORAGE (FIFO'S) ORGANIZATION ....................................................................11
6.1.1
INTERFACE TO THE MICROCONTROLLER:.......................................................................11
6.2
REGISTER DESCRITPION ......................................................................................................................12
6.2.1
Status Registers ........................................................................................................................12
6.2.2
Control Registers .......................................................................................................................13
6.3
RESET .................................................................................................................................................15
6.3.1
External Reset (Hardware Reset) ............................................................................................16
6.3.2
Warm Reset (Software Reset) .................................................................................................16
6.4
USB SUSPEND.................................................................................................................................16
6.5
USB RESUME:..................................................................................................................................16
7.
PROGRAMMING NOTES: ..............................................................................................................17
7.1
7.2
7.3
7.4
7.5
CONTROL REGISTERS ACCESS:...........................................................................................................17
STATUS REGISTERS ACCESS:..............................................................................................................17
FIFOS ACCESS : .................................................................................................................................17
SET STALL FOR ENDPOINT 0 - 4 : ........................................................................................................17
SET NULL DATA FOR IN TRANSACTION OF EP 0 :................................................................................18
8.
ELECTRICAL CHARACTERISTICS & CAPACITANCE..............................................................19
9.
USB KEYBOARD SAMPLE APPLICATION .................................................................................22
10.
PACKAGE DIMENSIONS................................................................................................................24
APPENDIX A: WINBOND( W81281-004) DEFAULT MATRIX CODE .................................................28
II
Publication Release Date: July 1999
Revision 0.60
W81281
USB Keyboard/ Device Controller
1.
GENERAL DESCRIPTION
W81281 is a low cost, high integration single-chip microcontroller with Universal Serial Bus (USB) interface
for keyboard application, it includes the core of Winbond 8-bit microprocessor W78C52 which works on
6MHz. It implements a standard PC keyboard and enables connection to host system through low-speed
(1.5Mhz) USB connection . It complies with USB Specification Revision 1.0 and HID Class Definition
Revision 1.0.
For Keyboard application, W81281 supports an 18 X 8 keyboard scan matrix, which allows suspend wake
up, and also provides a port for PS/2 mouse. It consists of an 8051 compatible CPU core, a 6K-byte ROM,
a 256-byte SRAM, and three 16-bit programmable timers.
W81281 supports one device address and five endpoints, one bi-directional endpoint for Control transfer
and four unidirectional endpoints for Interrupt IN transfer. Through modification of firmware of W78C52, it
can be used for multifunction device design, such as USB-IR receiver and any Slow-Speed (1.5Mhz) USB
peripheral device controller.
-1-
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
2.
FEATURES
Fully compliant with USB spec. Rev.1.0 and HID Class Rev. 1.0
Supporting one device address and five endpoints (one Control transfer, four Interrupt transfer)
Implementing USB keyboard with PS/2 mouse connection
Microsoft Intellimouse(3D mouse) Supported
Supporting 8-bit sense (row) input with wake up interrupt on falling edge, internal pull-ups
Supporting 18-bit drive (column) output, open drain with pull-ups
8-bit 8051 compatible CPU core
6K-byte ROM
256-byte SRAM
3 direct drive LED outputs with internal series resisters
Supporting warm reset
Built-in low voltage reset and EFT/ESD protection circuit
Built-in Watch-Dog Timer for device recovery
Support Win98 system control function
Support suspend/wake-up function, suspend current under 500µA
Internal 3.3V regulator supported
40-pin DIP, 28-pin SOP and 48-pin LQFP packages
5V CMOS Device
2
Publication Release Date: July 1999
Revision 0.60
Preliminary
3
Winbond USB Keyboard/HID Controller
Winbond USB Keyboard/HID Controller
(W81281)
LED0-2(P33-P35)
(x3)
RST IDSEL(P30)
P02SO*
INT
USB
Transceiver
USB SIE
.
.
.
8052
Micro
Processor
(x18)
P1SI*
XFRI
Endpoints
Clock
Generator
(x8)
EFT, LVRST
*P02SO: P00-P07,P20-P27,SCO16,SCO17
X1
Power Down
Control
Watch Dog
Timer
X2
5V to 3.3V
Conversion
DD+
VSS
VBUS
VDD
*P1SI:P10-P17
PSCL PSDA
(P32) (P31) External Clock Circuit
Publication Release Date:
1999
60
W81281
Preliminary
4.
PIN CONFIGURATION
VSS
D+
DVDD3
SI0/P10
SI1/P11
SI2/P12
SI3/P13
SO04/P04
SO05/P05
SO06/P06
SO07/P07
IDSEL/P30
LED0/P33
PSCLK/P32
PSDA/P31
LED1/P34
LED2/P35
RESET
X2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
SO17
SO16
SO00/P00
SO01/P01
SO02/P02
SO03/P03
SI4/P14
SI5/P15
SI6/P16
SI7/P17
SO015/P27
SO014/P26
SO013/P25
SO012/P24
SO011/P23
SO010/P22
SO09/P21
SO08/P20
VDD
X1
40-PIN DIP
VSS
VSS
D+
DVDD3
AD04
AD05
AD06
AD07
XALE
XWR
XRD
RESET
X2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AD00
AD01
AD02
AD03
WK0
WK1
WK2
WK3
NC
NC
XMODE
XINT
VDD
X1
28-PIN SOP
4
Publication Release Date: July 1999
Revision 0.60
W81281
36
SO01/P02
SO10/P22
SO11/P23
SO12/P24
SO13/P25
SO15/P27
SO14/P26
SI6/P16
SI7/P17
SI5/P15
SO03/P03
SI4/P14
SO02/P02
Preliminary
25
24
37
NC
SO09/P21
SO08/P20
SO00/P00
SO16
VDD
X1
SO17
EESCL
VID1
X2
W81281D
VID0
RESET
EESDA
LED2/P35
VSS
VSS
LED1/P34
PSDA/P31
D+
48
13
PSCLK/P32
LED0/P33
NC
IDSEL/P30
SO07/P07
SO06/P06
SO04/P04
SO05/P05
NC
SI2/P12
SI3/P13
12
SI1/P11
VDD3
1
SI0/P10
D-
48-pin LQFP
5
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
5.
PIN DESCRIPTION
5.1
40 PIN DIP
PIN NO.
NAME
TYPE
POWER
DESCRIPTION
1
VSS
2
D+
Ground
3
D-
4
VDD3
5
SI0/P10
I/O
Keyboard scan Input 0 / Internal µC IO port 1.0
6
SI1/P11
I/O
Keyboard scan Input 1 / Internal µC IO port 1.1
7
SI2/P12
I/O
Keyboard scan Input 2 / Internal µC IO port 1.2
8
SI3/P13
I/O
Keyboard scan Input 3 / Internal µC IO port 1.3
9
SO04/P04
I/O
Keyboard scan Output 04 / Internal µC IO port 0.4
10
SO05/P05
I/O
Keyboard scan Output 05 / Internal µC IO port 0.5
11
SO06/P06
I/O
Keyboard scan Output 06 / Internal µC IO port 0.6
12
SO07/P07
I/O
Keyboard scan Output 07 / Internal µC IO port 0.7
13
IDSEL/P30
I/O
Vendor ID selection / Internal µC IO port 3.0
14
LED0/P33
I/O
Num. Lock LED / Internal µC IO port 3.3
15
PSCLK/P32
I/O
PS/2 mouse clock pin / Internal µC IO port 3.2
16
PSDA/P31
I/O
PS/2 mouse data pin / Internal µC IO port 3.1
17
LED1/P34
I/O
Caps Lock LED / Internal µC IO port 3.4
18
LED2/P35
I/O
19
RESET
I/O
USB signal (+)
I/O
USB signal (-)
POWER
INPUT
DC power 3.3V output
Scroll Lock LED / Internal µC IO port 3.5
Chip reset pin
20
X2
OUTPUT
21
X1
INPUT
Clock input
Clock output
22
VDD
POWER
VDD power
23
SO08/P20
I/O
Keyboard scan Output 08 / Internal µC IO port 2.0
24
SO09/P21
I/O
Keyboard scan Output 09 / Internal µC IO port 2.1
25
SO10/P22
I/O
Keyboard scan Output 10 / Internal µC IO port 2.2
26
SO11/P23
I/O
Keyboard scan Output 11 / Internal µC IO port 2.3
27
SO12/P24
I/O
Keyboard scan Output 12 / Internal µC IO port 2.4
28
SO13/P25
I/O
Keyboard scan Output 13 / Internal µC IO port 2.5
6
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
5.1 40-PIN DIP, continued
PIN NO.
NAME
TYPE
DESCRIPTION
I/O
Keyboard scan Output 14 / Internal µC IO port 2.6
29
SO14/P26
30
SO15/P27
I/O
Keyboard scan Output 15 / Internal µC IO port 2.7
31
SI7/P17
I/O
Keyboard scan Input 7 / Internal µC IO port 1.7
32
SI6/P16
I/O
Keyboard scan Input 6 / Internal µC IO port 1.6
33
SI5/P15
I/O
Keyboard scan Input 5 / Internal µC IO port 1.5
34
SI4/P14
I/O
Keyboard scan Input 4 / Internal µC IO port 1.4
35
SO03/P03
I/O
Keyboard scan Output 03 / Internal µC IO port 0.3
36
SO02/P02
I/O
Keyboard scan Output 02 / Internal µC IO port 0.2
37
SO01/P01
I/O
Keyboard scan Output 01 / Internal µC IO port 0.1
38
SO00/P00
I/O
Keyboard scan Output 00 / Internal µC IO port 0.0
39
SO16
OUTPUT
Keyboard scan Output 16
40
SO17
OUTPUT
Keyboard scan Output 17
7
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
5.2
28-PIN SOP
PIN NO.
NAME
TYPE
DESCRIPTION
1
VSS
POWER
Ground
2
VSS
POWER
Ground
3
D+
I/O
USB signal (+)
4
D-
I/O
USB signal (-)
5
VDD3
POWER
6
AD04
I/O
µC Interface AD04 (Address/Data 04)
7
AD05
I/O
µC Interface AD05 (Address/Data 05)
8
AD06
I/O
µC Interface AD06 (Address/Data 06)
9
AD07
I/O
µC Interface AD07 (Address/Data 07)
10
XALE
I/O
µC Interface ALE (Address Latch Enable)
11
XWR
I/O
µC Interface WR (Data Write)
12
XRD
I/O
µC Interface RD (Data Read)
13
RESET
14
DC power 3.3V output
INPUT
Chip reset pin
X2
OUTPUT
Clock output
15
X1
INPUT
Clock input
16
VDD
POWER
VDD power
17
XINT
I/O
µC Interface INT (Interrupt)
18
XMODE
I/O
Controller mode setting, it should be kept high
19
NC
I/O
Not Used
20
NC
I/O
Not Used
21
WK3
INPUT
Wakeup pin, Active low and keep more than 100ns
22
WK2
INPUT
Wakeup pin, Active low and keep more than 100ns
23
WK1
INPUT
Wakeup pin, Active low and keep more than 100ns
24
WK0
INPUT
Wakeup pin, Active low and keep more than 100ns
25
AD03
I/O
µC Interface AD03 (Address/Data 03)
26
AD02
I/O
µC Interface AD02 (Address/Data 02)
27
AD01
I/O
µC Interface AD01 (Address/Data 01)
28
AD00
I/O
µC Interface AD00 (Address/Data 00)
8
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
5.3
48-PIN LQFP
PIN NO.
NAME
TYPE
POWER
DESCRIPTION
1
VDD3
2
SI0/P10
I/O
Keyboard scan Input 0 / Internal µC IO port 1.0
3
SI1/P11
I/O
Keyboard scan Input 1 / Internal µC IO port 1.1
4
SI2/P12
I/O
Keyboard scan Input 2 / Internal µC IO port 1.2
5
SI3/P13
I/O
Keyboard scan Input 3 / Internal µC IO port 1.3
none
DC power 3.3V output
6
NC
7
SO04/P04
I/O
Not Used
Keyboard scan Output 04 / Internal µC IO port 0.4
8
SO05/P05
I/O
Keyboard scan Output 05 / Internal µC IO port 0.5
9
SO06/P06
I/O
Keyboard scan Output 06 / Internal µC IO port 0.6
10
SO07/P07
I/O
Keyboard scan Output 07 / Internal µC IO port 0.7
11
IDSEL/P30
I/O
Vendor ID selection / Internal µC IO port 3.0
12
NC
13
LED0/P33
I/O
Num. Lock LED / Internal µC IO port 3.3
14
PSCLK/P32
I/O
PS/2 mouse clock pin / Internal µC IO port 3.2
15
PSDA/P31
I/O
PS/2 mouse data pin / Internal µC IO port 3.1
16
LED1/P34
I/O
Caps Lock LED / Internal µC IO port 3.4
17
LED2/P35
I/O
Scroll Lock LED / Internal µC IO port 3.5
18
RESET
none
INPUT
Not Used
Chip reset pin
19
X2
OUTPUT
20
X1
INPUT
Clock input
21
VDD
POWER
VDD power
22
SO08/P20
I/O
Keyboard scan Output 08 / Internal µC IO port 2.0
23
SO09/P21
I/O
Keyboard scan Output 09 / Internal µC IO port 2.1
24
NC
25
SO10/P22
I/O
Keyboard scan Output 10 / Internal µC IO port 2.2
26
SO11/P23
I/O
Keyboard scan Output 11 / Internal µC IO port 2.3
27
SO12/P24
I/O
Keyboard scan Output 12 / Internal µC IO port 2.4
28
SO13/P25
I/O
Keyboard scan Output 13 / Internal µC IO port 2.5
29
SO14/P26
I/O
Keyboard scan Output 14 / Internal µC IO port 2.6
30
SO15/P27
I/O
Keyboard scan Output 15 / Internal µC IO port 2.7
none
Clock output
Not Used
9
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
5.3 48-PIN LQFP, continued
PIN NO.
NAME
TYPE
DESCRIPTION
31
SI7/P17
I/O
Keyboard scan Input 7 / Internal µC IO port 1.7
32
SI6/P16
I/O
Keyboard scan Input 6 / Internal µC IO port 1.6
33
SI5/P15
I/O
Keyboard scan Input 5 / Internal µC IO port 1.5
34
SI4/P14
I/O
Keyboard scan Input 4 / Internal µC IO port 1.4
35
SO03/P03
I/O
Keyboard scan Output 03 / Internal µC IO port 0.3
36
SO02/P02
I/O
Keyboard scan Output 02 / Internal µC IO port 0.2
37
SO01/P01
I/O
Keyboard scan Output 01 / Internal µC IO port 0.1
38
SO00/P00
I/O
Keyboard scan Output 00 / Internal µC IO port 0.0
39
SO16
OUTPUT
Keyboard scan Output 16
40
SO17
OUTPUT
Keyboard scan Output 17
41
EESCL
OUTPUT
42
VID1
INPUT
Vendor ID selection 1
43
VID0
INPUT
Vendor ID selection 0
44
EESDA
45
VSS
POWER
46
VSS
POWER
47
D+
I/O
USB signal (+)
48
D-
I/O
USB signal (-)
I/O
Clock pin of External serial EEPROM
Data pin of External serial EEPROM
Ground
Ground
10
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
6
FUNCTIONAL DESCRIPTION
6.1
First In First Out Storage (FIFO'S) Organization
The W81281 has six FIFO's, one for receiving and five for transmitting.
FIFO or
SRAM
SIZE (Byte )
NOTES
Endpt 0
Receiving
8
Data received on upstream port which contains the correct address
and pids will be stored here for the CPU core to read.
Endpt 0
Transmitting
8
The CPU core writes the data here which will be sent to the host when
the correct address and pids are transmitted by the host.
Endpt 1
Transmitting
8
The CPU core writes the data here which will be sent to the host when
the correct address and pids are transmitted by the host.
Endpt 2
Transmitting
8
The CPU core writes the data here which will be sent to the host when
the correct address and pids are transmitted by the host.
Endpt 3
Transmitting
8
The CPU core writes the data here which will be sent to the host when
the correct address and pids are transmitted by the host.
Endpt 4
Transmitting
8
The CPU core writes the data here which will be sent to the host when
the correct address and pids are transmitted by the host.
6.1.1
INTERFACE TO THE MICROCONTROLLER:
The FIFOs communicate with the CPU core by address 06H 0f External DATA Memory Access of CPU
during IP.6 = "1".The FIFO access steps are firstly set IP.6 = "1" in CPU core. Secondly, CPU core selects
FIFO to access by setting the followed bits in control register 2 :
EP0_RD_EN : read "IN" FIFO of Endpoint 0 ( EP0 ).
EP0_WR_EN : write "OUT" FIFO of Endpoint 0 ( EP0 ).
EP1_WR_EN : write "OUT" FIFO of Endpoint 1 ( EP1 ).
EP2_WR_EN : write "OUT" FIFO of Endpoint 2 ( EP2 ).
EP3_WR_EN : write "OUT" FIFO of Endpoint 3 ( EP3 ).
EP4_WR_EN : write "OUT" FIFO of Endpoint 4 ( EP4 ).
Then access FIFO by address 06H of External DATA Memory Access of CPU. For detailed programming
steps, refer to section 7.3 Programming Note.
11
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
6.2
Register Descritpion
The CPU core accesses registers by External DATA Memory Access during IP.6 = "1"‘1’
6.2.1
Status Registers
CPU core can set "High" at USB_EventINT_EN bit of control register 4 to enable interrupt of USB events to
INT0. When interrupt comes, CPU reads status register 0 and 1 to check which event occurs. ( refer to
section 7.2 for accessing Status Registers )
Status Register 0: Address = 00H (Interrupt Event Flags)
BIT
SYMBOL
DESCRIPTION
7
NAK_EP0_IN
NAK occurs from EP0 for IN Transaction. ( only valid during
NakEP0In_INT_EN = 1 in Control Register 3 )
6
ACK_EP0_SETUP
ACK occurs from EP0 for SETUP Transaction
5
ACK_EP0_OUT
ACK occurs from EP0 for OUT Transaction
4
ACK_EP0_IN
ACK occurs from EP0 for IN Transaction
3
ACK_EP1_IN
ACK occurs from EP1 for IN Transaction
2
ACK_EP2_IN
ACK occurs from EP2 for IN Transaction
1
ACK_EP3_IN
ACK occurs from EP3 for IN Transaction
0
ACK_EP4_IN
ACK occurs from EP4 for IN Transaction
Status Register 1: Address = 01H (Interrupt Event Flags)
BIT
7-6
SYMBOL
DESCRIPTION
VID[1:0]
Keyboard Scan Matrix Selection.
5
Reserved
must ignore this value.
4
EP0OutNullData
receiving Null Data at EP0 during OUT Transaction
3
Suspend_In
Suspend Mode active ( no traffic on USB Bus > 3 mS )
2
USB_Reset
receiving Reset command from USB Bus
1
Resume_In
receiving Resume command from USB Bus
0
Reserved
must ignore this value
12
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
Status Register 2: Address = 07H (Data Byte Count of EP0 IN FIFO)
BIT
SYMBOL
DESCRIPTION
7-4
Reserved
must ignore those values
3-0
DataLength_CNT[3:0]
Number of Data byte for EP0 FIFO ( receiving Data from USB Bus
)
6.2.2
Control Registers
( All registers are set to 00h at power up.)( refer to section 7.1 for accessing Control Registers )
Control Register 0: Address = 02H (Endpoint Enable Control)
BIT
7-5
SYMBOL
DESCRIPTION
Reserved
must keep bits = “0”
4
USB_Speed
set
3
EP1_EN
set "High" to enable Endpoint 1
2
EP2_EN
set "High" to enable Endpoint 2
1
EP3_EN
set "High" to enable Endpoint 3
0
EP4_EN
set "High" to enable Endpoint 4
igh” for Full Speed; set "Low" for Low Speed
Control Register 1: Address = 03H (Device Address Setting)
BIT
7
6-0
SYMBOL
DESCRIPTION
Bus_Connection
connect up stream port on USB Bus after chip initialization done
Device_Address[6:0]
Setup Device Address
Control Register 2: Address = 04H (FIFO Access Control)
BIT
SYMBOL
DESCRIPTION
7
Reserved
must keep bit = "0".
6
Set_Stall
Set Stall for EP 0 -4 ( refer to section 7.4 for programming )
13
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
5
EP0_RD_EN
Set "High" before reading IN FIFO of EP0 (receiving Data from USB Bus )
4
EP0_WR_EN
Set "High" before writting OUT FIFO of EP0 (transmitting Data to USB Bus
)
3
EP1_WR_EN
Set "High" before writting OUT FIFO of EP1 (transmitting Data to USB Bus
)
2
EP2_WR_EN
Set "High" before writting OUT FIFO of EP2 (transmitting Data to USB Bus
)
1
EP3_WR_EN
Set "High" before writting OUT FIFO of EP3 (transmitting Data to USB Bus
)
0
EP4_WR_EN
Set "High" before writting OUT FIFO of EP4 (transmitting Data to USB Bus
)
Control Register 3: Address = 05H (USB Event Control)
BIT
SYMBOL
DESCRIPTION
7
Reserved
must keep bit = "0"
6
NakEP0In_INT_EN
Enable interrupt event when NAK comes from EP0 for IN Transaction
5
Set_EP0NullData
set Null Data for IN Transaction of EP 0 ( refer to section 7.5 for
programming )
4
Warm_Reset
Active Warm Reset
3
Resume_Out
Send Resume command (K-state) to USB Bus ( Set_Suspend should
be “1” )
2
Set_Suspend
Set suspend mode active
1
Read_Event
Set "High" during reading Status Registers ( refer to section 7.2 for
programming )
0
Set_EP0_Nak
Set "High" for responsing Nak when IN/OUT Transaction of EP0 come
14
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
Control Register 4: Address = 08H (Interrupt Enable Control)
BIT
7-4
SYMBOL
DESCRIPTION
Reserved
must keep bits = "0"
3
Remote_Wakeup_EN
for Remote Wakeup Enable from Keystroke or Mouse moving
2
USB_EventINT_EN
for USB event interrupt enable
1
SCANOUT[17]
output port value of port SO17
0
SCANOUT[16]
output port value of port SO16
Control Register 5: Address = 09H (CPU Reset Control)
BIT
7-2
SYMBOL
DESCRIPTION
Reserved
must keep bit = "0"
1
UC_WarmReset_EN
set "High" for reseting CPU when Warm_Reset = "1"
0
DisconUSB_Bus_Disable
set "High" keeping device conecting with USB Bus during
software or hardware reset
set
ow” disconnecting with USB Bus during software or
hardware reset
Control Register 6: Address = 0EH (Watch Dog Timer Reset)
BIT
7-0
6.3
SYMBOL
Reset_WDT
DESCRIPTION
Clear WDT = 00H when set Reset_WDT = AAH
Reset
The W81281 supports three types of reset. During a reset, all registers of the CPU core and USB return to
their default status, and USB device address is set to zero.
15
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
6.3.1
External Reset (Hardware Reset)
As in 8051 series controller, the external RESET signal is sampled at S5P2. To take effect, it must be held
high at least two machine cycles while the oscillator is running.
An internal trigger circuit in the reset line is used to deglitch the reset line. The reset logic also has a special
glitch remocal circuit that ignores glitches on the reset line.
During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON(with exception of bit 4) to
00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
6.3.2
Warm Reset (Software Reset)
W81281 provides a warm reset by setting "High" at Warm_Reset bit of control register 3.
The W81281 handles the USB reset function independently from the CPU core. If a Single Ended Zero
(SE0) is detected on the upstream port for greater then 2.5us, then the interrupt is enabled. The CPU core
read flag from USB_Reset bit of status register 1 then CPU
- to reset the device address to 0, and enter the default state. No any reset timing occurs.
or
- to set "High" at Warm_Reset bit of control register
6.3.3 WDT Reset (Hardware Reset)
There is a Watch Dog Timer installed in W81C281. CPU should periodically clear WDT to 00H by setting
Reset_WDT=AAH before WDT time out. If CPU hangs WDT will time-out and cause hardware reset.
6.4
USB SUSPEND
If there is no upstream activity for 3 msec then the Suspend_In flag is set and the interrupt enabled. When
Suspend_In flag is read, CPU core actives power down mode for W81281 go into suspend
6.5
USB RESUME:
The suspend state can be exit by a 'resume'. The resume can occur by three methods.
• The host can send a resume to all ports by placing a 0 (K state) on the bus. The W81281 sees the
resume, , and enables the interrupt. In this case, the CPU core does not have to perform any functions.
• The host can reset the bus.
• When any falling edge is detected on CPU port1(keystrokes). The CPU core will exit from power down
mode and initiate a resume by setting Resume_Out in the Control Register 3 which will cause a K state
to be sent. To un-resume, the CPU core must clear the Resume_Out bit in the Control Register 3.
16
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
7.
PROGRAMMING NOTES:
The W81281 uses reserved bit of the Interrupt Priority Register IP.6 as a pre-decoding bit to implement a
alternative register and FIFO by External Data Memory Access of CPU core. Programming functions
described as below:
7.1
Control Registers Access:
Step 1: set IP.6 = 1
Step 2: access Control Register (by MOVX Instruction)
Step 3: set IP.6 = 0
7.2
Status Registers Access:
Step 1: set IP.6 = 1
Step 2 : set Read_Event = 1 in Control Register 3 ( by MOVX Instruction )
step 3 : access Status Registers ( by MOVX Instruction )
step 4 : set IP.6 = 0
7.3
FIFOs Access :
step 1 : set IP.6 = 1
step 2 : set EP0_RD_EN/EPX_WR_EN = 1 ( X : 0 - 4) (by MOVX Instruction )
step 3 : access FIFO by address 06H of MOVX Instruction
step 4 : set EP0_RD_EN/EPX_WR_EN = 0 ( X : 0 - 4) (by MOVX Instruction )
step 5 : set IP.6 = 0
7.4
Set Stall for Endpoint 0 - 4 :
step 1 : set IP.6 = 1
step 2 : set Set_Stall = 1 (by MOVX Instruction )
step 3 : set EP0_RD_EN/EPX_WR_EN = 1 ( X : 0 - 4) (by MOVX Instruction )
step 4 : set EP0_RD_EN/EPX_WR_EN = 0 ( X : 0 - 4) (by MOVX Instruction )
step 5 : set Set_Stall = 0 (by MOVX Instruction )
step 6 : set IP.6 = 0
Note : 1. EP0_RD_EN = 1 for OUT Transaction of
EP0.
17
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
2. EP0_WR_EN = 1 for IN Transaction of EP0.
7.5
Set Null Data for IN Transaction of EP 0 :
step 1 : set IP.6 = 1
step 2 : set Set_EP0NullData = 1 (by MOVX Instruction )
step 3 : set EP0_WR_EN = 1 (by MOVX Instruction )
step 4 : set EP0_WR_EN = 0 (by MOVX Instruction )
step 5 : set Set_EP0NullData = 0 (by MOVX Instruction )
step 6 : set IP.6 = 0
18
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
8.
ELECTRICAL CHARACTERISTICS & CAPACITANCE
J + 70¢ ,JVDD = +5V ± 5% )
(Ta = 0¢ to
SYMBOL
DESCRIPTION
MIN.
TYP.
MAX.
UNIT
4.0
5.0
5.5
V
VDD
Power Support
VIL
Input Low Voltage (except RESET)
0.8
V
VIL1
Input Low Voltage (RESET)
0.6
V
VIH1
Input High Voltage (except RESET)
2.0
V
VIH2
Input High Voltage (RESET)
3.5
V
VOH
Output High Voltage (except D+/D-)
VOL
Output Low Voltage (except D+/D-)
0.4
IOFL
Output Leakage Current (High-Z
state)
-10
10
uA
Input Leakage Current
-10
10
uA
IIH
2.4
NOTE
V
IOH=-4mA
V
IOL= 4mA
VDD=5.5V
VIN=VDD
IIL
Input Leakage Current
-10
10
uA
VDD=5.5V
VIN=VSS
19
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
Symbol
Conditions
Min
Max
Unit
+10
µA
D+/D- Leakage Current:
Hi-Z State Data Line Leakage
ILO
0 V < VIN < 3.3V
-10
VDI
(D+)-(D-)
0.2
Includes VDI range
0.8
2.5
V
0.8
2.0
V
0.3
V
3.6
V
20
pF
D+/D- Input Levels:
Differential Input Sensitivity
Differential Common Mode Range
VCM
Single Endge Receiver Threshold
VSE
V
D+/D- Output Levels:
Static Output Low
VOL
RL of 1.5kΩ to 3.6V
Static Output High
VOH
RL of 1.5kΩ to GND
CIN
Pin to GND
Rise Time
TR
CL=50pF/350pF
75
300
ns
Fall Time
TF
CL=50pF/350pF
75
300
ns
(TR / TF)
80
125
%
1.3
2.0
V
2.8
D+/D- Capacitance:
Transceiver Capacitance
D+/D- Driver Characteristics:
Transition Time:
Rise / Fall Time Matching
TRFM
Output Signal Crossover Voltage
VCRS
D+/D- Data Source Timings:
Low Speed Data Rate
TDRATE
Ave.Bit Rate
1.4775 1.5225
Mbs
(1.5Mb/s ±1.5%)
Source Differential Driver Jitter
To Next Transition
TDJ1
-95
95
ns
For Paired Transitions
TDJ2
-150
150
ns
Source EOP Width
TEOPT
1.25
1.50
µs
Differential to EOP Transition Skew
TDEOP
-40
100
ns
To Next Transition
TDJR1
-75
75
ns
For Paired Transitions
TDJR2
-45
D+/D- Data Receiver Timings:
Receiver Data Jitter Tolerance
Receiver SE0 Tolerance during
Differential Transition
TLST
45
ns
210
ns
20
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
EOP Width at receiver
Must reject as EOP
TEORP1
330
ns
Must accept as EOP
TEOPR2
675
ns
21
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
9.
USB KEYBOARD SAMPLE APPLICATION
1. For 40 pin DIP package
W81281 USB Keyboard Reference
S h
i
VCC
U1
+
VCC
R6
R7
30
30
UU+
R1
7.5K
VCC
USB1
USB-CONN
1
2
3
4
L7
L8
L1
L2
FB
FB
FB
FB
+
C4
0.1u
6 5
C5
10u
5
6
7
8
34
33
32
31
ScanIn0
ScanIn1
ScanIn2
ScanIn3
ScanIn4
ScanIn5
ScanIn6
ScanIn7
38
37
36
35
9
10
11
12
ScanOut0
ScanOut1
ScanOut2
ScanOut3
ScanOut4
ScanOut5
ScanOut6
ScanOut7
23
24
25
26
27
28
29
30
ScanOut8
ScanOut9
ScanOut10
ScanOut11
ScanOut12
ScanOut13
ScanOut14
ScanOut15
39
40
ScanOut16
ScanOut17
SI0
SI1
SI2
SI3
SI4
SI5
SI6
SI7
VDD
VDD3
VSS
RESET
X1
X2
SO0
SO1
SO2
SO3
SO4
SO5
SO6
SO7
IDSEL
LED0
LED1
LED2
SO8
SO9
SO10
SO11
SO12
SO13
SO14
SO15
DD+
PSDA
PSCLK
22
4
1
19
RESET
21
20
X1
X2
IDSEL
13
LED0
LED1
LED2
14
17
18
3
2
DD+
PSDA
PSCLK
16
15
SO16
SO17
VCC
W81281
L3
FB
PSDA
L4
PSCLK
L5
VCC
CapsLoc
JP4
1
2
3
4
5
6
FB
FB
C7
47p
L6
FB
C1
47p
NumLoc
k
R 100ohm
be short
an
while
not used
J
PS/2 MOUSE
ScrollLoc
D1
D2
D3
R2
100
R3
100
R4
100
LED0
LED1
VCC
LED2
+
C2
C8
10u
X1
JP1
RESET
R5
3.3K
30p
X1
6MHZ Crystal / Resonator
JUMPER
C3
X2
30p
IDSEL
JUMPER
JP2
JP3
JUMPER
Only one
Jumper
can be
short
or all
22
Publication Release Date: July 1999
Revision 0.60
C6
10u
W81281
Preliminary
For 48 pin LQFP package reference circuit
W81281 (48pin LQFP) USB Keyboard Reference Schematic
VCC
CapsLock
VCC
L3
NumLock
FB
D1
D2
D3
ScrollLock
VCC
PSDA
U1
2
3
4
5
34
33
32
31
ScanIn0
ScanIn1
ScanIn2
ScanIn3
ScanIn4
ScanIn5
ScanIn6
ScanIn7
38
37
36
35
7
8
9
10
ScanOut0
ScanOut1
ScanOut2
ScanOut3
ScanOut4
ScanOut5
ScanOut6
ScanOut7
22
23
25
26
27
28
29
30
ScanOut8
ScanOut9
ScanOut10
ScanOut11
ScanOut12
ScanOut13
ScanOut14
ScanOut15
39
40
ScanOut16
ScanOut17
+
VDD 1
VDD3 45
VSS 46
VSS
RESET
PSCLK
1
2
3
4
5
6
L6
FB
FB
R3
R4
100
100
C1
LED0
47p
LED1
LED0
LED1
LED2
13
LED0 16
LED1 17
LED2
R2
100
PS/2 MOUSE
C7
47p
IDSEL
VID0
VID1
11
IDSEL 43
VID0 42
VID1
LED2
Option
48
D- 47
D+
DD+
JP1
PSCLK
PSDA
EESCL
EESDA
14
PSCLK 15
PSDA 41
EESCL 44
EESDA
JP2
JP3
VCC
EESDA
EESCL
6
NC 12
NC 24
NC
SO16
SO17
JP4
FB
X1
X2
20
SO8
SO9
SO10
SO11
SO12
SO13
SO14
SO15
L5
RESET
18
X1 19
X2
SO0
SO1
SO2
SO3
SO4
SO5
SO6
SO7
L4
C6
10u
21
SI0
SI1
SI2
SI3
SI4
SI5
SI6
SI7
R 100ohm can
be short
while Jumper
not used
JUMPER JUMPER JUMPER
U2
5
6
7
8
Only one
Jumper
can be
short
or all open
4
SDA
SCL
RC
VCC
VSS 3
A2 2
A1 1
A0
IDSEL
24LC04B
W81C281-48
VID0
JP4
JUMPER
VCC
VID1
R6
R7
R1
30
30
UU+
JP5
JUMPER
VCC
7.5K
VCC
USB1
USB-CONN
1
2
3
4
C2
L7
L8
L1
L2
+
FB
FB
X1
C8
10u
RESET
+
5
6
FB
FB
C4
0.1u
C5
10u
30p
C3
R5
3.3K
30p
X1
6M
inbond
X2
WINBOND ELECTRONICS CORP.
Title
W81281 USB Keyboard Reference Schematic
Size
B
Document Number
281DEMO4.SCH
Date:
Monday, January 25, 1999
Rev
1.3
Sheet
1
of
1
23
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
10.
PACKAGE DIMENSIONS
40-pin DIP
Symbol
A
A1
A2
B
B1
c
D
E
E1
e1
L
D
40
21
E1
Dimension in inches
Dimension in mm
Min.
Min. Nom. Max.
0.010
0.150
0.25
0.155
0.160
3.81
3.94
4.06
0.56
0.016
0.018
0.022
0.41
0.46
0.048
0.050
0.054
1.22
1.27
1.37
0.008
0.010
0.014
0.20
0.25
0.36
2.055
2.070
52.20
52.58
0.590
0.600
0.610
14.99
15.24
15.49
0.540
0.545
0.550
13.72
13.84
13.97
0.090
0.100
0.110
2.29
2.54
2.79
0.120
0.130
0.140
3.05
3.30
3.56
15
0
0.670
16.00
16.51
17.02
0
0.630
eA
S
0.650
15
0.090
2.29
Notes:
20
E
S
c
A A2
A1
Base Plane
Seating Plane
L
B
5.33
0.210
a
1
Nom. Max.
e1
eA
a
B1
1. Dimensions D Max & S include mold flash or
tie bar burrs.
2. Dimension E1 does not include interlead flash.
3. Dimensions D & E1 include mold mismatch and
. parting line.
are determined at the mold
4. Dimension B1 does not include dambar
protrusion/intrusion.
5. Controlling dimension: Inches.
6. General appearance spec. should be based on
final visual inspection spec.
28-pin SOP
15
28
c
Control demensions are in milme
DIMENSION IN MM
DIMENSION IN INCH
SYMBOL
MIN.
E
H
E
A
2.35
2.65
14
MAX.
0.104
A1
0.10
0.30
0.004
0.012
0.33
0.51
0.013
0.020
c
0.23
0.32
0.009
0.013
E
7.40
7.60
0.291
0.299
D
17.70
18.10
0.697
0.713
e
D
MIN.
0.093
b
L
1
MAX.
0.050 BSC
1.27 BSC
O
0.25
H
10.00
10.65
0.394
0.419
E
Y
A
0.10
L
0.40
θ
0
1.27
0.004
0.016
0.050
Y
SEATING PLANE
e
b
GAUGE PLANE
8
0
8
A1
24
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
48-pin LQFP
HD
D
25
36
Symbol
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
24
37
E
HE
13
48
1
e
b
12
0
Dimension in inch
Dimension in mm
Min.
Min.
Nom.
Max.
---
---
1.60
0.05
---
0.15
1.35
1.40
1.45
0.17
0.20
0.27
0.09
---
0.20
Nom.
Max.
7.00
7.00
0.50
9.00
9.00
0.45
0.60
0.75
1.00
---
0.08
---
0
3.5
7
Notes:
c
A2
Seating Plane
See Detail F
A
A1
y
L
L1
Detail F
1. Dimensions D & E do not include interlead
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Controlling dimension: Millimeters
4. General appearance spec. should be based
on final visual inspection spec.
Headquarters
Winbond Electronics (H.K.) Ltd.
No. 4, Creation Rd. III
Science-Based Industrial Park
Hsinchu, Taiwan
TEL: 886-35-770066
FAX: 886-35-789467
www: http://www.winbond.com.tw/
Rm. 803, World Trade Square, Tower II
123 Hoi Bun Rd., Kwun Tong
Kowloon, Hong Kong
TEL: 852-27516023-7
FAX: 852-27552064
Winbond Electronics
(North America) Corp.
2730 Orchard Parkway
San Jose, CA 95134 U.S.A.
TEL: 1-408-9436666
FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
TLX: 16485 WINTPE
25
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
26
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
27
Publication Release Date: July 1999
Revision 0.60
W81281
W81281 USB Keyboard Reference
h
i
VCC
Preliminary
U1
+
VCC
R6
R7
30
30
ScanIn0
ScanIn1
ScanIn2
ScanIn3
ScanIn4
ScanIn5
ScanIn6
ScanIn7
UU+
R1
7.5K
5
6
7
8
34
33
32
31
VCC
W81281 (48pin LQFP) USB Keyboard Reference Schematic
USB1
USB-CONN
L7
L8
L1
L2
1
2
3
4
FB
FB
FB
FB
+
C4
0.1u
6 5
C5
10u
ScanOut8
L3 VCC
ScanOut9
FB
ScanOut10
ScanOut11
ScanOut12
ScanOut13
ScanOut14
ScanOut15
VCC
PSDA
U1
2
3
4
5
34
33
32
31
ScanIn0
ScanIn1
ScanIn2
ScanIn3
ScanIn4
ScanIn5
ScanIn6
ScanIn7
+
RESET
PSCLKSO7
22
23
25
26
27
28
29
30
ScanOut8
ScanOut9
ScanOut10
ScanOut11
ScanOut12
ScanOut13
ScanOut14
ScanOut15
39
40
ScanOut16
ScanOut17
D- 47
D+
FB
DD+
14
PSCLK
PSDA
EESCL
EESDA C1
47p
PSCLK 15
PSDA 41
EESCL 44
C7
EESDA
47p6
NC 12
NC 24
NC
SO16
SO17
FB
39
40
RESET
X1
X2
SO0
SO1
SO2
SO3
SO4
SO5
SO6
SO7
RESET
X1
X2
C6
10u
IDSEL
14
17
18
LED0
LED1
LED2
SO8
SO9
SO10
SO11
SO12
SO13
SO14
SO15
19
21
20
13
IDSEL
LED0
LED1
LED2
VCC
CapsLock
3
DD+
D-
2
NumLock
D2D+
D1
D3
ScrollLock
PSDA
PSCLK
16
PSDA
15
RPSCLK
100ohm can
be short
while Jumper
not used
SO16
SO17
R2
R3
R4
100
100
100
W81281
C7
C1
1
2
3
4
5
6
L6
FB
VCC
LED0
47p
CapsLoc
LED1
JP4
48
SO8
SO9
SO10
SO11
SO12
SO13
SO14
SO15
L6
47p
LED0
LED1
LED2
13
LED0 16
FB
LED1
17
LED2
1
2
3
4
5
6
23
24
25
26
27
28
29
30
VDD
VDD3
VSS
PS/2 MOUSE
L3
FB
IDSEL
VID0
VID1
11
JP4
ScanOut16
ScanOut17
FB
FB
X1
X2
IDSEL 43
VID0 42
VID1
L5
L5
RESET
18
X1 19
X2
L4
PSCLK
VCC
20
38
37 SO0
36 SO1
PSDA
35 SO2
7 SO3
8 SO4
9 SO5
10 SO6
ScanOut0
ScanOut1
ScanOut2
ScanOut3
ScanOut4
ScanOut5
ScanOut6
ScanOut7
10u
VDD 1
VDD3 45
VSS 46
VSS
L4
C6
21
SI0
SI1
SI2
SI3
SI4
SI5
SI6
SI7
38
37
36
35
9
10
11
12
ScanOut0
ScanOut1
ScanOut2
ScanOut3
ScanOut4
ScanOut5
ScanOut6
ScanOut7
SI0
SI1
SI2
SI3
SI4
SI5
SI6
SI7
22
4
1
NumLoc
D1
ScrollLoc
LED2
D2
D3
Option
JP1
JP2
JP3
VCC
PS/2 MOUSE
EESDA
EESCL
R 100ohm
be short
an
4
VSS 3 while
not used
A2 2 Jumper
A1 1
A0
U2
5
6
7
8
SDA
SCL
RC
VCC
JUMPER JUMPER JUMPER
R2
100
R3
100
Only one
Jumper
can be
short
or all open
R4
100
IDSEL
24LC04B
W81C281-48
LED0
LED1
VCC
LED2
+
C8
10u
VCC
JUMPER
C2
X1
R6
R7
RESET
R1
30
30
USB-CONN
1
2
3
4
L7
L8
L1
L2
JP1
U-
30p U+
7.5K
USB1
R5
3.3K
VCC
FB
FB
30p
VID1
JP3
JP2
X1
6MHZ Crystal / Resonator
JUMPER
JUMPER
JUMPER
Only one
Jumper
can be
short
or all
open
C3
X2
C2
+
+
5
6
C4
0.1u
X1
C8
10u
C5
10u
IDSEL
30p
C3
R5
3.3K
JP5
JUMPER
VCC
RESET
FB
FB
JP4
VID0
X1
6M
inbond
X2
WINBOND ELECTRONICS CORP.
30p
Title
W81281 USB Keyboard Reference Schematic
Size
B
Document Number
281DEMO4.SCH
Date:
Monday, January 25, 1999
Rev
1.3
Sheet
1
of
1
APPENDIX A: WINBOND( W81281-004) DEFAULT MATRIX CODE
VID: 0000 PID: 0801(with PS/2 mouse) PID: 0802(without PS/2 mouse)
101(AT)/102(Europe+Macro)(+Fn)/103(Korean)(Brazillian)/106(Japan.)+Windows 95 keys compatible
28
Publication Release Date: July 1999
Revision 0.60
25
8
26
9
27
0
2D
-
2E
+
2A
BKS
2B
TAB
29
ESC
1E
1
1F
2
20
3
21
4
22
5
23
6
SI2
SI3
SI4
SI5
SI6
SI7
Macro
0C
I
18
U
1C
Y
17
T
15
R
08
E
1A
W
16
S
04
A
51
Down
28
Enter
30
]
2F
[
13
P
33
;
0F
L
0E
K
0D
J
0B
H
0A
G
09
F
19
V
06
C
1B
X
1D
Z
\
K42
32
4D
End
35
~
55
*
4C
Del
38
?
37
>
36
<
10
M
11
N
3E
F5
3D
F4
3C
F3
3B
F2
3A
F1
4E
PgDn
2C
SPC
45
F12
44
F11
29
59
46
P_1 PrtScr
47
57
Scroll P_+
5F
P_7
63
P_.
62
P_0
5B
P_3
\
J-NCHG
E0
Ctrl-L
4B
E4
PgUp Ctrl-R
52
Up
49
Ins
4F
Right
50
Left
J-CHG
K132
8A
ED
E8
54
/
Sleep
E9
EF
65
APP
F2
F3
E5
Shift-R
01
F0
J-14
J-56
F7
BZ0
K56
87
F8
Kor0-L
K150
91
F9
F6
FB
FF
BZ1
K107
94
E5
Shift-R
Kor1-R
K151
90
EA
EE
Publication Release Date: July 1999
Revision 0.60
J-ROMA
K133
88
E6
E7
Alt-R Win-R
E2
Alt-L
F4
01
01
K14
K56
01
89
87
F1
4A Wake E3
Home -up Win-L
5D
58
48 Power
P_5 P_Entr Pause
5C
P_4
56
P_-
61
P_9
53
5E
Num P_6
43
F10
42
F9
41
F8
40
F7
SO0 SO1 SO2 SO3 SO4 SO5 SO6 SO7 SO8 SO9 SO10 SO11 SO12 SO13 SO14 SO15 SO16 SO17
24
14
12
07
34
05
39
3F
60
5A
E1
EC 8B
F5 FA EB
31
64
7
Q
O
D
B Caps F6 P_8 P_2
“
K45
K29
K131 Shift-L
SI1
SI0
Preliminary
W81281
W81281
Preliminary
NOTE 1: The contents in the table are hexadecimal HID codes and function descriptor.
2: Six are scan-in lines, Sox are scan-out lines.
3: The three ACPI power management keys for Windows 98 are Power (SI4-SO12), Sleep (SI5SO13) and Wakeup (SI1-SO12).
Multimedia Buttons & Reserved Buttons (W81281-004)
HID Code
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Functions (ref. Qtronix)
Play/Pause
Stop/Eject
Rewind
Forward
Record
Volume+
VolumeMute
WWW
Previous
Next
Stop
Search
Scroll
-Up
Scroll
-Down
Menu
Suspend
Coffee
Xfer
Calculator
Reserved (OnNow
-Power)
Reserved (OnNow
-Sleep)
Reserved (OnNow
-Wakeup)
Reserved
30
Publication Release Date: July 1999
Revision 0.60
SI7
SI6
SI5
SI4
SI3
SI2
SI1
SI0
25
K9
1A
K18
13
K26
09
K34
35
K1
11
K51
50 72 72
2C
40
61
5B
K61 K118 K101 K103
0A
K35
4D
K81
10
K52
27
K11
15
K20
30
K28
0B
K36
K42
32
36
3A
42
5C
K53 K112 K120 K92
0D
K37
1D
K46
37
3B
43
5D
K54 K113 K121 K97
2E
K13
1C
K22
51
K84
0E
K38
1B
K47
2A
K15
18
K23
2B
K16
0F 0D
0D
23
K7
07 36 36
16
K32
1E 1C
1C
04
K31
06
K48
33
K40
19
55
3E
5F
K49 K100 K116 K91
59
K93
31
37 7C 57
46
K124
58 07 5E
4C
3D
47
57
45
K76 K115 K125 K106 K123
26 4B 4B 2E 21 21 53 71 64 3E 0C 1F 46 7E 5F 4E 79 7C
0F
K39
17 43 43 1F 1B 1B 27 4C 4C 2F 2A 2A 37 7C 7E 3F 03 27 47 6C 6C 4F 69 69
0C
K24
06 2E 2E 0E 66 66 16 3C 3C
22
K6
57 78 56
38
3C
53
5E
44
K55 K114 K90 K102 K122
05 25 25 0D 55 55 15 35 35 50 72 60 25 42 42 2D 22 22 35 4A 4A 3D 04 17 45 77 76 4D 74 74
21
K5
52 70 67
49
K75
4D 74 6A
4F
K89
4B 6B 61
50
K79
FF FF 62
28
K43
04 26 26 0C 4E 4E 14 2C 2C 1C 5A 5A 24 3B 3B 2C 1A 1A 34 49 49 3C 06 0F 44 09 4F 4C 73 73 1C 5A 79
17
K21
49 7D 6F
4B
K85
48 75 63
48
K126
2D
K12
53 71 71
63
K104
52
K83
47 6C 6E
4A
K80
2B 5D 5C
58
K108
20
K4
03 1E 1E 0B 45 45 13 2D 2D 1B 5B 5B 23 33 33 2B 5D 53 33 41 41 3B 05 07 43 01 47 4B 6B 6B
1F
K3
52 70 70
2F
K27
02 16 16 0A 46 46 12 24 24 1A 54 54 22 34 34 4F 69 65 32 3A 3A 51 7A 6D 42 0A 3F 4A 7B 84
08
K19
62
K99
26
K10
4E
41
56
K86 K119 K105
1E
K2
01 76 08 09 3E 3E 11 1D 1D 19 4D 4D 21 2B 2B 29 0E 0E 31 31 31 39 29 29 41 83 37 49 7D 7D 51 7A 7A
29
K110
56 61 13 08 3D 3D 10 15 15 18 44 44 20 23 23 28 52 52 30 32 32 3A 58 14 40 0B 2F 48 75 75
35 4A 77
54
K95
E8
65
K129
5D 2F 8D
79 64 86
F2
K132
8A
ED
5F 3F
F6
5C 27 8C
E7
K128
FB
FF
7E 6D 7B
Publication Release Date: July 1999
Revision 0.60
70 13 87
K133
88
38 11 39
E6
K62
38 11 19
K107
94
36 59 59
F7
E2
K60
73 51 51
E5
K57
F0 F2 F2
K151
90
EA
EE
K56
87
F8
F1 F1 F1
F3
F4
01
36 59 59
E5
K57
01
K150
91
F9
5E 37
EF
F0
01
F1
01
K14
7D 6A 5D
K56
73 51 51
89
5B 1F 8B
87
2A 12 12
E9
1D 14 58
E4
K64
1D 14 11
E0
K58
63 5E
E3
K127
7B 67 85
SO0 SO1 SO2 SO3 SO4 SO5 SO6 SO7 SO8 SO9 SO10 SO11 SO12 SO13 SO14 SO15 SO16 SO17
24
E1
14
12
07
34
05
39
3F
60
5A
64
EC 8B
F5 FA EB
31
K8 K17 K25 K33 K41 K50 K30 K117 K96 K98
K44
K45
K29
K131
HID Codes vs. Legacy Scan-Codes (W81281-004)
Preliminary
W81281
32
Publication Release Date: July 1999
Revision 0.60
NOTE: The contents in the table are hexadecimal HID Code + Order Number of Legacy Keys + Legacy Scan-Code (set1 set2 set3).
Preliminary
W81281
W81281
Preliminary
Winbond USB Product Roadmap
HUB
W81C180
180
4 potRB5387
HUB
W81C280
USB K/B
W81182
Legacy HUB
W81181D
4 pot HUB
W81281
USB 8052
W81282
HUB+K/B
~
~
K/B
2H/98 1Q/99
2Q/99
3Q/99
4Q/99
1Q/2K
Winbond USB Product Brief
• W81C180: USB 4 Port Hub Controller
• W81181D: High Integrated USB 4 Port Hub Controller
• W81182:USB Legacy Hub, Translate EPP, Serial, PS/2
to USB Connection, Including 4 port USB Hub
• W81C280: USB K/B Controller
• W81281: High Integrated USB+8052 Controller or
USB K/B Controller
• W81282:USB 4 Port Hub + K/B Controller
33
Publication Release Date: July 1999
Revision 0.60
W81281
Preliminary
Headquarters
Winbond Electronics (H.K.) Ltd.
No. 4, Creation Rd. III
Science-Based Industrial Park
Hsinchu, Taiwan
TEL: 886-35-770066
FAX: 886-35-789467
www: http://www.winbond.com.tw/
Rm. 803, World Trade Square, Tower II
123 Hoi Bun Rd., Kwun Tong
Kowloon, Hong Kong
TEL: 852-27516023-7
FAX: 852-27552064
Winbond Electronics
(North America) Corp.
2730 Orchard Parkway
San Jose, CA 95134 U.S.A.
TEL: 1-408-9436666
FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without notice. All the trade
marks of products and companies mentioned in this data sheet belong to their respective owners.
34
Publication Release Date: July 1999
Revision 0.60
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.