w WM8321 Processor Power Management Subsystem DESCRIPTION FEATURES The WM8321 is an integrated power-management subsystem which provides a cost-effective, flexible, single-chip solution for power management. It is specifically targeted at the requirements of a range of low-power portable consumer products, but is suitable to any application with a multimedia processor. The WM8321 is designed to operate as a system PMIC supporting the ARM9™, ARM11™ and ARM Cortex-A™ processors, but is also capable of supporting the majority of application and mobile processors at the heart of a wide range of low-power consumer multimedia applications. Power Management The start-up behaviour and configuration is fully programmable in an integrated OTP non-volatile memory. This highly flexible solution helps reduce time-to-market, as changing application requirements can be very easily accommodated in the OTP. TM The InstantConfig interface enables an external EEPROM to configure the WM8321. The WM8321 power management subsystem comprises four programmable DC-DC converters and eleven LDO regulators (four of which are low-noise for supplying sensitive analogue subsystems). The integrated OTP bootstrap circuitry controls the start-up sequencing and voltages of the converters and regulators as well as the sequencing of system clocks. The DC-DC converters deliver high performance and high efficiency across a wide range of operating conditions. They are optimised to support the high load current transients seen in modern processor core domains. DC-DC3 / DC-DC4 can be connected together and operated in ‘dual’ mode to support an increased current load of up to 1.6A An on-chip regulator provides power for always-on PMIC functions such as register map and the RTC. The device provides autonomous backup battery switchover. A low-power LDO is included to support ‘Alive’ processor power domains external to the WM8321. A 12-bit Auxiliary ADC supports a wide range of applications for internal as well as external analogue sampling, such as voltage detection and temperature measurement. WM8321 includes a crystal oscillator and an internal RC oscillator to generate all clock signals for autonomous system start-up and processor clocking. A Secure Real-time Clock (SRTC) and alarm function is included, capable of waking up the system from low-power modes. A watchdog function is provided to ensure system integrity. To maximise battery life, highly-granular power management enables each function in the WM8321 subsystem to be independently powered down through a control interface or alternatively through register and OTP-configurable GPIOs. The device offers a standby power consumption of <7uA, making it particularly suitable for portable applications. The WM8321 is supplied in an 8x8mm 81-lead QFN package, ideal for use in portable systems. The WM8321 forms part of the Wolfson series of audio and power management solutions, and is widely register compatible with the WM831X devices. 2 x DC-DC synchronous buck converters (0.6V - 1.8V, 1.25A, DVS) 2 x DC-DC synchronous buck converters (0.85V - 3.4V, 1A) 1 x LDO regulator (0.9V - 3.3V, 300mA, 1) 2 x LDO regulators (0.9V - 3.3V, 200mA, 1) 3 x LDO regulators (0.9V - 3.3V, 100mA, 2) 2 x Low-noise LDO regulators (1.0V - 3.5V, 200mA, 1) 2 x Low-noise LDO regulators (1.0V - 3.5V, 150mA, 2) 1 x ‘Alive’ regulator (0.8V – 1.55V, up to 25mA) System Control 2 I C or SPI compatible primary control interface Comprehensive interrupt scheme Watchdog timer and system reset control Autonomous power sequencing and fault detection OTP memory bootstrap configuration function Additional Features Auxiliary ADC for multi-function analogue measurement 128-bit pseudo-random unique ID Secure Real-Time Clock with wake-up alarm 12 x configurable multi-function (GPIO) pins Comprehensive clocking scheme: low-power 32kHz RTC crystal oscillator, GPIO clock output and 4MHz RC clock for power management System LED outputs indicating device power state, and fault status Package Options 8 x 8 x 0.85mm, 81-lead QFN package APPLICATIONS Cellular Handsets Smartphones Electronic Books Portable Media Players Mobile Internet Devices Electronic Gaming Devices Netbooks Smartbooks Set Top Box Digital Picture Frames WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews Production Data, February 2012, Rev 4.0 Copyright 2012 Wolfson Microelectronics plc WM8321 Production Data LED1 LED2 System Status LED Driver Register Map and Application Processor Interface DC4GND DC4FB DC4LX DC4VDD PROGVDD Instant ConfigTM EEPROM Interface DC3GND DC3FB DC3LX DC3VDD Primary Control Interface DC2GND DC2FB DC2LX DC2VDD Interrupt and Reset Controller DC1GND DC1FB DC1LX DC1VDD DBVDD SDA2 SCLK2 IRQ RESET CS SDA1 SCLK1 SDOUT1 CIFMODE BLOCK DIAGRAM DC-DC1 Buck 0.6 to 1.8V 1.25A DC-DC2 Buck 0.6 to 1.8V 1.25A DC-DC3 Buck 0.85 to 3.4V 1A DC-DC4 Buck 0.85 to 3.4V 1A DVS DVS OTP NVM Bootstrap Config & Unique ID Dual Mode Control VREFC References LDO 1 Standard LDO 0.9 to 3.3V 300mA GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 MultiFunction Pin (GPIO) Controller 1 to 4MHz RC Oscillator Power Management Control WM8321 LDO 2 Standard LDO 0.9 to 3.3V 200mA LDO 3 Standard LDO 0.9 to 3.3V 200mA LDO 4 Standard LDO 0.9 to 3.3V 100mA ` PM SubSystem Monitoring LDO 5 Standard LDO 0.9 to 3.3V 100mA LDO 6 Standard LDO 0.9 to 3.3V 100mA ON LDO 7 Analogue LDO 1.0 to 3.5V 200mA AP Interface, GPIOs and PM Control LDO 8 Analogue LDO 1.0 to 3.5V 200mA LDO 9 Analogue LDO 1.0 to 3.5V 150mA GPIO10 GPIO11 GPIO12 LDO 10 Analogue LDO 1.0 to 3.5V 150mA Aux ADC CHIP temperature XTO XTI XOSCGND 32.768kHz Oscillator Real-Time Clock GND (Exposed Ground Paddle) Wake-Up Timer IREFR LDO1VOUT LDO1_2VDD LDO2VOUT LDO3VDD LDO3VOUT LDO4VDD LDO4VOUT LDO5VDD LDO5VOUT LDO6VDD LDO6VOUT LDO7VOUT LDO7_8VDD LDO8VOUT LDO9VOUT LDO9_10VDD LDO10VOUT LDO 11 Alive LDO 0.8 to 1.55V 25mA LDO11VOUT LDO 12 Internal LDO 2.1V 2mA LDO12VOUT (Backup Battery Connection) LDO 13 Internal LDO 2.5V 20mA LDO13VOUT CLKOUT TEST Internal Power Source Management (test function only) Clocking and Auxiliary ADC Functions w PVDD Power Management PD, February 2012, Rev 4.0 2 WM8321 Production Data TYPICAL APPLICATIONS The WM8321 is designed as a system PMIC device that generates configurable DC supplies to power processors and associated peripherals within a system. The WM8321 provides four DC-DC synchronous buck (step-down) converters. Two of these can operate in dual mode, providing an increased current capability. Eleven LDO regulators provide a high degree of flexibility to provide power to multiple devices, with the capability to power-up and power-down different circuits independently. TM Two of the DC-DC buck converters incorporate Wolfson’s BuckWise technology specifically designed to handle rapid changes in load current; programmable slew rate DVS is also provided, as required by modern application processors. Selectable operating modes on all of the DC-DC converters allow each converter to be optimally configured for light, heavy or transient load conditions. Flexible operating configurations allow the converters to be tailored for minimum PCB area, maximum performance, or for maximum efficiency. The analogue LDOs provide low-noise outputs suitable for powering sensitive circuits such as RF / Wi-Fi / cellular handset applications. The WM8321 powers up the converters and LDOs according to a programmable sequence. A configurable ‘SLEEP’ state is also available, providing support for an alternate configuration, typically for low-power / standby operation. The power control sequences and many other parameters can be stored in an integrated user-configurable OTP (One-Time Programmable) memory or may be loaded from an external memory. The WM8321 supports the programming and verification of the integrated OTP memory. A backup battery supply can be connected to the WM8321 in order to maintain the Real Time Clock (RTC) in the absence of the primary supply. Programmable GPIO pins may be configured as hardware inputs for general use or for selecting different power management configurations. As outputs, the GPIOs can provide indications of the device status, or may be used as control signals for other power management circuits. The WM8321 also provides two LED drivers, which can be controlled manually or configured as status indicators for the OTP memory programmer or operating power state. w PD, February 2012, Rev 4.0 3 WM8321 Production Data TABLE OF CONTENTS DESCRIPTION ....................................................................................................... 1 FEATURES ............................................................................................................ 1 APPLICATIONS..................................................................................................... 1 BLOCK DIAGRAM ................................................................................................ 2 TYPICAL APPLICATIONS .................................................................................... 3 TABLE OF CONTENTS ......................................................................................... 4 1 PIN CONFIGURATION.................................................................................. 8 2 ORDERING INFORMATION ......................................................................... 8 3 PIN DESCRIPTION ....................................................................................... 9 4 THERMAL CHARACTERISTICS ................................................................ 13 5 ABSOLUTE MAXIMUM RATINGS.............................................................. 14 6 RECOMMENDED OPERATING CONDITIONS .......................................... 15 7 ELECTRICAL CHARACTERISTICS ........................................................... 16 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 DC-DC SYNCHRONOUS BUCK CONVERTERS ............................................... 16 LDO REGULATORS ............................................................................................ 17 RESET THRESHOLDS ....................................................................................... 22 REFERENCES .................................................................................................... 22 GENERAL PURPOSE INPUTS / OUTPUTS (GPIO)........................................... 23 DIGITAL INTERFACES ....................................................................................... 24 AUXILIARY ADC.................................................................................................. 24 SYSTEM STATUS LED DRIVERS ...................................................................... 24 8 TYPICAL POWER CONSUMPTION ........................................................... 25 9 TYPICAL PERFORMANCE DATA.............................................................. 26 9.1 DC-DC CONVERTERS ....................................................................................... 26 9.2 LDO REGULATORS ............................................................................................ 26 10 SIGNAL TIMING REQUIREMENTS ............................................................ 27 10.1 CONTROL INTERFACE ................................................................................... 27 11 DEVICE DESCRIPTION .............................................................................. 29 11.1 GENERAL DESCRIPTION ............................................................................... 29 11.2 POWER STATES ............................................................................................. 29 11.3 POWER STATE CONTROL ............................................................................. 31 11.4 POWER STATE INTERRUPTS ........................................................................ 36 11.5 POWER STATE GPIO INDICATION ................................................................ 36 11.6 ON PIN FUNCTION .......................................................................................... 37 11.7 RESET PIN FUNCTION ................................................................................... 38 12 CONTROL INTERFACE.............................................................................. 40 12.1 GENERAL DESCRIPTION ............................................................................... 40 12.2 2-WIRE (I2C) CONTROL MODE ...................................................................... 40 12.3 4-WIRE (SPI) CONTROL MODE ...................................................................... 43 12.4 REGISTER LOCKING ...................................................................................... 43 12.5 SOFTWARE RESET AND CHIP ID .................................................................. 44 12.6 SOFTWARE SCRATCH REGISTER ................................................................ 44 13 CLOCKING AND OSCILLATOR CONTROL .............................................. 45 13.1 GENERAL DESCRIPTION ............................................................................... 45 13.2 CRYSTAL OSCILLATOR INTERRUPTS ......................................................... 47 13.3 CRYSTAL OSCILLATOR CONNECTIONS ...................................................... 48 14 INSTANTCONFIG™ (ICE) AND OTP MEMORY CONTROL ...................... 49 w PD, February 2012, Rev 4.0 4 Production Data WM8321 14.1 14.2 14.3 GENERAL DESCRIPTION ............................................................................... 49 ICE AND OTP MEMORY DEFINITION ............................................................ 49 BOOTSTRAP (START-UP) FUNCTION ........................................................... 50 14.3.1 START-UP FROM OTP MEMORY ...................................................................................... 50 14.3.2 START-UP FROM ICE MEMORY (DEVELOPMENT MODE).............................................. 51 14.3.3 START-UP FROM DCRW REGISTER SETTINGS ............................................................. 51 14.3.4 EXTERNAL ICE MEMORY CONNECTION ......................................................................... 51 14.4 OTP / ICE MEMORY CONTROL ...................................................................... 52 14.4.1 ENTERING / EXITING THE PROGRAM STATE ................................................................. 53 14.4.2 OTP / ICE READ COMMAND .............................................................................................. 53 14.4.3 OTP WRITE COMMAND ..................................................................................................... 54 14.4.4 OTP VERIFY COMMAND .................................................................................................... 54 14.4.5 OTP FINALISE COMMAND ................................................................................................. 55 14.4.6 OTP CONTROL REGISTER ................................................................................................ 55 14.5 OTP / ICE INTERRUPTS ................................................................................. 57 14.6 DCRW MEMORY CONTENTS ......................................................................... 57 14.6.1 DCRW PAGE 0 .................................................................................................................... 57 14.6.2 DCRW PAGE 1 .................................................................................................................... 58 14.6.3 DCRW PAGE 2 .................................................................................................................... 58 14.6.4 DCRW PAGE 3 .................................................................................................................... 59 14.6.5 DCRW PAGE 4 .................................................................................................................... 61 15 POWER MANAGEMENT ............................................................................ 62 15.1 GENERAL DESCRIPTION ............................................................................... 62 15.2 DC-DC CONVERTER AND LDO REGULATOR ENABLE ............................... 62 15.3 TIMESLOT CONTROL AND HARDWARE ENABLE (GPIO) CONTROL ......... 63 15.4 OPERATING MODE CONTROL ...................................................................... 64 15.4.1 DC-DC SYNCHRONOUS BUCK CONVERTERS ................................................................ 64 15.4.2 LDO REGULATORS ............................................................................................................ 64 15.5 OUTPUT VOLTAGE CONTROL ...................................................................... 64 15.5.1 DC-DC SYNCHRONOUS BUCK CONVERTERS ................................................................ 64 15.5.2 LDO REGULATORS 1-10 .................................................................................................... 65 15.5.3 LDO REGULATOR 11 .......................................................................................................... 65 15.6 DC-DC SYNCHRONOUS BUCK CONVERTER CONTROL ............................ 65 15.6.1 DC-DC3 / DC-DC4 DUAL MODE ......................................................................................... 66 15.7 LDO REGULATOR CONTROL ........................................................................ 67 15.8 HARDWARE CONTROL (GPIO) ...................................................................... 67 15.9 FAULT PROTECTION ...................................................................................... 68 15.10 MONITORING AND FAULT REPORTING ....................................................... 68 15.11 POWER MANAGEMENT REGISTER DEFINITIONS ...................................... 69 15.11.1 DC-DC CONVERTER AND LDO REGULATOR ENABLE ................................................... 69 15.11.2 DC-DC SYNCHRONOUS BUCK CONVERTER CONTROL ................................................ 69 15.11.3 LDO REGULATOR CONTROL ............................................................................................ 76 15.11.4 EXTERNAL POWER ENABLE (EPE) CONTROL ................................................................ 84 15.11.5 MONITORING AND FAULT REPORTING ........................................................................... 85 15.12 POWER MANAGEMENT INTERRUPTS ......................................................... 86 15.13 POWER GOOD INDICATION .......................................................................... 87 15.14 DC-DC SYNCHRONOUS BUCK CONVERTER OPERATION ........................ 89 15.14.1 OVERVIEW .......................................................................................................................... 89 15.14.2 DC-DC SYNCHRONOUS BUCK CONVERTERS ................................................................ 89 15.15 LDO REGULATOR OPERATION ..................................................................... 93 15.15.1 OVERVIEW .......................................................................................................................... 93 15.15.2 LDO REGULATORS ............................................................................................................ 94 16 RESERVED ................................................................................................. 95 17 POWER SUPPLY CONTROL ..................................................................... 96 w PD, February 2012, Rev 4.0 5 WM8321 Production Data 17.1 GENERAL DESCRIPTION ............................................................................... 96 17.2 POWER PATH MANAGEMENT INTERRUPTS ............................................... 96 17.3 BACKUP POWER ............................................................................................ 96 18 AUXILIARY ADC ......................................................................................... 97 18.1 GENERAL DESCRIPTION ............................................................................... 97 18.2 AUXADC CONTROL ........................................................................................ 97 18.3 AUXADC READBACK ...................................................................................... 99 18.4 DIGITAL COMPARATORS ............................................................................. 100 18.5 AUXADC INTERRUPTS ................................................................................. 102 19 RESERVED ............................................................................................... 103 20 REAL-TIME CLOCK (RTC) ....................................................................... 104 20.1 GENERAL DESCRIPTION ............................................................................. 104 20.2 RTC CONTROL .............................................................................................. 104 20.3 RTC INTERRUPTS ........................................................................................ 106 20.4 DIGITAL RIGHTS MANAGEMENT ................................................................ 107 20.5 BACKUP MODE CLOCKING OPTIONS ........................................................ 107 21 GENERAL PURPOSE INPUTS / OUTPUTS (GPIO) ................................ 108 21.1 GENERAL DESCRIPTION ............................................................................. 108 21.2 GPIO FUNCTIONS ......................................................................................... 108 21.3 CONFIGURING GPIO PINS ........................................................................... 110 21.4 GPIO INTERRUPTS ....................................................................................... 114 22 SYSTEM STATUS LED DRIVERS ............................................................ 115 22.1 GENERAL DESCRIPTION ............................................................................. 115 22.2 LED DRIVER CONTROL................................................................................ 115 22.2.1 OTP PROGAM STATUS .................................................................................................... 115 22.2.2 POWER STATE STATUS .................................................................................................. 116 22.2.3 MANUAL MODE................................................................................................................. 116 22.3 LED DRIVER CONNECTIONS....................................................................... 118 23 INTERRUPT CONTROLLER .................................................................... 119 23.1 PRIMARY INTERRUPTS ............................................................................... 120 23.2 SECONDARY INTERRUPTS ......................................................................... 122 23.2.1 POWER STATE INTERRUPT ............................................................................................ 122 23.2.2 THERMAL INTERRUPTS .................................................................................................. 123 23.2.3 GPIO INTERRUPTS .......................................................................................................... 123 23.2.4 ON PIN INTERRUPTS ....................................................................................................... 123 23.2.5 WATCHDOG INTERRUPTS .............................................................................................. 124 23.2.6 AUXADC INTERRUPTS .................................................................................................... 124 23.2.7 POWER PATH MANAGEMENT INTERRUPTS ................................................................. 124 23.2.8 REAL TIME CLOCK AND CRYSTAL OSCILLATOR INTERRUPTS ................................. 125 23.2.9 OTP MEMORY INTERRUPTS ........................................................................................... 126 23.2.10 HIGH CURRENT INTERRUPTS ........................................................................................ 126 23.2.11 UNDERVOLTAGE INTERRUPTS ...................................................................................... 127 24 RESETS AND SUPPLY VOLTAGE MONITORING .................................. 128 24.1 RESETS ......................................................................................................... 128 24.2 HARDWARE RESET ...................................................................................... 130 24.3 SOFTWARE RESET ...................................................................................... 130 24.4 SUPPLY VOLTAGE MONITORING ............................................................... 132 25 WATCHDOG TIMER ................................................................................. 134 26 TEMPERATURE SENSING ...................................................................... 136 27 VOLTAGE AND CURRENT REFERENCES ............................................. 137 27.1 VOLTAGE REFERENCE (VREF) ................................................................... 137 27.2 CURRENT REFERENCE (IREF) ................................................................... 137 w PD, February 2012, Rev 4.0 6 Production Data 28 29 30 WM8321 REGISTER MAP OVERVIEW ................................................................... 138 REGISTER BITS BY ADDRESS ............................................................... 145 APPLICATIONS INFORMATION .............................................................. 246 30.1 30.2 30.3 TYPICAL CONNECTIONS ............................................................................. 246 VOLTAGE AND CURRENT REFERENCE COMPONENTS .......................... 247 DC-DC BUCK CONVERTER EXTERNAL COMPONENTS ........................... 247 30.3.1 DC-DC3 / DC-DC4 DUAL MODE ....................................................................................... 250 30.4 LDO REGULATOR EXTERNAL COMPONENTS .......................................... 251 30.5 PCB LAYOUT ................................................................................................. 252 31 PACKAGE DIAGRAM ............................................................................... 253 32 IMPORTANT NOTICE ............................................................................... 254 33 REVISION HISTORY ................................................................................. 255 w PD, February 2012, Rev 4.0 7 WM8321 1 Production Data PIN CONFIGURATION A1 A3 A2 B1 A4 B2 A5 B3 A7 A6 B4 B5 B6 B7 A8 B8 A9 A10 A11 B9 B10 B11 C1 D1 D2 D3 F2 F3 H2 H3 K2 K3 M2 M3 N2 N3 R2 R3 U2 U3 V3 V4 E1 F1 G1 H1 J1 K1 L1 EGP (Exposed Ground Paddle) M1 N1 P1 R1 T1 V1 U1 V2 W1 W2 W3 Y1 Y2 Y3 W4 Y4 W5 Y5 W6 Y6 W7 Y7 W8 Y8 W9 Y9 W10 Y10 W11 W12 Y11 Y12 Top View – WM8321 2 ORDERING INFORMATION ORDER CODE OTP TEMPERATURE RANGE (TA) PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE WM8321GEFL/V Unprogrammed -40C to +85C 81-lead QFN (8 x 8mm) MSL3 260C MSL3 260C MSL3 260C (Pb-free) WM8321GEFL/RV Unprogrammed -40C to +85C 81-lead QFN (8 x 8mm) (Pb-free, tape and reel) WM8321GEFLxxx/RV* Custom -40C to +85C 81-lead QFN (8 x 8mm) (Pb-free, tape and reel) ** Note: Reel quantity = 2200 * xxx = Unique OTP part number ** Custom OTP minimum order quantity 22,000. w PD, February 2012, Rev 4.0 8 WM8321 Production Data 3 PIN DESCRIPTION Notes: 1. Pins are sorted by functional groups. 2. The power domain associated with each pin is noted; VPMIC is the domain powered by LDO12 for the ‘always-on’ functions internal to the WM8321. 3. Note that an external level-shifter may be required when interfacing between different power domains. PIN NAME TYPE POWER DOMAIN DESCRIPTION Clocking and Real Time Clock Y12 XTO Analogue Output Y11 XTI Analogue Input W11 XOSCGND Supply VPMIC Crystal Drive Output Crystal Drive Input or 32.768kHz CMOS Clock Input Crystal Oscillator Ground CMOS Clock Output H1 CLKOUT Digital Output DBVDD Configurable Open Drain / CMOS mode. (External 4.7kΩ pull-up recommended in Open Drain mode.) General Purpose Input / Output and Auxiliary ADC D3 GPIO1 F2 GPIO2 Digital I/O F3 GPIO3 Digital I/O W4 GPIO4 Digital I/O Y4 GPIO5 Digital I/O W5 GPIO6 Digital I/O H2 GPIO7 Digital I/O H3 GPIO8 Digital I/O K3 GPIO9 Digital I/O Y5 GPIO10 Digital I/O Y6 GPIO11 Digital I/O W6 GPIO12 Digital I/O w GPIO Pin 1 Digital I/O Selectable pull-up/pull-down. DBVDD or VPMIC GPIO Pin 2 Selectable pull-up/pull-down. GPIO Pin 3 Selectable pull-up/pull-down. GPIO Pin 4 Selectable pull-up/pull-down. DBVDD or PVDD GPIO Pin 5 Selectable pull-up/pull-down. GPIO Pin 6 Selectable pull-up/pull-down. GPIO Pin 7 Selectable pull-up/pull-down. DBVDD or VPMIC GPIO Pin 8 Selectable pull-up/pull-down. GPIO Pin 9 Selectable pull-up/pull-down. GPIO Pin 10 / Auxiliary ADC input Selectable GPIO pull-up/pull-down. DBVDD or PVDD GPIO Pin 11 / Auxiliary ADC input Selectable GPIO pull-up/pull-down. GPIO Pin 12 / Auxiliary ADC input Selectable GPIO pull-up/pull-down. PD, February 2012, Rev 4.0 9 WM8321 PIN Production Data NAME TYPE POWER DOMAIN DESCRIPTION Processor Interface and IC Control W9 ¯¯¯ ON Digital Input VPMIC B10 RESET ¯¯¯¯¯¯ Digital I/O DBVDD A11 IRQ ¯¯¯ Digital Output DBVDD ON Request Pin (Internal pull-up) System Reset Input and Open Drain Output. (Internal pull-up) PMIC Interrupt Flag Output. Configurable Open Drain / CMOS mode. (Internal pull-up in Open Drain mode.) Primary Control Interface Mode Select: E1 CIFMODE Digital Input DBVDD 2 0 = I C Compatible Control Interface Mode 1 = SPI Compatible Control Interface Mode SPI Compatible Control Interface Mode 2 I C Compatible Control Interface Mode Control Interface Serial Data Out. D2 SDOUT1 Digital Output B9 SCLK1 Digital Input Open Drain output; external 4.7kΩ pull-up recommended. No Function Control Interface Serial Clock Control Interface Serial Clock DBVDD A9 SDA1 Control Interface Serial Data In Digital I/O Control Interface Serial Data Input and Open Drain Output. External 4.7kΩ pull-up recommended. (Output can extend above DBVDD domain.) 2 A10 Y10 CS ¯¯ SCLK2 Control Interface Chip Select Digital Input I C Address Select: 0 = 68h 1 = 6Ch Control Interface Serial Clock for external TM InstantConfig EEPROM (ICE) Digital I/O VPMIC (Internal pull-down) Control Interface Serial Data to/from external TM InstantConfig EEPROM (ICE) W10 SDA2 Digital I/O B11 DBVDD1 Supply Digital Buffer Supply F1 DBVDD2 Supply Digital Buffer Supply PROGVDD Supply High-voltage input for OTP programming. (Internal pull-down) OTP Memory Y3 w PD, February 2012, Rev 4.0 10 WM8321 Production Data PIN NAME TYPE POWER DOMAIN DESCRIPTION DC-DC Converters and LDO Regulators DC-DC1 Power Ground B7 DC1GND Supply A8 DC1FB Analogue Input A7 DC1LX Analogue I/O B8 DC1VDD Supply DC-DC1 Power Input (connect to PVDD system supply) B6 DC2GND Supply DC-DC2 Power Ground A5 DC2FB Analogue Input A6 DC2LX Analogue I/O B5 DC2VDD Supply DC-DC2 Power Input (connect to PVDD system supply) M1 DC3GND Supply DC-DC3 Power Ground J1 DC3FB Analogue Input L1 DC3LX Analogue I/O DC1VDD DC2VDD DC3VDD DC-DC1 Feedback Pin DC-DC1 Inductor Connection DC-DC2 Feedback Pin DC-DC2 Inductor Connection DC-DC3 Feedback Pin DC-DC3 Inductor Connection K1 DC3VDD Supply DC-DC3 Power Input (connect to PVDD system supply) N1 DC4GND Supply DC-DC4 Power Ground DC-DC4 Feedback Pin T1 DC4FB Analogue Input P1 DC4LX Analogue I/O R1 DC4VDD Supply DC-DC4 Power Input (connect to PVDD system supply) A3 LDO1_2VDD Supply LDO1 & LDO2 Power Input B2 LDO1VOUT Analogue Output LDO1VDD LDO1 Power Output B3 LDO2VOUT Analogue Output LDO2VDD LDO2 Power Output B4 LDO3VDD Supply A4 LDO3VOUT Analogue Output W3 LDO4VDD Supply Y2 LDO4VOUT Analogue Output Y1 LDO5VDD Supply W2 LDO5VOUT Analogue Output W1 LDO6VDD Supply V1 LDO6VOUT Analogue Output R3 LDO7_8VDD Supply N2 LDO7VOUT Analogue Output LDO7VDD R2 LDO8VOUT Analogue Output LDO8VDD M2 LDO9_10VDD Supply DC4VDD DC-DC4 Inductor Connection LDO3 Power Input LDO3VDD LDO3 Power Output LDO4 Power Input LDO4VDD LDO4 Power Output LDO5 Power Input LDO5VDD LDO5 Power Output LDO6VDD LDO6 Power Output LDO6 Power Input LDO7 & LDO8 Power Input LDO7 Power Output LDO8 Power Output LDO9 Power Input M3 LDO9VOUT Analogue Output LDO9VDD LDO9 Power Output N3 LDO10VOUT Analogue Output LDO10VDD LDO10 Power Output V3 LDO11VOUT Analogue Output PVDD Y8 LDO12VOUT Analogue I/O PVDD W7 LDO13VOUT1 Analogue I/O PVDD LDO13 (Internal INTVDD) Output; not for general use K2 LDO13VOUT2 Analogue I/O PVDD LDO13 - Connect to LDO13VOUT1 (W7) LDO11 (Alive) Power Output LDO12 (Internal VPMIC) Output; Backup battery supply input / output Voltage and Current References W8 VREFC Analogue I/O Y9 IREFR Analogue I/O VPMIC Voltage Reference capacitor connection point Current Reference resistor connection point System LED Drivers U3 LED1 Digital Output U2 LED2 Digital Output w PVDD Status LED Driver 1. Open Drain Output Status LED Driver 2. Open Drain Output PD, February 2012, Rev 4.0 11 WM8321 Production Data PIN NAME TYPE POWER DOMAIN DESCRIPTION U1 PVDD1 Supply Y7 PVDD2 Supply System VDD Supply V4 PVDD3 Supply System VDD Supply EGP Exposed Ground Paddle Analogue Ground System Power System VDD Supply Ground Miscellaneous A1, A2, B1, C1, D1, V2 DNC Do Not Connect G1, W12 TEST Test function (connect to GND) w PD, February 2012, Rev 4.0 12 WM8321 Production Data 4 THERMAL CHARACTERISTICS Thermal analysis must be performed in the intended application to prevent the WM8321 from exceeding maximum junction temperature. Several contributing factors affect thermal performance most notably the physical properties of the mechanical enclosure, location of the device on the PCB in relation to surrounding components and the number of PCB layers. Connecting the GND balls through thermal vias and into a large ground plane will aid heat extraction. Three main heat transfer paths exist to surrounding air: - Package top to air (convection and radiation). - Package bottom to PCB (convection and radiation). - Package leads to PCB (conduction). (Note that radiation is not normally significant at the moderate temperatures experienced in typical applications.) The temperature rise TR is given by TR = PD * ӨJA - PD is the power dissipated by the device. - ӨJA is the thermal resistance from the junction of the die to the ambient temperature and is therefore a measure of heat transfer from the die to surrounding air. - For WM8321, ӨJA = 24C/W - The quoted ӨJA is based on testing to the EIA/JEDEC-51-2 test environment (ie. 1ft box, still air, with specific PCB stack-up and tracking rules). Note that this is not guaranteed to reflect all typical end applications. 3 The junction temperature TJ is given by TJ = TA + TR - TA, is the ambient temperature. The worst case conditions are when the WM8321 is operating in a high ambient temperature, and under conditions which cause high power dissipation, such as the DC-DC converters operating at low supply voltage, high duty cycle and high output current. Under such conditions, it is possible that the heat dissipated could cause the maximum junction temperature of the device to be exceeded. Care must be taken to avoid this situation. An example calculation of the junction temperature is given below. - PD = 500mW (example figure) - ӨJA = 24C/W - TR = PD * ӨJA = 12C - TA = 85°C (example figure) - TJ = TA +TR = 97C The minimum and maximum operating junction temperatures for the WM8321 are quoted in Section 5. The maximum junction temperature is 125°C. Therefore, the junction temperature in the above example is within the operating limits of the WM8321. w PD, February 2012, Rev 4.0 13 WM8321 5 Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The WM8321 has been classified as MSL3. CONDITION MIN MAX OTP Programming Supply (PROGVDD) -0.3V 7.0V System supply (PVDD1, PVDD2, PVDD3) -0.3V 7.0V Input voltage for LDO regulators -0.3V 7.0V Input voltage for DC-DC converters -0.3V 7.0V Digital buffer supply (DBVDD1, DBVDD2) -0.3V 4.5V Voltage range for digital inputs -0.3V DBVDD + 0.3V Operating Temperature Range, TA -40C +85C Junction Temperature, TJ -40C +125C Thermal Impedance Junction to Ambient, θJA Storage temperature prior to soldering Storage temperature after soldering Soldering temperature (10 seconds) 24C/W o 30 C max / 60% RH max -65C +150C +260C Note: These ratings assume that all ground pins are at 0V. w PD, February 2012, Rev 4.0 14 WM8321 Production Data 6 RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL MIN System power source PVDD1, PVDD2, PVDD3 2.7 Digital buffer supply DBVDD1, DBVDD2 1.71 OTP Programming Supply (see note) PROGVDD 6.25 Ground LDO12VOUT Exposed Ground Paddle (EGP), DC1GND, DC2GND, DC3GND, DC4GND, XOSCGND TYP 6.5 MAX UNITS 5.5 V 3.6 V 6.75 V 3.3 V 0 V Note: The OTP Programming Supply PROGVDD should only be present when programming the OTP. At other times, this pin should be left unconnected. The LDO12VOUT must be overdriven by an external supply when programming the OTP. At other times, the voltage at this pin is driven by the internal circuits of the WM8321. w PD, February 2012, Rev 4.0 15 WM8321 7 Production Data ELECTRICAL CHARACTERISTICS 7.1 DC-DC SYNCHRONOUS BUCK CONVERTERS DC-DC1 and DC-DC2 (1) Unless otherwise noted: VIN = 3.8V, VOUT = 1.2V, MODE = FCCM , TJ = -40°C to +125°C; typical values are at TJ = 25°C PARAMETER Input Voltage SYMBOL Programmable Output Voltage VOUT VOUT Step Size VOUT_STEP VOUT Accuracy VOUT_ACC Undervoltage margin VUV Overvoltage margin Output Current P-channel VOV IOUT IP_LIM Current Limit Quiescent Current IQ Shutdown Current ISD P-channel RDSP On Resistance N-channel RDSN On Resistance Switching Frequency TEST CONDITIONS MIN MAX UNIT 2.7 5.5 V FSW = 2MHz 0.6 1.8 V FSW = 4MHz 0.6 1.4 VIN = 2.7V to 5.5V, IOUT = 0mA to 1250mA -2.5 VIN FSW TYP 12.5 0.6V ≤ VOUT < 0.9V 50 80 1.3V ≤ VOUT ≤ 1.8V 100 0.6V ≤ VOUT ≤ 1.8V % mV 0.9V ≤ VOUT < 1.3V (1) mV +2.5 100 mV (2) FCCM and Auto (CCM/DCM with PS ) Modes 0 1250 Hysteretic Mode 0 150 LDO Mode 0 mA 10 DCm_FREQ = 01 or 10 1850 DCm_FREQ = 11 2050 (1) IOUT = 0mA, FCCM and Auto (CCM/DCM with (2) PS ) Modes (excluding switching losses) 585 IOUT = 0mA, Hysteretic Mode 100 IOUT = 0mA, LDO Mode 25 DCm_ENA = 0 0.01 VIN = VGS = 3.8V, IDCmLX = 100mA 150 VIN = VGS = 3.8V, IDCmLX = -100mA 140 DCm_FREQ = 01 2 DCm_FREQ = 1X 4 mA A A m m MHz Notes: 1. Forced Continuous Conduction Mode 2. Continuous / Discontinuous Conduction with Pulse-Skipping Mode w PD, February 2012, Rev 4.0 16 WM8321 Production Data DC-DC3 and DC-DC4 (1) Unless otherwise noted: VIN = 3.8V, VOUT = 1.8V, MODE = FCCM , TJ = -40°C to +125°C; typical values are at TJ = 25°C PARAMETER Input Voltage SYMBOL Programmable Output Voltage VOUT VOUT Step Size VOUT_STEP VOUT Accuracy VOUT_ACC Undervoltage margin VUV Output Current P-channel TEST CONDITIONS IOUT MIN 0.85 (4) 0.85V ≤ VOUT ≤ 3.4V (1) FCCM and Auto (CCM/DCM with (2) PS ) Modes 3.4 V +4 0 1000 Dual mode operation (DC4_SLV=1) 0 800 (5) Hysteretic Mode, DCm_STNBY_LIM=01 0 100 (3) LDO Mode 0 10 1600 IOUT = 0mA, FCCM and Auto (CCM/DCM with (2) PS ) Modes (excluding switching losses) 330 IOUT = 0mA, Hysteretic Mode 110 IOUT = 0mA, LDO Mode 20 P-channel RDSP VIN = VGS = 3.8V, IDCmLX = 100mA RDSN VIN = VGS = 3.8V, IDCmLX = -100mA A A 0.01 m 165 On Resistance m 155 On Resistance FSW mA mA (1) DCm_ENA = 0 % mV Independent operation (DC4_SLV=0) ISD Switching Frequency V 50 Shutdown Current N-channel UNIT 5.5 mV -4 IP_LIM IQ MAX 25 VIN = 2.7V to 5.5V, IOUT = 0mA to 1000mA Current Limit Quiescent Current TYP 2.7 VIN MHz 2 Notes: 1. Forced Continuous Conduction Mode 2. Continuous / Discontinuous Conduction with Pulse-Skipping Mode 3. The maximum output current in Hysteretic mode can be adjusted using the DCm_STNBY_LIM registers 4. In FCCM mode, the minimum VOUT is 1.2V 5. In Dual mode operation, the ratings are ‘per converter’. The combined maximum output current is 1600mA 7.2 LDO REGULATORS LDO1 Unless otherwise noted: VIN = 3.8V, VOUT = 1.8V, TJ = -40°C to +125°C; Typical values are at TJ = +25ºC PARAMETER Input Voltage SYMBOL Programmable Output Voltage VOUT VOUT Step Size VOUT_STEP Output Current VOUT Accuracy TEST CONDITIONS VIN IOUT VOUT_ACC w MIN MAX UNIT 1.5 TYP 5.5 V 0.9 3.3 V VOUT = 0.9V to 1.6V 50 VOUT = 1.7V to 3.3V 100 mV Normal mode 0 300 Low power mode, LDOn_LP_MODE=0 0 50 Low power mode, LDOn_LP_MODE=1 0 20 ILOAD = 1mA -3 +3 mA % PD, February 2012, Rev 4.0 17 WM8321 Production Data PARAMETER SYMBOL Line Regulation VOUT LINE TEST CONDITIONS MIN VIN = (VOUT + 0.5) to 5.5V, ILOAD = 150mA Note that VIN must be >= 1.5V TYP MAX UNIT 0.1 %/V Load Regulation VOUT LOAD ILOAD =1mA to 300mA 0.011 %/mA Dropout Voltage VIN - VOUT ILOAD =150mA, VOUT > 2.7V 250 mV ILOAD =150mA, VOUT 1.8V to 2.7V 300 ILOAD =150mA, VOUT < 1.8V 500 Undervoltage level Quiescent Current VOUT IQ VOUT Falling 88 % Normal mode, no load 30 A Low power mode, LDOn_LP_MODE=0, no load 10 Low power mode, LDOn_LP_MODE=1, no load ILOAD = 1mA to 300mA Power Supply Rejection Ratio PSRR On Resistance (Switch mode) RDSON Current Limit (Switch mode) Start-up time Shutdown time 5 IQ (no load) + 1% of load ILOAD = 150mA, <= 1kHz 53 ILOAD = 150mA, 10kHz 53 dB ILOAD = 150mA, 100kHz 32 VIN = 1.5V, ILOAD = 100mA 1.5 VIN = 1.8V, ILOAD = 100mA 1.2 VIN = 2.5V, ILOAD = 100mA 0.85 VIN = 3.3V, ILOAD = 100mA 0.7 VOUT = 0V 600 tstart_up No load, Output cap 2.2 µF, 90% of VOUT 10 tshut_down No load, Output cap 2.2 µF, 10% of VOUT ICL mA s 10 ms LDO2, LDO3 Unless otherwise noted: VIN = 3.8V, VOUT = 1.8V, TJ = -40°C to +125°C; Typical values are at TJ = +25ºC PARAMETER Input Voltage SYMBOL TEST CONDITIONS VIN Programmable Output Voltage VOUT VOUT Step Size VOUT_STEP MIN MAX UNIT 1.5 5.5 V 0.9 3.3 V VOUT = 0.9V to 1.6V 50 VOUT = 1.7V to 3.3V Output Current IOUT TYP mV 100 Normal mode 0 200 Low power mode, LDOn_LP_MODE=0 0 50 Low power mode, LDOn_LP_MODE=1 0 20 VOUT Accuracy VOUT_ACC ILOAD = 1mA -3 +3 Line Regulation VOUT LINE VIN = (VOUT + 0.5) to 5.5V, ILOAD = 100mA Note that VIN must be >= 1.5V mA % 0.1 %/V Load Regulation VOUT LOAD ILOAD =1mA to 200mA 0.011 %/mA Dropout Voltage VIN - VOUT ILOAD =100mA, VOUT > 2.7V 200 mV ILOAD =100mA, VOUT 1.8V to 2.7V 250 ILOAD =100mA, VOUT < 1.8V 400 Undervoltage level Quiescent Current VOUT IQ VOUT Falling PSRR On Resistance RDSON w % A Normal mode, no load 30 Low power mode, LDOn_LP_MODE=0, no load 10 Low power mode, LDOn_LP_MODE=1, no load 5 ILOAD = 1mA to 200mA Power Supply Rejection Ratio 88 IQ (no load) + 1% of load ILOAD = 100mA, <= 1kHz 55 ILOAD = 100mA, 10kHz 55 dB ILOAD = 100mA, 100kHz 32 VIN = 1.5V, ILOAD = 100mA 1.5 PD, February 2012, Rev 4.0 18 WM8321 Production Data PARAMETER (Switch mode) Current Limit (Switch mode) Start-up time Shutdown time SYMBOL TEST CONDITIONS MIN TYP VIN = 1.8V, ILOAD = 100mA 1.2 VIN = 2.5V, ILOAD = 100mA 0.85 MAX UNIT VIN = 3.3V, ILOAD = 100mA 0.7 VOUT = 0V 400 mA tstart_up No load, Output cap 2.2 µF, 90% of VOUT 10 s tshut_down No load, Output cap 2.2 µF, 10% of VOUT ICL 10 ms MAX UNIT 1.5 5.5 V 0.9 3.3 V LDO4, LDO5, LDO6 Unless otherwise noted: VIN = 3.8V, VOUT = 1.8V, TJ = -40°C to +125°C; Typical values are at TJ = +25ºC. PARAMETER Input Voltage SYMBOL VIN Programmable Output Voltage VOUT VOUT Step Size VOUT_STEP Output Current TEST CONDITIONS IOUT MIN TYP VOUT = 0.9V to 1.6V 50 VOUT = 1.7V to 3.3V 100 mV Normal mode 0 100 Low power mode, LDOn_LP_MODE=0 0 50 Low power mode, LDOn_LP_MODE=1 0 20 VOUT Accuracy VOUT_ACC ILOAD = 1mA -3 +3 Line Regulation VOUT LINE VIN = (VOUT + 0.5) to 5.5V, ILOAD = 50mA Note that VIN must be >= 1.5V mA % 0.1 %/V Load Regulation VOUT LOAD ILOAD =1mA to 100mA 0.022 %/mA Dropout Voltage VIN - VOUT ILOAD =100mA, VOUT > 2.7V 200 mV ILOAD =100mA, VOUT 1.8V to 2.7V 250 ILOAD =100mA, VOUT < 1.8V 400 Undervoltage level Quiescent Current VOUT IQ VOUT Falling 88 % Normal mode, no load 30 A Low power mode, LDOn_LP_MODE=0, no load 10 Low power mode, LDOn_LP_MODE=1, no load Power Supply Rejection Ratio On Resistance (Switch mode) Current Limit (Switch mode) Start-up time Shutdown time PSRR RDSON 5 ILOAD = 1mA to 100mA IQ (no load) + 1% of load ILOAD = 50mA, <= 1kHz 55 ILOAD = 50mA, 10kHz 55 dB ILOAD = 50mA, 100kHz 32 VIN = 1.5V, ILOAD = 100mA 3.2 VIN = 1.8V, ILOAD = 100mA 2.1 VIN = 2.5V, ILOAD = 100mA 1.35 VIN = 3.3V, ILOAD = 100mA 1.1 VOUT = 0V 230 tstart_up No load, Output cap 2.2 µF, 90% of VOUT 10 tshut_down No load, Output cap 2.2 µF, 10% of VOUT ICL mA s 10 ms LDO7, LDO8 Unless otherwise noted: VIN = 3.8V, VOUT = 1.8V, TJ = -40°C to +125°C; Typical values are at TJ = +25ºC PARAMETER Input Voltage SYMBOL Programmable Output Voltage VOUT VOUT Step Size VOUT_STEP Output Current TEST CONDITIONS VIN IOUT w MAX UNIT 1.71 MIN TYP 5.5 V 1.0 3.5 V VOUT = 1.0V to 1.6V 50 VOUT = 1.7V to 3.5V 100 Normal mode 0 mV 200 mA PD, February 2012, Rev 4.0 19 WM8321 PARAMETER Production Data SYMBOL TEST CONDITIONS Low Power mode VOUT Accuracy VOUT_ACC ILOAD = 1mA Line Regulation VOUT LINE VIN = (VOUT + 0.5) to 5.5V, ILOAD = 100mA MIN TYP MAX 0 50 -2.5 +2.5 Note that VIN must be >= 1.71V UNIT % 0.025 %/V Load Regulation VOUT LOAD ILOAD =1mA to 200mA 0.003 %/mA Dropout Voltage VIN - VOUT ILOAD =100mA, VOUT =1.8V 95 mV ILOAD =100mA, VOUT =2.5V 65 ILOAD =100mA, VOUT =3.3V 60 Undervoltage level Quiescent Current VOUT IQ VOUT Falling 93 % Normal mode, no load 110 A Low Power mode, no load 70 ILOAD = 1mA to 200mA Power Supply Rejection Ratio PSRR Output noise voltage VOUT On Resistance (Switch mode) RDSON Current Limit (Switch mode) Start-up time Shutdown time IQ (no load) + 0.1% of load ILOAD = 100mA, <= 1kHz 70 ILOAD = 100mA, 10kHz 67 ILOAD = 100mA, 100kHz 48 f=10Hz to 100kHz; VOUT=2.8V, ILOAD = 1mA 30 f=10Hz to 100kHz; VOUT=2.8V, ILOAD = 10mA 32 dB VRMS f=10Hz to 100kHz; VOUT=2.8V, ILOAD = 100mA 32 VIN = 1.71V, ILOAD = 100mA 550 VIN = 1.8V, ILOAD = 100mA 500 VIN = 2.5V, ILOAD = 100mA 330 VIN = 3.5V, ILOAD = 100mA 250 VOUT = 0V 320 tstart_up No load, Output cap 4.7 µF, 90% of VOUT 50 tshut_down No load, Output cap 4.7 µF, 10% of VOUT ICL m mA s 10 ms LDO9, LDO10 Unless otherwise noted: VIN = 3.8V, VOUT = 1.8V, TJ = -40°C to +125°C; Typical values are at TJ = +25ºC PARAMETER Input Voltage SYMBOL Programmable Output Voltage VOUT VOUT Step Size VOUT_STEP Output Current TEST CONDITIONS VIN IOUT VOUT Accuracy VOUT_ACC Line Regulation VOUT LINE MAX UNIT 1.71 MIN TYP 5.5 V 1.0 3.5 V VOUT = 1.0V to 1.6V 50 VOUT = 1.7V to 3.5V 100 mV Normal mode 0 150 Low Power mode 0 50 -2.5 +2.5 ILOAD = 1mA VIN = (VOUT + 0.5) to 5.5V, ILOAD = 75mA Note that VIN must be >= 1.71V mA % 0.025 %/V Load Regulation VOUT LOAD ILOAD =1mA to 150mA 0.004 %/mA Dropout Voltage VIN - VOUT ILOAD =100mA, VOUT =1.8V 135 mV ILOAD =100mA, VOUT =2.5V 100 ILOAD =100mA, VOUT =3.3V 90 Undervoltage level Quiescent Current Power Supply Rejection Ratio VOUT IQ PSRR w VOUT Falling % 93 Normal mode, no load 110 Low Power mode, no load 70 ILOAD = 1mA to 150mA IQ (no load) + 0.1% of load ILOAD = 75mA, <= 1kHz 73 ILOAD = 75mA, 10kHz 69 A dB PD, February 2012, Rev 4.0 20 WM8321 Production Data PARAMETER SYMBOL Output noise voltage VOUT On Resistance (Switch mode) RDSON TEST CONDITIONS MIN 49 f=10Hz to 100kHz; VOUT=2.8V, ILOAD = 1mA 30 f=10Hz to 100kHz; VOUT=2.8V, ILOAD = 10mA 32 f=10Hz to 100kHz; VOUT=2.8V, ILOAD = 100mA Current Limit (Switch mode) Start-up time Shutdown time TYP ILOAD = 75mA, 100kHz UNIT VRMS 32 VIN = 1.71V, ILOAD = 100mA 1000 VIN = 1.8V, ILOAD = 100mA 930 VIN = 2.5V, ILOAD = 100mA 610 VIN = 3.5V, ILOAD = 100mA 430 VOUT = 0V 250 tstart_up No load, Output cap 4.7 µF, 90% of VOUT 70 tshut_down No load, Output cap 4.7 µF, 10% of VOUT ICL MAX m mA s 10 ms MAX UNIT 1.55 V 10 mA LDO11 Unless otherwise noted: VIN = 3.8V, VOUT = 1.2V, TJ = -40°C to +125°C; Typical values are at TJ = +25ºC PARAMETER SYMBOL TEST CONDITIONS MIN TYP Programmable Output Voltage VOUT VOUT Step Size VOUT_STEP Output Current IOUT VOUT Accuracy VOUT Line Regulation VOUT LINE VIN = 2.7 to 5.5V; ILOAD = 1mA 0.4 %/V Load Regulation VOUT LOAD ILOAD = 100µA to 10mA 0.2 %/mA No load 2.5 A tstart_up No load, Output cap 0.1 µF, 90% of VOUT 0.3 1 ms tshut_down No load, Output cap 0.1 µF, 10% of VOUT 0.3 1 ms Quiescent Current Start-up time Shutdown time IQ w 0.8 50 PVDD < 3.1V mV 0 PVDD ≥ 3.1V 0 25 VIN = 2.7 to 5.5V ; ILOAD = 100µA -4 +4 % PD, February 2012, Rev 4.0 21 WM8321 7.3 Production Data RESET THRESHOLDS Unless otherwise noted: TJ = -40°C to +125°C; Typical values are at TJ = +25ºC PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Power On Reset Power on Reset threshold VPMIC (LDO12VOUT) voltage at which device transitions between NO POWER and BACKUP states Power on Reset hysteresis VPOR, DE- VPMIC rising 1.18 V VPMIC falling 1.08 V 100 mV VPMIC rising 1.89 V VPMIC falling 1.80 V 90 mV 2.7 V ASSERT VPOR, ASSERT VPOR, HYST Device Reset Control Device Reset threshold VPMIC (LDO12VOUT) voltage at which device transitions between BACKUP and OFF states Device Reset hysteresis VRES, DEASSERT VRES, ASSERT VRES, HYST Device Shutdown Shutdown threshold VSHUTDOWN PVDD falling VSYSLO PVDD falling, PVDD voltage at which the device forces an OFF transition SYSLO threshold accuracy SYSOK threshold accuracy -3 +3 % -3 +3 % VSYSLO set by SYSLO_THR (2.8V to 3.5V) PVDD voltage at which SYSLO is asserted. VSYSOK PVDD rising, VSYSOK set by SYSOK_THR (2.8V to 3.5V) PVDD voltage at which SYSOK is asserted. Note the SYSOK hysteresis margin (VSYSOK, HYST) is added to SYSOK_THR. SYSOK hysteresis 7.4 40 VSYSOK, HYST mV REFERENCES Unless otherwise noted: TJ = +25ºC PARAMETER SYMBOL Voltage Reference VVREFC Current Reference VIREFR w TEST CONDITIONS 100k to GND MIN TYP MAX UNIT 0.8 V 0.5 V PD, February 2012, Rev 4.0 22 WM8321 Production Data 7.5 GENERAL PURPOSE INPUTS / OUTPUTS (GPIO) Unless otherwise noted: TJ = -40°C to +125°C; Typical values are at TJ = +25ºC PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT GPIO1, GPIO2, GPIO3, GPIO7, GPIO8, GPIO9 Input HIGH Level VIH Input LOW Level VIL Output HIGH Level VOH IOH = 1mA Output LOW Level VOL IOL = -1mA Pull-up resistance to VDD RPU Pull-down resistance RPD GPn_PWR_DOM=0 and DBVDD=1.8V 0.75 x VDD V 0.25 x VDD 0.8 x VDD V V 0.2 x VDD V 180 kΩ 180 kΩ or GPn_PWR_DOM=1 GPIO4, GPIO5, GPIO6, GPIO10, GPIO11, GPIO12 Input HIGH Level VIH Input LOW Level VIL Output HIGH Level VOH IOH = 1mA Output LOW Level VOL IOL = -1mA Pull-up resistance to VDD RPU Pull-down resistance RPD GPn_PWR_DOM=0 and DBVDD=1.8V 0.85 x VDD V 0.2 x VDD 0.75 x VDD V V 0.2 x VDD V 180 kΩ 180 kΩ or GPn_PWR_DOM=1 and PVDD=3.8V Notes: 1. ‘VDD’ is the voltage of the applicable power domain for each pin (selected by the corresponding GPn_PWR_DOM register). 2. Pull-up / pull-down resistance only applies when enabled using the GPn_PULL registers. 3. Pull-up / pull-down resistors are disabled when the GPIO pin is tri-stated. 4. Pull-up / pull-down resistance may change with the applicable power domain (as selected by GPn_PWR_DOM). w PD, February 2012, Rev 4.0 23 WM8321 7.6 Production Data DIGITAL INTERFACES Unless otherwise noted: TJ = -40°C to +125°C; Typical values are at TJ = +25ºC PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT ON ¯¯ , RESET ¯¯¯¯¯¯, IRQ ¯¯¯, CIFMODE, SDOUT1, SCLK1, SDA1, CS ¯¯ , SCLK2, SDA2 Input HIGH Level VIH Input LOW Level VIL Output HIGH Level VOH IOH = 1mA Output LOW Level VOL IOL = -1mA 0.75 x VDD V 0.2 x VDD 0.8 x VDD V V 0.2 x VDD V ‘VDD’ is the voltage of the applicable power domain for each pin, as defined in Section 3. ON pin pull-up resistance RPU RESET pin pull-up resistance RPU IRQ pin pull-up resistance RPU 140 kΩ DBVDD=1.8V 180 kΩ DBVDD=3.6V 85 DBVDD=1.8V 180 DBVDD=3.6V 85 kΩ SCLK2 pin pull-down resistance RPD 100 kΩ SDA2 pin pull-down resistance RPD 100 kΩ 7.7 AUXILIARY ADC Unless otherwise noted: TJ = +25ºC PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX Input resistance RGPIO10, 11, 12 During measurement Input voltage range VGPIO10, 11, 12 GPn_PWR_DOM = 0 0 VDBVDD GPn_PWR_DOM = 1 0 VPVDD Input capacitance 400 CGPIO10, 11, 12 AUXADC Resolution AUXADC Conversion Time 7.8 kΩ Input voltage = 3V V 2 pF 12 bits 39 AUXADC accuracy UNIT µs -2.5 +2.5 % MAX UNIT SYSTEM STATUS LED DRIVERS Unless otherwise noted: TJ = +25ºC PARAMETER SYMBOL TEST CONDITIONS MIN TYP LED1 and LED2 Sink current w VLED1/2 = 1V 10 mA PD, February 2012, Rev 4.0 24 Production Data 8 WM8321 TYPICAL POWER CONSUMPTION Data to follow w PD, February 2012, Rev 4.0 25 WM8321 9 9.1 Production Data TYPICAL PERFORMANCE DATA DC-DC CONVERTERS Data to follow 9.2 LDO REGULATORS Data to follow w PD, February 2012, Rev 4.0 26 WM8321 Production Data 10 SIGNAL TIMING REQUIREMENTS 10.1 CONTROL INTERFACE Figure 1 Control Interface Timing - 2-wire (I2C) Control Mode Test Conditions TJ = -40ºC to +125 ºC unless otherwise stated. PARAMETER SYMBOL SCLK1 Frequency MIN 0 TYP MAX UNIT 400 kHz SCLK1 Low Pulse-Width t1 1300 ns SCLK1 High Pulse-Width t2 600 ns Hold Time (Start Condition) t3 600 ns Setup Time (Start Condition) t4 600 ns Data Setup Time t5 100 SDA1, SCLK1 Rise Time t6 SDA1, SCLK1 Fall Time t7 Setup Time (Stop Condition) t8 Data Hold Time t9 Pulse width of spikes that will be suppressed tps w ns 300 ns 300 ns 900 ns 5 ns 600 0 ns PD, February 2012, Rev 4.0 27 WM8321 Production Data Figure 2 Control Interface Timing - 4-wire (SPI) Control Mode (Write Cycle) Figure 3 Control Interface Timing - 4-wire (SPI) Control Mode (Read Cycle) Test Conditions TJ = -40ºC to +125 ºC unless otherwise stated. PARAMETER SYMBOL MIN CS ¯¯ falling edge to SCLK1 rising edge tCSU 40 TYP MAX UNIT ns SCLK1 falling edge to CS ¯¯ rising edge tCHO 10 ns SCLK1 pulse cycle time tSCY 200 ns SCLK1 pulse width low tSCL 80 ns SCLK1 pulse width high tSCH 80 ns SDA1 to SCLK1 set-up time tDSU 40 ns SDA1 to SCLK1 hold time tDHO 10 Pulse width of spikes that will be suppressed tps 0 SCLK1 falling edge to SDOUT1 transition tDL ns 5 ns 40 ns The CS ¯¯ pin must be held high for at least 1s after every register write operation in SPI mode. w PD, February 2012, Rev 4.0 28 WM8321 Production Data 11 DEVICE DESCRIPTION 11.1 GENERAL DESCRIPTION The WM8321 is a multi-purpose Power Management device with a comprehensive range of features. The WM8321 provides 4 DC-DC synchronous buck converters and 11 LDO regulators which are all programmable to application-specific requirements. The on-board oscillator and two additional LDOs support the clocking and control functions for the DC-DC converters and other core functions. The WM8321 provides a 32.768kHz crystal oscillator and secure Real Time Clock (SRTC). An auxiliary ADC is included, for measurement of external voltages. Other features include flexible GPIO capability, and LED outputs for system status indications. Under typical operating conditions, the device is powered up and shut down under the control of the ON ¯¯ pin. The device executes a programmable sequence of enabling or disabling the DC-DC converters, LDOs and other functions when commanded to power up or shut down respectively. An alternate device state (SLEEP power state) is provided, in which selected functions may be separately configured for a low-power or other operating condition. The configuration of the normal operating state may be programmed into an integrated OTP non-volatile memory. If desired, the OTP memory can be programmed during device manufacture in accordance with the user’s specification. See Section 14 for details of the OTP and associated bootstrap configuration functions. In the absence of a main power supply, the WM8321 automatically reverts to a backup state, under which a minimal functionality is maintained to enable a smooth return to normal operation when the supply is restored. With a backup battery present, the RTC is updated in the backup state, allowing the main battery to be depleted or changed without loss of RTC function. Without a backup battery, a small capacitor is sufficient to maintain the RTC (unclocked) for up to 5 minutes. 11.2 POWER STATES The WM8321 has 6 main power states, which are described below. Different levels of functionality are associated with each of the power states. Some of the state transitions are made autonomously by the WM8321 (eg. transitions to/from BACKUP are scheduled according to the available power supply conditions). Other transitions are initiated as a result of instructions issued over the Control Interface or as a result of software functions (eg. Watchdog timer) or hardware functions such as the ON ¯¯ pin. The valid transitions and the associated conditions are detailed below. NO POWER - This is the device state when no power is available. All functions are disabled and all register data is lost. OFF - This is the device state when power is available but the device is switched off. The RTC is enabled and the register map contents are maintained. The RESET ¯¯¯¯¯¯ pin is pulled low in this state. LDO11 may optionally be enabled in this state; all other DC-DCs and LDOs are disabled (apart from LDO12, which supports internal functions). ON - This is the normal operating state when the device is switched on. All device functions are available in this state. SLEEP - This is a user-configurable operating state which is intended for a low-power operating condition. Selected functions may be enabled, disabled or re-configured according to the user’s requirements. A programmable configuration sequence for the DC-DCs and LDOs is executed on transition to/from SLEEP mode. BACKUP - This is the operating state when the PVDD power supply is below the reset threshold of the device. Typically, this means that the PVDD supply has been removed. All DC-DC converters and LDO regulators are disabled in this state. The RTC and oscillator and a ‘software scratch’ memory area can be maintained from the backup supply (if available) in this state. All other functions and registers are reset in BACKUP. (Note that, for power saving, an ‘unclocked’ mode, in which the RTC is held constant, may be selected if required.) PROGRAM - This is a special operating state which is used for programming the integrated OTP memory with the device configuration data. The settings stored in the OTP define the device configuration in the ON state, and also the time/sequencing data associated with ON/OFF power state transitions. See Section 14 for details of the OTP features. w PD, February 2012, Rev 4.0 29 WM8321 Production Data The valid power state transitions are illustrated in Figure 4. Figure 4 Power States and Transitions State transitions to/from the NO POWER state are controlled automatically by the internal supply (VPMIC) voltage generated by LDO12. The device is in the NO POWER state when this voltage is below the Power-On Reset (POR) threshold. See Section 24 for more details on Power-On Reset. State transitions to/from the BACKUP state are controlled automatically by the internal supply (VPMIC) voltage generated by LDO12. The device is in the BACKUP state when this voltage is below the Device Reset threshold. See Section 24 for more details on Resets. State transitions to/from the PROGRAM state are required to follow specific control sequences. See Section 14 for details of the PROGRAM functions. The remaining transitions between the OFF, ON and SLEEP states may be initiated by a number of different mechanisms - some of them automatic, some of them user-controlled. Transitions between these states are time-controlled sequences of events. These are the OFF, ON, SLEEP and WAKE sequences shown in Figure 4. These transitions are programmable, using data stored in the TM integrated OTP memory or else data loaded from an external InstantConfig EEPROM (ICE) memory. See Section 14 for details. w PD, February 2012, Rev 4.0 30 WM8321 Production Data Note that a transition from the SLEEP state to the OFF state is not a controlled transition. If an ‘OFF’ event occurs whilst in the SLEEP state, then the WM8321 will select the OFF state, but all the enabled converters and regulators will be disabled immediately; the time-controlled sequence is not implemented in this case. See Section 11.3 for details of the WM8321 ‘OFF’ events. The current power state of the WM8321 can be read from the MAIN_STATE register field. A restricted definition of this field is shown in Table 1. Note that other values of MAIN_STATE are defined for transition states, but it is recommended that only the values quoted below should be used to confirm power state transitions. A power state transition to the BACKUP, SLEEP, ON or OFF state is indicated by the Interrupt bits described in Section 11.4. ADDRESS R16397 (400Dh) BIT 4:0 LABEL MAIN_STATE [4:0] System Status DEFAULT 0_0000 DESCRIPTION Main State Machine condition 0_0000 = OFF 0_1011 = PROGRAM 1_1100 = SLEEP 1_1111 = ACTIVE (ON) Table 1 Power State Readback 11.3 POWER STATE CONTROL The OFF, ON, SLEEP and WAKE sequences are initiated by many different conditions. When such a condition occurs, the WM8321 schedules a series of 5 timeslots, enabling a sequence of enable/disable events to be controlled. The nominal duration of the timeslots is fixed at 2ms, though this may be extended if any selected circuit has not started up within this time, as described later in this section. The OFF, SLEEP and WAKE sequences commence after a programmable delay set by PWRSTATE_DLY. This allows a host processor to request a WM8321 state transition and then complete other tasks before the transition actually occurs. The ON sequence is the transition from OFF to ON power states. Each LDO and each DC-DC Converter may be associated with any one of the available timeslots in the ON sequence. This determines the time, within the sequence, at which that DC-DC Converter or LDO will be enabled following an ‘ON’ event. The clock output (CLKOUT) and GPIO pins configured as External Power Enable (EPE) outputs can also be associated with any one of the available timeslots in the ON sequence. The EPE function is a logic output that may be used to control external circuits, including external DC-DC converters. An example ‘ON’ state transition sequence is illustrated in Figure 5. Each of the DC-DC Converters and LDO regulators can be individually assigned to one of the five timeslots (shown as T1, T2, T3, T4, T5), providing total flexibility in the power sequence. Figure 5 Example Control Sequence for ‘ON’ State Transition w PD, February 2012, Rev 4.0 31 WM8321 Production Data The possible ‘ON’ events that may trigger the ON sequence are listed in Table 3. The ON sequence is only permitted when the supply voltage PVDD exceeds a programmable threshold SYSOK. See Section 24 for details of PVDD voltage monitoring. The OFF sequence is the reverse of the ON sequence. Each DC-DC Converter, LDO Regulator or GPIO output that is associated with a timeslot in the ON sequence is switched off in the reverse sequence following an ‘OFF’ event. If CLKOUT is assigned to a timeslot in the ON sequence, then this is disabled in the reverse (OFF) sequence also. The possible ‘OFF’ events are listed in Table 3. Note that it is possible to modify the OFF sequence by writing to the associated registers in the ON power state if required; this allows the OFF sequence to be independent of the ON sequence. The SLEEP sequence is the transition from ON to SLEEP power states. Each LDO and each DC-DC Converter may be associated with any one of the available timeslots in the SLEEP sequence. This determines the time, within the sequence, at which that DC Converter or LDO will be disabled following a ‘SLEEP’ event. The clock output (CLKOUT) and GPIO pins configured as External Power Enable (EPE) outputs can also be associated with any one of the available timeslots in the SLEEP sequence. The possible ‘SLEEP’ events are listed in Table 3. The WAKE sequence is the reverse of the SLEEP sequence. Each DC-DC Converter, LDO Regulator or GPIO output that is associated with a timeslot in the SLEEP sequence is switched on in the reverse sequence following a ‘WAKE’ event. If CLKOUT is assigned to a timeslot in the SLEEP sequence, then this is disabled in the reverse (WAKE) sequence also. The possible ‘WAKE’ events are listed in Table 3. Note that it is possible to modify the WAKE sequence by writing to the associated registers in the SLEEP power state if required; this allows the WAKE sequence to be independent of the SLEEP sequence. Any DC-DC Converter or LDO that is not associated with one of the 5 timeslots in the ON sequence may, instead, be configured to be hardware controlled via a GPIO pin configured as one of the Hardware Enable inputs. See Section 21 for details of the GPIO functions. Any DC-DC Converter or LDO that is not under Hardware control may be enabled or disabled under Software control in the ON state, regardless of whether it is associated with any timeslot in the ON sequence. When a valid OFF event occurs, any DC-DC Converter or LDO which is not allocated a timeslot in the ON sequence is disabled immediately. This includes any DC-DC Converter or LDO which is under GPIO (Hardware Enable) control. The only exception is LDO11 which may, optionally, be configured to be enabled in the OFF state. The WM8321 monitors the DC-DC Converters and LDOs during the ON sequence to ensure that the required circuits have powered up successfully before proceeding to the next timeslot. The nominal timeslot durations are extended if necessary in order to wait for the selected DC-DC Converters or LDOs to power up. If the ON sequence has not completed within 2 seconds of starting the transition, then a Power Sequence Failure has occurred, resulting in the OFF state being forced. The most recent ON or WAKE event can be determined by reading the bits in the “ON Source” register, R400Eh. The most recent OFF event can be determined by reading the bits in the “OFF Source” register, R400Fh. The “ON Source” register is updated when a new ON event occurs. The “OFF Source” register is updated when a new OFF event occurs. Note that some Reset conditions (see Section 24) result in an OFF transition followed by an ON transition; these events are recorded as Reset events in the “ON Source” register. w PD, February 2012, Rev 4.0 32 WM8321 Production Data The ON Source and OFF Source register fields are defined in Table 2. ADDRESS R16387 (4003h) BIT 15 LABEL CHIP_ON DEFAULT 0 Power State DESCRIPTION Indicates whether the system is ON or OFF. 0 = OFF 1 = ON (or SLEEP) OFF can be commanded by writing CHIP_ON = 0. Note that writing CHIP_ON = 1 is not a valid ‘ON’ event, and will not trigger an ON transition. 14 CHIP_SLP 0 Indicates whether the system is in the SLEEP state. 0 = Not in SLEEP 1 = SLEEP WAKE can be commanded by writing CHIP_SLP = 0. SLEEP can be commanded by writing CHIP_SLP = 1. 11:10 PWRSTATE_DLY 10 Power State transition delay 00 = No delay 01 = No delay 10 = 1ms 11 = 10ms R16398 (400Eh) 15 ON_TRANS 0 Most recent ON/WAKE event type 0 = WAKE transition ON Source 1 = ON transition 11 ON_GPIO 0 Most recent ON/WAKE event type 0 = Not caused by GPIO input 1 = Caused by GPIO input 10 ON_SYSLO 0 Most recent WAKE event type 0 = Not caused by PVDD 1 = Caused by SYSLO threshold. Note that the SYSLO threshold cannot trigger an ON event. 7 ON_WDOG_TO 0 Most recent WAKE event type 0 = Not caused by Watchdog timer 1 = Caused by Watchdog timer 6 ON_SW_REQ 0 Most recent WAKE event type 0 = Not caused by software WAKE 1 = Caused by software WAKE command (CHIP_SLP = 0) 5 ON_RTC_ALM 0 Most recent ON/WAKE event type 0 = Not caused by RTC Alarm 1 = Caused by RTC Alarm 4 ON_ON_PIN 0 Most recent ON/WAKE event type 0 = Not caused by the ON pin 1 = Caused by the ON pin 3 RESET_CNV_UV 0 Most recent ON event type 0 = Not caused by undervoltage 1 = Caused by a Device Reset due to a Converter (LDO or DC-DC) undervoltage condition 2 RESET_SW 0 Most recent ON event type 0 = Not caused by Software Reset 1 = Caused by Software Reset w PD, February 2012, Rev 4.0 33 WM8321 Production Data ADDRESS BIT 1 LABEL RESET_HW DEFAULT 0 DESCRIPTION Most recent ON event type 0 = Not caused by Hardware Reset 1 = Caused by Hardware Reset 0 RESET_WDOG 0 Most recent ON event type 0 = Not caused by the Watchdog 1 = Caused by a Device Reset triggered by the Watchdog timer R16399 (400Fh) 13 OFF_INTLDO_ERR 0 Most recent OFF event type 0 = Not caused by LDO13 Error condition OFF Source 1 = Caused by LDO13 Error condition 12 OFF_PWR_SEQ 0 Most recent OFF event type 0 = Not caused by Power Sequence Failure 1 = Caused by a Power Sequence Failure 11 OFF_GPIO 0 Most recent OFF event type 0 = Not caused by GPIO input 1 = Caused by GPIO input 10 OFF_PVDD 0 Most recent OFF event type 0 = Not caused by PVDD 1 = Caused by the SYSLO or SHUTDOWN threshold 9 OFF_THERR 0 Most recent OFF event type 0 = Not caused by temperature 1 = Caused by over-temperature 6 OFF_SW_REQ 0 Most recent OFF event type 0 = Not caused by software OFF 1 = Caused by software OFF command (CHIP_ON = 0) 4 OFF_ON_PIN 0 Most recent OFF event type 0 = Not caused by the ON pin 1 = Caused by the ON pin Table 2 Power State Control Registers Table 3 lists all of the events which can trigger an ON, WAKE, OFF or SLEEP transition sequence. It also lists the associated status bits of the ‘ON Source’ and ‘OFF Source’ register bits which are asserted under each condition. w PD, February 2012, Rev 4.0 34 WM8321 Production Data TRANSITION SEQUENCE ON (see note 1) WAKE OFF EVENT NOTES ON SOURCE / OFF SOURCE RTC alarm An ON request occurs if the RTC Alarm occurs in the OFF power state. See Section 20. ON_TRANS, ON_RTC_ALM GPIO ON request Requires a GPIO to be configured as “Power On request” or “Power On/Off request”. See Section 21. ON_TRANS, ON_GPIO ON ¯¯ pin request Requires the ON ¯¯ pin to be configured to generate ON request. See Section 11.6. ON_TRANS, ON_ON_PIN Software WAKE Writing CHIP_SLP = 0. See Table 2. ON_SW_REQ Watchdog timeout Requires the Watchdog to be configured to generate WAKE request. See Section 25. ON_WDOG_TO RTC alarm A WAKE request occurs if the RTC Alarm occurs in the SLEEP power state. See Section 20. ON_RTC_ALM GPIO WAKE request Requires a GPIO to be configured as “Sleep/Wake request”. See Section 21. ON_GPIO PVDD undervoltage Requires the PVDD monitor circuit to be configured to generate WAKE request. See Section 24.4. ON_SYSLO ON ¯¯ pin request Requires the ON ¯¯ pin to be configured to generate WAKE request. See Section 11.6. ON_ON_PIN Watchdog timeout Requires the Watchdog to be configured to generate Device Reset. See Section 25. RESET_WDOG Hardware Reset See Section 24. RESET_HW Software Reset See Section 24. RESET_SW Power Management Undervoltage Reset Configurable option for each LDO/DC-DC converter. See Section 15. RESET_CNV_UV Software OFF request Writing CHIP_ON = 0. See Table 2. OFF_SW_REQ ON pin request Requires the ON ¯¯ pin to be configured to generate OFF request. See Section 11.6. OFF_ON_PIN Thermal shutdown See Section 26. OFF_THERR PVDD undervoltage Requires the PVDD monitor circuit to be configured to generate OFF request. See Section 24.4. OFF_PVDD PVDD shutdown PVDD has fallen below the SHUTDOWN threshold. See Section 24.4. OFF_PVDD GPIO OFF request Requires a GPIO to be configured as “Power On/Off request”. See Section 21. OFF_GPIO Power Sequence failure DC-DC converters, LDOs or CLKOUT circuits have failed to start up within the permitted time. OFF_PWR_SEQ Internal LDO error Error condition detected in LDO13 OFF_INTLDO_ERR Software SLEEP request Writing CHIP_SLP = 1. See Table 2. See note 3 GPIO SLEEP request Requires a GPIO to be configured as “Sleep request” or “Sleep/Wake request”. See Section 21. See note 3 (See note 2) (See note 2) (See note 2) SLEEP (See note 2) Table 3 Power State Transition Events Notes: 1. An ON sequence is only permitted when the supply voltage PVDD exceeds a programmable threshold VSYSOK. See Section 24.4 for details of PVDD voltage monitoring. 2. These Reset conditions result in an OFF transition followed by an ON transition. These events are recorded as Reset events in the ‘ON Source’ register. 3. SLEEP events are not recorded in the ‘OFF Source’ register. w PD, February 2012, Rev 4.0 35 WM8321 Production Data 11.4 POWER STATE INTERRUPTS Power State transitions are associated with a number of Interrupt event flags. Transitions to BACKUP, SLEEP, ON or OFF states are indicated by the Interrupt bits described in Table 4. Each of these secondary interrupts triggers a primary Power State Interrupt, PS_INT (see Section 23). This can be masked by setting the mask bit(s) as described in Table 4. ADDRESS R16402 (4012h) Interrupt Status 2 BIT 2 LABEL PS_POR_EINT DESCRIPTION Power On Reset interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 1 PS_SLEEP_OFF_EINT SLEEP or OFF interrupt (Power state transition to SLEEP or OFF states) (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 0 PS_ON_WAKE_EINT ON or WAKE interrupt (Power state transition to ON state) (Rising Edge triggered) Note: Cleared when a ‘1’ is written. R16410 (401Ah) 2 IM_PS_POR_EINT Interrupt mask. 0 = Do not mask interrupt. Interrupt Status 2 Mask 1 = Mask interrupt. Default value is 1 (masked) 1 IM_PS_SLEEP_OFF_EINT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 0 IM_PS_ON_WAKE_EINT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Table 4 Power State Interrupts 11.5 POWER STATE GPIO INDICATION The WM8321 can be configured to generate logic signals via GPIO pins to indicate the current Power State. See Section 21 for details of configuring GPIO pins. A GPIO pin configured as “ON state” output will be asserted when the WM8321 is in the ON state. A GPIO pin configured as “SLEEP state” output will be asserted when the WM8321 is in the SLEEP state. w PD, February 2012, Rev 4.0 36 WM8321 Production Data 11.6 ON PIN FUNCTION The ON ¯¯ pin is intended for connection to the master power switch on the user’s application. It can be used to start-up the WM8321 from the SLEEP or OFF states and also to power down the system. This pin operates on the LDO12 (VPMIC) power domain and has an internal pull-up resistor. This pin is asserted by shorting it to GND. A de-bounce circuit is provided on this input pin. The behaviour of the ON ¯¯ pin is programmable. The primary action taken on asserting this pin is determined by the ON_PIN_PRIMACT register field. Note that the ON_PIN_INT interrupt event is always raised when the ON ¯¯ pin is asserted. If the pin is held asserted for longer than the timeout period set by ON_PIN_TO, then a secondary action is executed. The secondary action is determined by the ON_PIN_SECACT register field. If the pin is held asserted for a further timeout period, then a tertiary action is executed. The tertiary action is not programmable, and is to generate an OFF request. The status of the ON ¯¯ pin can be read at any time via the ON_PIN_STS register. Note that the ON ¯¯ pin control registers are locked by the WM8321 User Key. These registers can only be changed by writing the appropriate code to the Security register, as described in Section 12.4. ADDRESS R16389 (4005h) ON Pin Control BIT 9:8 LABEL ON_PIN_SECACT DEFAULT DESCRIPTION 01 Secondary action of ON ¯¯ pin (taken after 1 timeout period) 00 = Interrupt 01 = ON request 10 = OFF request 11 = Reserved Protected by user key 5:4 ON_PIN_PRIMACT 00 Primary action of ON ¯¯ pin 00 = Ignore 01 = ON request 10 = OFF request 11 = Reserved Note that an Interrupt is always raised. Protected by user key 3 ON_PIN_STS 0 Current status of ON ¯¯ pin 0 = Asserted (logic 0) 1 = Not asserted (logic 1) 1:0 ON_PIN_TO 00 ON ¯¯ pin timeout period 00 = 1s 01 = 2s 10 = 4s 11 = 8s Protected by user key Table 5 ON Pin Control Registers The ON ¯¯ pin interrupt event is always raised as part of the primary action when the ON ¯¯ pin is asserted or de-asserted. (Note that the ON ¯¯ pin interrupt is raised on the rising and falling edges of this ON ¯¯ pin input signal.) The ON ¯¯ pin interrupt is a selectable option as the secondary action. The ON ¯¯ pin interrupt event is indicated by the ON_PIN_CINT register field. This secondary interrupt triggers a primary ON Pin Interrupt, ON_PIN_INT (see Section 23). This can be masked by setting the mask bit as described in Table 6. w PD, February 2012, Rev 4.0 37 WM8321 Production Data ADDRESS R16401 (4011h) BIT 12 LABEL DESCRIPTION ON_PIN_CINT ON pin interrupt. (Rising and Falling Edge triggered) Interrupt Status 1 R16409 (4019h) Note: Cleared when a ‘1’ is written. 12 IM_ON_PIN_CINT Interrupt mask. 0 = Do not mask interrupt. Interrupt Status 1 Mask 1 = Mask interrupt. Default value is 1 (masked) Table 6 ON Pin Interrupt 11.7 RESET PIN FUNCTION The RESET ¯¯¯¯¯¯ pin is an active low input/output which is used to command Hardware Resets in the WM8321 and in other connected devices. The pin is an open-drain type, with integrated pull-up; it can be driven low by external sources or by the WM8321 itself. The WM8321 drives the RESET ¯¯¯¯¯¯ pin low in the OFF state. The output status of the RESET ¯¯¯¯¯¯ pin in SLEEP is configurable; this is determined by the RST_SLPENA register bit as defined in Table 7. The WM8321 clears the RESET ¯¯¯¯¯¯ pin following the transition to ON. On completion of the state transition, the RESET ¯¯¯¯¯¯ pin is held low for a further delay time period, extending the RESET ¯¯¯¯¯¯ low duration. The RESET ¯¯¯¯¯¯ delay period is set by the RST_DUR register bit. See Figure 6 for further details. The WM8321 detects a Hardware Reset request whenever the RESET ¯¯¯¯¯¯ pin is driven low by an external source. In this event, the WM8321 resets the internal control registers (excluding the RTC) and initiates a start-up sequence. See Section 24. It is possible to mask the RESET ¯¯¯¯¯¯ pin input in the SLEEP state by setting the RST_SLP_MSK register bit. In SLEEP mode, if RST_SLP_MSK is set, the WM8321 will take no action if the RESET ¯¯¯¯¯¯ pin is pulled low. Note that the RESET ¯¯¯¯¯¯ pin control registers are locked by the WM8321 User Key. These registers can only be changed by writing the appropriate code to the Security register, as described in Section 12.4. ADDRESS R16390 (4006h) Reset Control BIT LABEL DEFAULT 5 RST_SLP_MSK 1 DESCRIPTION Masks the RESET ¯¯¯¯¯¯ pin input in SLEEP mode 0 = External RESET ¯¯¯¯¯¯ active in SLEEP 1 = External RESET ¯¯¯¯¯¯ masked in SLEEP Protected by user key 4 RST_SLPENA 1 Sets the output status of RESET ¯¯¯¯¯¯ pin in SLEEP 0 = RESET ¯¯¯¯¯¯ high (not asserted) 1 = RESET ¯¯¯¯¯¯ low (asserted) Protected by user key 1:0 RST_DUR 11 Delay period for releasing RESET ¯¯¯¯¯¯ after ON or WAKE sequence 00 = 3ms 01 = 11ms 10 = 51ms 11 = 101ms Protected by user key Table 7 RESET Pin Control Registers w PD, February 2012, Rev 4.0 38 WM8321 Production Data The WM8321 can generate an Auxiliary Reset output via a GPIO pin configured as “Auxiliary Reset” output (see Section 21). This signal is asserted in the OFF state. The status of the Auxiliary Reset in the SLEEP state is configurable, using the AUXRST_SLPENA register bit as defined in Table 8. ADDRESS R16390 (4006h) BIT LABEL DEFAULT 6 AUXRST_SLPE NA 1 Reset Control DESCRIPTION Sets the output status of Auxiliary Reset (GPIO) function in SLEEP 0 = Auxiliary Reset not asserted 1 = Auxiliary Reset asserted Protected by user key Table 8 Auxiliary Reset (GPIO) Control Power State OFF State Transition RESET is de-asserted ON transition completes ON transition starts ‘ON’ event The timing details of the RESET ¯¯¯¯¯¯ pin relative to an ON state transition are illustrated in Figure 6. ON RESET pin Time Time delay set by PWRSTATE_DELAY 1ms or 10ms ON transition. Nominal duration = 5 x 2ms RESET delay set by RST_DUR 3ms, 11ms, 51ms or 101ms Figure 6 RESET Pin Output w PD, February 2012, Rev 4.0 39 WM8321 Production Data 12 CONTROL INTERFACE 12.1 GENERAL DESCRIPTION The WM8321 is controlled by writing to its control registers. Readback is available for all registers, including Chip ID, power management status and GPIO status. The control interface can operate as a 2-wire (I2C) or 4-wire (SPI) control interface. Readback is provided on the bi-directional pin SDA1 in 2-wire (I2C) mode. The WM8321 Control Interface is powered by the DBVDD power domain. The control interface mode is determined by the logic level on the CIFMODE pin as shown in Table 9. CIFMODE INTERFACE FORMAT Low 2-wire (I2C) mode High 4-wire (SPI) mode Table 9 Control Interface Mode Selection 12.2 2-WIRE (I2C) CONTROL MODE In 2-wire (I2C) mode, the WM8321 is a slave device on the control interface; SCLK1 is a clock input, while SDA1 is a bi-directional data pin. To allow arbitration of multiple slaves (and/or multiple masters) on the same interface, the WM8321 transmits logic 1 by tri-stating the SDA1 pin, rather than pulling it high. An external pull-up resistor is required to pull the SDA1 line high so that the logic 1 can be recognised by the master. In order to allow many devices to share a single 2-wire control bus, every device on the bus has a unique 8-bit device ID (this is not the same as the 16-bit address of each register in the WM8321). The device ID is determined by the logic level on the CS ¯¯ pin as shown in Table 10. The LSB of the device ID is the Read/Write bit; this bit is set to logic 1 for “Read” and logic 0 for “Write”. CS ¯¯ DEVICE ID Low 0110 100x = 68h(write) / 69h(read) High 0110 110x = 6Ch(write) / 6Dh(read) Table 10 Control Interface Device ID Selection The WM8321 operates as a slave device only. The controller indicates the start of data transfer with a high to low transition on SDA1 while SCLK1 remains high. This indicates that a device ID, register address and data will follow. The WM8321 responds to the start condition and shifts in the next eight bits on SDA1 (8-bit device ID including Read/Write bit, MSB first). If the device ID received matches the device ID of the WM8321, then the WM8321 responds by pulling SDA1 low on the next clock pulse (ACK). If the device ID is not recognised or the R/W bit is ‘1’ when operating in write only mode, the WM8321 returns to the idle condition and waits for a new start condition and valid address. If the device ID matches the device ID of the WM8321, the data transfer continues as described below. The controller indicates the end of data transfer with a low to high transition on SDA1 while SCLK1 remains high. After receiving a complete address and data sequence the WM8321 returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e. SDA1 changes while SCLK1 is high), the device returns to the idle condition. The WM8321 supports the following read and write operations: w Single write Single read Multiple write using auto-increment Multiple read using auto-increment PD, February 2012, Rev 4.0 40 WM8321 Production Data The sequence of signals associated with a single register write operation is illustrated in Figure 7. Figure 7 Control Interface 2-wire (I2C) Register Write The sequence of signals associated with a single register read operation is illustrated in Figure 8. Figure 8 Control Interface 2-wire (I2C) Register Read The Control Interface also supports other register operations, as listed above. The interface protocol for these operations is summarised below. The terminology used in the following figures is detailed in Table 11. Note that, for multiple write and multiple read operations, the auto-increment option must be enabled. This feature is enabled by default; it is described in Table 12 below. TERMINOLOGY DESCRIPTION S Start Condition Sr Repeated start A Acknowledge (SDA Low) ¯¯ A Not Acknowledge (SDA High) P R/W ¯¯ Stop Condition ReadNotWrite 0 = Write 1 = Read [White field] Data flow from bus master to WM8321 [Grey field] Data flow from WM8321 to bus master Table 11 Control Interface Terminology Figure 9 Single Register Write to Specified Address w PD, February 2012, Rev 4.0 41 WM8321 Production Data Figure 10 Single Register Read from Specified Address Figure 11 Multiple Register Write to Specified Address using Auto-increment Figure 12 Multiple Register Read from Specified Address using Auto-increment Figure 13 Multiple Register Read from Last Address using Auto-increment Multiple Write and Multiple Read operations enable the host processor to access sequential blocks of the data in the WM8321 register map faster than is possible with single register operations. The autoincrement option is enabled when the AUTOINC register bit is set. This bit is defined in Table 12. Auto-increment is enabled by default. ADDRESS R16391 (4007h) BIT 2 LABEL AUTOINC Control Interface DEFAULT 1 DESCRIPTION Enable Auto-Increment function 0 = Disabled 1 = Enabled Table 12 Auto-Increment Control w PD, February 2012, Rev 4.0 42 WM8321 Production Data 12.3 4-WIRE (SPI) CONTROL MODE In this mode, the WM8321 registers are accessed using a 4-wire serial control interface. The CS ¯¯ and SCLK1 pins provide the ‘Chip Select’ and ‘Serial Data Clock’ functions respectively. Serial data input is supported on the SDA1 pin; serial data output is supported on the SDOUT1 pin. A control word consists of 32 bits. The first bit is the read/write bit (R/W), which is followed by 15 address bits (A14 to A0) that determine which control register is accessed. The remaining 16 bits (B15 to B0) are data bits, corresponding to the 16 bits in each control register. In Write operations (R/W=0), all SDA1 bits are driven by the controlling device. Each rising edge of SCLK1 clocks in one data bit from the SDA1 pin. A rising edge on CS ¯¯ latches in a complete control word consisting of the last 32 bits. In Read operations, the SDA1 pin is ignored following receipt of the valid register address. The data bits are output by the WM8321 on the SDOUT1 pin. SDOUT1 is undriven (high impedance) when not outputting register data bits. The SDOUT1 pin is an Open Drain output; an external pull-up resistor to DBVDD is required on SDOUT1 in 4-wire (SPI) mode. The sequence of signals associated with a register write operation is illustrated in Figure 14. CS SCLK SDIN R/W A14 A13 A12 A2 A1 A0 B15 15-bit control register address B14 B13 B2 B1 B0 16-bit control register data Figure 14 Control Interface 4-wire (SPI) Register Write The sequence of signals associated with a register read operation is illustrated in Figure 15. Figure 15 Control Interface 4-wire (SPI) Register Read 12.4 REGISTER LOCKING Selected registers are protected by a security key. These registers can only be written to when the appropriate ‘unlock’ code has been written to the Security Key register. The protected registers include those associated with Reset Control, OTP Programming and RTC Trim. Other selected functions also include protected registers; the affected registers are identified in the Register Map definitions throughout the document, and also in Section 29. To unlock the protected registers, a value of 9716h must be written to the Security register (R16392), as defined in Table 13. w PD, February 2012, Rev 4.0 43 WM8321 Production Data It is recommended to re-lock the protected registers immediately after writing to them. This helps protect the system against accidental overwriting of register values. To lock the protected registers, a value of 0000h should be written to the Security register. ADDRESS R16392 (4008h) BIT LABEL 15:0 SECURITY [15:0] Security Key DEFAULT 0000h DESCRIPTION Security Key A value of 9716h must be written to this register to access the userkeyed registers. Table 13 Security Key Registers 12.5 SOFTWARE RESET AND CHIP ID A Software Reset can be commanded by writing to Register 0000h. This is a read-only register field and the contents of this register will not be affected by a write operation. For more details of the different reset types, see Section 24. Note that a maximum of 6 Software Resets is permitted. If more than 6 Software Resets are scheduled, the WM8321 will remain in the OFF state until the next valid ON state transition event occurs. The Chip ID can be read back from Register 0000h. Other ID fields can be read from the registers defined in Table 14. ADDRESS R0 (0000h) BIT 15:0 Reset/ID LABEL CHIP_ID [15:0] DEFAULT DESCRIPTION 0000h Writing to this register causes a Software Reset. The register map contents may be reset, depending on SW_RESET_CFG. Reading from this register will indicate Chip ID. R1 (0001h) 15:8 PARENT_RE V [7:0] 00h The revision number of the parent die 7:0 CHILD_REV [7:0] 00h The revision number of the child die (when present) 15:0 PARENT_ID [15:0] 6246h Revision R16384 (4000h) Parent ID The ID of the parent die Table 14 Reading Device Information 12.6 SOFTWARE SCRATCH REGISTER The WM8321 provides one 16-bit register as a “Software Scratch” register. This is available for use by the host processor to store data for any purpose required by the application. The contents of the Software Scratch register are retained in the BACKUP power state. ADDRESS R16393 (4009h) Software Scratch BIT LABEL DEFAULT 15:0 SW_SCRATC H [15:0] 0000h DESCRIPTION Software Scratch Register for use by the host processor. Note that this register’s contents are retained in the BACKUP power state. Table 15 Software Scratch Register w PD, February 2012, Rev 4.0 44 WM8321 Production Data 13 CLOCKING AND OSCILLATOR CONTROL 13.1 GENERAL DESCRIPTION The WM8321 incorporates a 32.768kHz crystal oscillator in order to maintain the Real Time Clock (RTC). An external crystal is normally required. Alternatively, a 32.768kHz signal may be input directly on the XTI pin. The crystal oscillator and RTC are enabled at all times, including the OFF and BACKUP power states. It is possible to disable the crystal oscillator in BACKUP for power-saving RTC ‘unclocked’ mode if desired. The WM8321 clock functions are illustrated in Figure 16. Figure 16 Clocking Configuration The 32.768kHz crystal oscillator is enabled using the XTAL_ENA register. The crystal oscillator is enabled in the OFF, ON and SLEEP power states when XTAL_ENA = 1. The status of the crystal oscillator in BACKUP is selected using the XTAL_BKUPENA register. Note that the XTAL_ENA field is set via OTP/ICE settings only; it cannot be changed by writing to the control register. If the crystal is omitted, and an external 32.768kHz signal is connected as an input to the XTI pin, it is still required to set XTAL_ENA = 1 for normal operation. The crystal oscillator can be disabled in the BACKUP state by setting the XTAL_BKUPENA register bit to 0. This feature may be used to minimise the device power consumption in the BACKUP state, as described in Section 20.5. The crystal oscillator is maintained in the BACKUP state if both XTAL_ENA and XTAL_BKUPENA are set to 1. The CLKOUT signal, derived from the 32.768kHz oscillator, can be enabled or disabled directly by writing to the CLKOUT_ENA register in the ON or SLEEP power states. The CLKOUT can also be controlled as part of the power state transitions using the CLKOUT_SLOT and CLKOUT_SLP_SLOT register fields. See Section 11.3 for a description of the state transition timeslots. The CLKOUT pin may be configured as a CMOS output or as an Open-Drain output. The CLKOUT signal is referenced to the DBVDD power domain. The status of the crystal oscillator is indicated by the XTAL_OK register bit. If the crystal oscillator fails to start, or if it stops for any reason, then the XTAL_OK register will be set to 0. An internal RC oscillator is available in order to provide CLKOUT functionality during start-up of the crystal oscillator. This function is selectable using the XTAL_INH register bit, as described below. If XTAL_INH = 0, then the internal RC oscillator provides the CLKOUT signal in the event that the crystal oscillator has not fully started up prior to an ‘ON’ state transition event. A glitch-free transition between the clock sources is implemented after the crystal oscillator is ready. If XTAL_INH = 1, then an ‘ON’ state transition is delayed until the crystal oscillator has fully started up. This may be desirable if the CLKOUT signal is used as a clock for another circuit, to ensure that CLKOUT signal has been verified before the ‘ON’ state transition occurs. Note that the CLKOUT output is always disabled in the OFF power state; it is typically enabled as part of the ‘ON’ state transition sequence. Setting XTAL_INH = 1 ensures that the CLKOUT output cannot be enabled until the crystal frequency has been verified. If XTAL_INH = 1, and the crystal oscillator fails to start, then a System Reset will be scheduled after a timeout period of approximately 32 seconds. See Section 24 for details of System Resets. w PD, February 2012, Rev 4.0 45 WM8321 Production Data The WM8321 provides two interrupt flags associated with the crystal oscillator, as described in Section 13.2. These interrupts will provide indication of a crystal oscillator start-up failure, or detection of an interruption to the crystal oscillator (eg, due to tampering). The CLKOUT control fields are described in Table 16. Some of these controls may also be stored in the integrated OTP memory. See Section 14 for details. The 32.768kHz oscillator may also be output on a GPIO pin, as described in Section 21. Note that a GPIO pin configured as 32.768kHz output will continue to output the oscillator clock in the OFF power state; this may be used to provide clocking to the processor in the OFF state, provided that the selected power domain for that GPIO pin remains enabled in the OFF state. The CLKOUT output is always disabled in the OFF power state. The internal RC oscillator generates the required clocks for the integrated DC-DC Converters on the WM8321. Note that a 2MHz ‘External Power Clock’, derived from this oscillator, may be output on a GPIO pin to provide synchronised clocking of external DC-DC Converters if required (see Section 21). The 2MHz External Power Clock is only enabled when either of the External Power Enable signals EPE1 or EPE2 is asserted. The External Power Enable (EPE) signals are controlled as described in Section 15.3. Note that the CLKOUT_ENA control register is locked by the WM8321 User Key. This register can only be changed by writing the appropriate code to the Security register, as described in Section 12.4. ADDRESS R16397 (400Dh) BIT 7 LABEL XTAL_OK DEFAULT 0 System Status DESCRIPTION Crystal Oscillator Status 0 = Disabled or in start-up phase 1 = Enabled and verified R16528 (4090h) 15 CLKOUT_ENA 0 Clock Control 1 CLKOUT output enable 0 = Disabled 1 = Enabled Protected by user key 13 CLKOUT_OD 0 CLKOUT pin configuration 0 = CMOS 1 = Open Drain 10:8 CLKOUT_SLOT 000 CLKOUT output enable ON slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Do not enable 111 = Do not enable 6:4 CLKOUT_SLP SLOT 000 CLKOUT output SLEEP slot select 000 = Controlled by CLKOUT_ENA 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = Controlled by CLKOUT_ENA 111 = Controlled by CLKOUT_ENA w PD, February 2012, Rev 4.0 46 WM8321 Production Data ADDRESS BIT LABEL 15 XTAL_INH R16529 (4091h) DEFAULT 0 Clock Control 2 DESCRIPTION Crystal Start-Up Inhibit 0 = Disabled 1 = Enabled When XTAL_INH=0, the internal RC oscillator will provide CLKOUT until the crystal oscillator is valid. When XTAL_INH=1, the ‘ON’ transition is inhibited until the crystal oscillator is valid. 13 XTAL_ENA 0 Crystal Oscillator Enable 0 = Disabled at all times 1 = Enabled in OFF, ON, SLEEP states (Note that the BACKUP behaviour is determined by XTAL_BKUPENA.) This field can only be written to by loading configuration settings from OTP/ICE. In all other cases, this field is Read Only. 12 XTAL_BKUPE NA 1 Selects the RTC and 32.768kHz oscillator in BACKUP state 0 = RTC unclocked in BACKUP 1 = RTC maintained in BACKUP (Note that XTAL_ENA must also be set if the RTC is to be maintained in BACKUP) Table 16 Clocking Control 13.2 CRYSTAL OSCILLATOR INTERRUPTS The Crystal Oscillator (XTAL) is associated with two Interrupt event flags. The XTAL_START_EINT interrupt is set if the crystal oscillator fails to start-up within a timeout period of approximately 24 seconds. The XTAL_TAMPER_EINT interrupt is set if the crystal oscillator is stopped unexpectedly (eg. due to tampering). Note that this interrupt is only supported if the crystal oscillator has previously started up successfully. The XTAL_TAMPER_EINT is also set if the crystal oscillator is re-started following an unexpected interruption. Each of these secondary interrupts triggers a primary Real Time Clock and Crystal Oscillator Interrupt, RTC_INT (see Section 23). In the case of XTAL_START_EINT, this can be masked by setting the mask bit(s) as described in Table 17. ADDRESS R16404 (4014h) Interrupt Status 4 BIT 7 LABEL XTAL_START_EINT DESCRIPTION Crystal Oscillator Start Failure interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 6 XTAL_TAMPER_EINT Crystal Oscillator Tamper interrupt (Rising and Falling Edge triggered) Note: Cleared when a ‘1’ is written. R16412 (401Ch) 7 IM_XTAL_START_EINT Interrupt Status 4 Mask Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Table 17 Crystal Oscillator (XTAL) Interrupts w PD, February 2012, Rev 4.0 47 WM8321 Production Data 13.3 CRYSTAL OSCILLATOR CONNECTIONS The crystal oscillator generates a 32.768kHz reference clock, which is used to provide reference clock for the Real Time Clock (RTC) in the WM8321. The oscillator requires an external crystal on the XTI and XTO pins, as well as two capacitors, connected as shown in Figure 17. 32kHz WM8321 Crystal Oscillator XOSCGND Crystal Model XTI C1 XTO Cp Rxt C2 Lxt Cxt Figure 17 Crystal Oscillator A suitable crystal oscillator should be selected in accordance with the following requirements: PARAMETER MIN Nominal frequency MAX UNITS 32.768 Series resistance 50 Maximum driving level 0.5 kHz 70 k W Table 18 Selection of Crystal Oscillator Component The load capacitors C1 and C2 should be selected according to the recommended load capacitance, CL of the crystal, which is given by the following equation: Assuming C1 = C2 and CSTRAY = 2.75pF (typical pad i/o capacitance), then: C1 = C2 = 2 x (CL - 2.75pF). For example, if the crystal has a load capacitance CL = 9pF, then C1 = C2 = 12.5pF. If a suitable 32.768kHz clock is already present elsewhere in the system, it is possible for the WM8321 to use that external clock instead. The external clock should be applied to pin XTI, and the XTO pin left floating in this case. w PD, February 2012, Rev 4.0 48 WM8321 Production Data 14 INSTANTCONFIG™ (ICE) AND OTP MEMORY CONTROL 14.1 GENERAL DESCRIPTION The WM8321 is a highly configurable device which can be tailored specifically to the requirements of a complex system application. The sequencing and voltage control of the integrated DC-DC Converters and LDOs in power-up, shut-down and SLEEP conditions is crucial to the robust operation of the application. In development, the WM8321 allows designers to modify or experiment with different settings of the control sequences by writing to the applicable registers in the OFF state prior to commanding an ‘ON’ state transition. Configuration settings can also be stored on an external EEPROM and loaded onto the WM8321 as required, using the InstantConfig™ EEPROM (ICE) interface. For production use, the WM8321 provides an on-chip One-Time Programmable (OTP) memory, in which the essential parameters for starting up the device can be programmed. This allows the WM8321 to start up and shut down the system with no dependency on any other devices for application-specific configuration parameters. 14.2 ICE AND OTP MEMORY DEFINITION An illustration of the WM8321 memory locations is shown in Figure 18. The main Register Map of the WM8321 contains a block of data in a ‘Window’ area which is mirrored in the OTP and/or the ICE Memory. Data from the external ICE Memory can be loaded into the Window area. Data can be transferred from the Window into OTP Memory and also from the OTP Memory into the Window. The Window is called the Device Configuration Register Window (DCRW); the data in this Window is mirrored in other locations within the WM8321 Register Map. Figure 18 ICE and OTP Memory Layout The DCRW contains 5 pages of data, as illustrated in Figure 18. w PD, February 2012, Rev 4.0 49 WM8321 Production Data Page 0 of the DCRW contains a 128-bit pseudo-random unique ID. The unique ID is written to the OTP at the time of manufacture. It is copied to the DCRW when the WM8321 schedules an ‘ON’ transition. This data cannot be changed. Page 1 of the DCRW contains factory-set calibration and configuration data. This data is written to the OTP at the time of manufacture. It is copied to the DCRW when the WM8321 schedules an ‘ON’ transition. This data cannot be changed. Page 2 and Page 3 of the DCRW contain bootstrap configuration data. This defines the sequence and voltage requirements for powering up the WM8321, and for configuring functions such as the clocks, GPIO1-6 and LED status indicators. Under default conditions, the bootstrap data is loaded into the DCRW when the WM8321 schedules an ‘ON’ transition. The WM8321 automatically determines whether to load the bootstrap data from ICE or from OTP as described in Section 14.3. Page 4 of the DCRW contains a register that is used for ICE validity checking. It is copied to the DCRW whenever the bootstrap configuration data is loaded from ICE in response to a start-up request in development mode. This register field enables the ICE data to be checked for valid content. The OTP contains 4 pages of data, as illustrated in Figure 18. The contents of the OTP pages correspond to Pages 0, 1, 2 and 3 of the DCRW register map addresses. The ICE memory contains 3 pages of data, as illustrated in Figure 18. The contents of the ICE pages correspond to Pages 2, 3 and 4 of the DCRW register map addresses. Note that the ICE memory (recommended component) is arranged as 8-bit words in “big-endian” format, and is therefore addressed as 6 pages of 8-bit data, corresponding to 3 pages of 16-bit data. For example, the ICE memory address 00h corresponds to bits 15:8 of the first register map word in DCRW Page 2, and ICE address 01h corresponds to bits 7:0 of that same register word in DCRW. The DCRW can be accessed directly using the Control Interface in the OFF, ON and SLEEP power states. Note that Read/Write access to the ICE or OTP memories is not possible directly; these can only be accessed by copying to/from the DCRW. In the PROGRAM state, Page 2 and Page 3 of the DCRW can be written to the OTP. 14.3 BOOTSTRAP (START-UP) FUNCTION Under default conditions, the WM8321 bootstrap configuration data is loaded when the WM8321 schedules an ‘ON’ transition. The bootstrap configuration data is loaded into Page 2 and Page 3 of the DCRW from either an external ICE or from the integrated OTP. (The factory-set data in Page 0 and Page 1 is always loaded from the integrated OTP memory.) TM If Development mode is selected, then the bootstrap data is loaded from the InstantConfig EEPROM (ICE). If Development mode is not selected, then the bootstrap data is loaded from the OTP memory. 14.3.1 START-UP FROM OTP MEMORY In volume production, development mode is not usually selected. In this case, the bootstrap configuration data is loaded from the internal OTP memory. The WM8321 performs a check for valid OTP data; if the OTP_CUST_ID field is set to zero, then the WM8321 remains in the OFF power state. A non-zero OTP_CUST_ID field is used to confirm valid OTP contents. The OTP memory contents are defined similarly to Pages 0, 1, 2 and 3 of the DCRW memory contents listed in Section 14.6. w PD, February 2012, Rev 4.0 50 WM8321 Production Data 14.3.2 START-UP FROM ICE MEMORY (DEVELOPMENT MODE) Development mode is selected if a logic high level (referenced to the LDO12 VPMIC voltage) is present on SCLK2. This should be implemented using a pull-up resistor. See Section 14.3.4 for details of the External ICE Memory connection. If development mode is selected, then the WM8321 performs a check for valid ICE data; if the ICE is not connected or contains invalid data, then the WM8321 remains in the OFF power state. The ICE data is deemed valid is the ICE_VALID_DATA field contains the value A596h. The WM8321 also performs a check for valid contents in the OTP_CUST_ID field in development mode; if the OTP_CUST_ID field is set to zero, then the WM8321 remains in the OFF power state. A non-zero OTP_CUST_ID field is used to confirm valid ICE contents. Note that, if a GPIO pin is configured in ICE memory as “Power On/Off request” (GPn_FN=02h), then inverted (active low) polarity should be selected for that GPIO (GPn_POL=0). The non-inverted (active high) polarity cannot be fully supported for this function in development mode. This restriction is only applicable in development mode, and applies only to the GPIO “Power On/Off request” function. See Section 21 for details of the GPIO pin configuration registers. The non-inverted (active high) polarity can be supported for the GPIO “Power On/Off request” function in development mode if the corresponding GPn_POL register bit in the OTP memory is set to 1. Note that, if the OTP memory is unprogrammed, the GPn_POL bits will default to 0. 14.3.3 START-UP FROM DCRW REGISTER SETTINGS Under default settings, the bootstrap configuration data is always loaded when an ON transition is scheduled. For development purposes, this can be disabled by clearing the RECONFIG_AT_ON register bit. (Note that RECONFIG_AT_ON only selects whether Page 2/3/4 data is loaded; Page 0/1 data is always loaded from OTP whenever an ON transition is scheduled.) When RECONFIG_AT_ON = 1, the bootstrap data is reloaded from either the ICE or OTP when an ON transition is scheduled. The logic level on SCLK2 is checked to determine whether the ICE or the OTP memory should be used. If RECONFIG_AT_ON = 0, then the latest contents of the DCRW are used to configure the start-up sequence. Note that, when WM8321 start-up is scheduled using this method, the contents of OTP_CUST_ID is still checked for valid contents. In development mode, the ICE_VALID_DATA field is also checked. See Section 14.3.2 for details. Note that the RECONFIG_AT_ON control register is locked by the WM8321 User Key. This register can only be changed by writing the appropriate code to the Security register, as described in Section 12.4. ADDRESS BIT LABEL DEFAULT R16390 (4006h) 15 RECONFIG_A T_ON 1 Reset Control DESCRIPTION Selects if the bootstrap configuration data should be reloaded when an ON transition is scheduled 0 = Disabled 1 = Enabled Protected by user key Table 19 Bootstrap Configuration Reload Control 14.3.4 EXTERNAL ICE MEMORY CONNECTION The recommended component for the external ICE is the Microchip 24AA32A, which provides 32 bytes of memory space. The ICE interfaces with the WM8321 via the SCLK2 and SDA2 pins, and initiates an I2C transfer of data from the ICE when required. The necessary electrical connections for this device are illustrated in Figure 19. The WM8321 assumes an EEPROM device ID of 1010 0001 (A1h) for ICE read cycles. The ICE memory contents are defined similarly to Pages 2, 3 and 4 of the DCRW memory contents listed in Section 14.6. w PD, February 2012, Rev 4.0 51 WM8321 Production Data Figure 19 ICE Memory Connection Note that the WM8321 does not support programming the external ICE memory. External programming of ICE whilst physically connected to the WM8321 is possible by putting the WM8321 in the OFF state. This is supported on the evaluation board, provided the voltage levels on SCLK2 and SDA2 are less than or equal to the LDO12 VPMIC voltage. Note that the Write-Protect (WP) pin on the ICE must be connected to GND (Vss) in this case. 14.4 OTP / ICE MEMORY CONTROL The OTP and ICE Memory commands are initiated by writing to the OTP Control Register, as defined in Section 14.4.6. The supported commands are described below. READ ICE MEMORY - This command instructs the WM8321 to load data from the external ICE into the WM8321 DCRW memory area. Note that this command is performed automatically when the WM8321 starts up in development mode. READ OTP MEMORY - This command instructs the WM8321 to load data from the integrated OTP memory area into the WM8321 DCRW memory area. Note that this command is performed automatically when the WM8321 starts up in normal (ie. non-development) mode. WRITE OTP MEMORY - This command instructs the WM8321 to program the integrated OTP, by writing a copy of the DCRW memory area (Pages 0, 1, 2 and 3) to the OTP memory. This command should be performed after the required settings have been configured in the DCRW memory. The required settings can be configured in the DCRW either as a result of a ICE Read command, or else through register writes in the PROGRAM power state. Note that the Write OTP command should only be performed once on each OTP page; after the Write OTP command has been performed, the contents of the affected page(s) cannot be erased or re-programmed. VERIFY OTP MEMORY - This command instructs the WM8321 to compare the contents of the OTP memory with the contents of the DCRW memory. The Verify OTP command performs a check that the OTP data is identical to the DCRW contents, in order to confirm the success of the Write OTP operation. For increased reliability, the WM8321 can apply a ‘Margin Read’ function when verifying the OTP memory; it is recommended that the Margin Read option is used, as described in Section 14.4.4. FINALISE OTP PAGES - This command instructs the WM8321 to set the OTP_CUST_FINAL bit in the OTP memory. The Finalise OTP command ensures that any subsequent OTP_WRITE commands to Page 2 or Page 3 of the OTP will have no effect and that the OTP contents are maintained securely. w PD, February 2012, Rev 4.0 52 WM8321 Production Data The OTP and ICE Memory commands are each described in the following sections. Note that, in some cases, commands may be executed on a single page of memory or may be executed as a Bulk operation on all available memory pages. Completion of each OTP or ICE Memory command is indicated via an Interrupt flag, as described in Section 14.5. The pass/fail outcome of any OTP command is also indicated by the Interrupt bits. Note that read/write access to the WM8321 Register Map is not supported while a ICE/OTP command is in progress. It is recommended that the IRQ ¯¯¯ pin is configured to indicate any ICE/OTP Interrupt event; the host processor should read the OTP/ICE Interrupt event flags to confirm the OTP/ICE command status following the assertion of the IRQ ¯¯¯ pin. The programming supply voltage PROGVDD is required for the OTP Write commands and the OTP Finalise command. It is also necessary to overdrive the LDO12VOUT pin from an external supply. See Section 6 for details of the required supply voltages. 14.4.1 ENTERING / EXITING THE PROGRAM STATE The ICE and OTP commands are only supported when the WM8321 is in the PROGRAM state. The WM8321 can only enter the PROGRAM state as a transition from the OFF state. This is commanded by setting the OTP_PROG register bit. Important note - when the PROGRAM state is selected, the WM8321 will read all pages of the OTP memory into the corresponding pages of the DCRW. This is required in order to confirm if the OTP contents have already been finalised (see Section 14.4.5). The previous contents of the DCRW registers will be lost when the PROGRAM state is entered. The transition into the PROGRAM state can be confirmed by reading the MAIN_STATE register field as defined in Section 11.2. When the MAIN_STATE register reads back a value of 01011, then the WM8321 is in the PROGRAM state. In the PROGRAM state, the ICE and OTP commands are initiated by further writes to the OTP Control Register (R16394), as described in the following sections. To exit the PROGRAM state and resume normal operations, a Device Reset must be scheduled. 14.4.2 OTP / ICE READ COMMAND The Read command loads either one or all data pages from the ICE or OTP into the corresponding page(s) of the DCRW. The Read commands are selected by writing 1 to the OTP_READ bit. To read the OTP, the OTP_MEM bit should be set to 1. To read the ICE, the OTP_MEM bit should be set to 0. The Read Margin Level is selected by setting the OTP_READ_LVL. Note that this register relates to the OTP only; it has no effect on ICE Read commands. The recommended setting for the OTP Read command is ‘Normal’ level. The OTP_READ_LVL field should be set to 00b. To read a single memory page, the applicable page is selected by setting the OTP_PAGE field. To read all memory pages, the OTP_BULK bit should be set to 1. Note that the OTP_PAGE field is defined differently for ICE pages and for OTP pages, as detailed in Section 14.4.6. All other bits in the OTP Control Register should be set to 0 when a Read command is issued. (Note that OTP_PROG should be set to 0 when a Read command is issued.) For typical applications, the Bulk Read commands are recommended. The OTP Control Register contents for the OTP / ICE Bulk Read Commands are detailed in Table 20. READ COMMAND OTP CONTROL REGISTER VALUE ICE Read All 0120h OTP Read All 2120h Table 20 OTP / ICE Read Command w PD, February 2012, Rev 4.0 53 WM8321 Production Data 14.4.3 OTP WRITE COMMAND The Write command programs one or all data pages of the OTP with data from the corresponding page(s) of the DCRW. The Write commands are selected by writing 1 to the OTP_WRITE bit. The OTP memory is selected by setting the OTP_MEM bit to 1. (Note that the WM8321 does not support programming the external ICE memory.) To write a single memory page, the applicable page is selected by setting the OTP_PAGE field. To write all memory pages, the OTP_BULK bit should be set to 1. Note that Page 0 and Page 1 will be programmed during manufacture, and cannot be re-written. OTP Write is then only possible to Page 2 and Page 3. Selecting the OTP_BULK bit will select OTP Write to Page 2 and Page 3 only. Note that selecting the OTP_BULK option will cause an OTP Error to be indicated (see Section 14.5). This is because the Bulk Write to Page 0 and Page 1 is not permitted after the factory configuration of the WM8321. It is still possible to Verify the OTP Bulk Write, but the OTP_ERR_EINT flag must be cleared before doing so. The recommended procedure is to Write Page 2 and Page 3 using single page OTP Write commands. All other bits in the OTP Control Register should be set to 0 when a Write command is issued. (Note that OTP_PROG should be set to 0 when a Write command is issued.) The programming supply voltage PROGVDD is required for the OTP Write command. It is also necessary to overdrive the LDO12VOUT pin from an external supply. See Section 6 for details of the required supply voltages. For typical applications, it is recommended to Write Page 2 and Page 3 in two separate commands. The OTP Control Register contents for these OTP Write Commands are detailed in Table 21. WRITE COMMAND OTP CONTROL REGISTER VALUE OTP Write Page 2 2202h OTP Write Page 3 2203h Table 21 OTP Write Command 14.4.4 OTP VERIFY COMMAND The Verify command compares one or all data pages of the OTP with data in the corresponding page(s) of the DCRW. The Verify commands are selected by writing 1 to the OTP_VERIFY bit. The OTP memory is selected by setting the OTP_MEM bit to 1. (Note that the WM8321 does not support verifying the external ICE memory.) The Read Margin Level is selected by setting the OTP_READ_LVL. The recommended setting for the OTP Verify command is Margin 1. The OTP_READ_LVL field should be set to 10b. To verify a single memory page, the applicable page is selected by setting the OTP_PAGE field. To verify all memory pages, the OTP_BULK bit should be set to 1. All other bits in the OTP Control Register should be set to 0 when a Verify command is issued. (Note that OTP_PROG should be set to 0 when a Verify command is issued.) If the OTP Verify operation is unsuccessful (ie. the WM8321 detects a difference between the selected pages of the OTP and DCRW memories), then this is indicated by the OTP_ERR_EINT Interrupt flag, as described in Section 14.5. Note that, when Verifying the OTP after it has been Finalised, the CUST_OTP_FINAL bit needs to be set in the DCRW using a register write to R30736 prior to the OTP_VERIFY operation. This is because the OTP_FINAL command does not set the CUST_OTP_FINAL bit in the DCRW; it only sets it in the OTP memory. If the CUST_OTP_FINAL bit is not set in DCRW, then the OTP_VERIFY command will result in an OTP error indication. w PD, February 2012, Rev 4.0 54 WM8321 Production Data The OTP Control Register contents for all OTP Verify Commands are detailed in Table 22. VERIFY COMMAND OTP CONTROL REGISTER VALUE OTP Verify Page 0 2480h OTP Verify Page 1 2481h OTP Verify Page 2 2482h OTP Verify Page 3 2483h OTP Verify All 24A0h Table 22 OTP Verify Command (Margin 1) 14.4.5 OTP FINALISE COMMAND The Finalise command sets the OTP finalise bit for the user-programmable pages of the OTP memory. The Finalise commands are selected by writing 1 to the OTP_FINAL bit. Note that Page 0 and Page 1 will be programmed and finalised during manufacture; these memory pages cannot be re-written by users. Following the user Finalise command, Page 2 and Page 3 of the OTP memory will be prevented from any further OTP Write commands. Each page of the OTP memory can be programmed only once; the OTP Finalise command ensures that any subsequent Write commands will have no effect and that the OTP contents are maintained securely. The OTP memory is selected by setting the OTP_MEM bit to 1. (Note that the WM8321 does not support this function on the external ICE memory.) The Customer Finalise bit (CUST_OTP_FINAL) is in Page 2. This page is selected by setting OTP_PAGE = 10. Note that the Page 2 finalise bit locks the contents of Page 2 and Page 3. All other bits in the OTP Control Register should be set to 0 when a Finalise command is issued. (Note that OTP_PROG should be set to 0 when a Finalise command is issued.) The programming supply voltage PROGVDD is required for the OTP Finalise command. It is also necessary to overdrive the LDO12VOUT pin from an external supply. See Section 6 for details of the required supply voltages. Note that the OTP_FINAL command does not set the CUST_OTP_FINAL bit in the DCRW; it only sets it in the OTP memory. Care is required when verifying a Finalised OTP page, to avoid an OTP error indication, as described in Section 14.4.4. The OTP Control Register contents for the OTP Finalise Command is detailed in Table 23. This is the only recommended OTP Finalise Command; no variants of the Finalise Command should be used. FINALISE COMMAND OTP Finalise Page 2 OTP CONTROL REGISTER VALUE 2802h (Note that this command finalises the contents of OTP Page 2 and Page 3.) Table 23 OTP Finalise Command 14.4.6 OTP CONTROL REGISTER The OTP Control register (R16394) is defined in Table 24. Note that some of the OTP Programming registers are locked by the WM8321 User Key. These registers can only be changed by writing the appropriate code to the Security register, as described in Section 12.4. w PD, February 2012, Rev 4.0 55 WM8321 Production Data ADDRESS R16394 (400Ah) BIT 15 LABEL OTP_PROG DEFAULT 0 OTP Control DESCRIPTION Selects the PROGRAM device state. 0 = No action 1 = Select PROGRAM mode Note that, after PROGRAM mode has been selected, the chip will remain in PROGRAM mode until a Device Reset. Protected by user key 13 OTP_MEM 1 Selects ICE or OTP memory for Program commands. 0 = ICE 1 = OTP 11 OTP_FINAL 0 10 OTP_VERIFY 0 9 OTP_WRITE 0 8 OTP_READ 0 Selects READ command for the selected memory page(s). 0 = No action 1 = Read Command OTP_READ_L VL [1:0] 00 Selects the Margin Level for READ or VERIFY OTP commands. 00 = Normal 01 = Reserved 10 = Margin 1 11 = Margin 2 OTP_BULK 0 Protected by user key Selects the FINALISE command, preventing further OTP programming. 0 = No action 1 = Finalise Command Protected by user key Selects the VERIFY command for the selected OTP memory page(s). 0 = No action 1 = Verify Command Protected by user key Selects WRITE command for the selected OTP memory page(s). 0 = No action 1 = Write Command Protected by user key Protected by user key 7:6 Protected by user key 5 Selects the number of memory pages for ICE / OTP commands. 0 = Single Page 1 = All Pages 1:0 OTP_PAGE [1:0] 00 Selects the single memory page for ICE / OTP commands (when OTP_BULK=0). If OTP is selected (OTP_MEM = 1): 00 = Page 0 01 = Page 1 10 = Page 2 11 = Page 3 If ICE is selected (OTP_MEM = 0): 00 = Page 2 01 = Page 3 10 = Page 4 11 = Reserved Table 24 OTP Memory Control w PD, February 2012, Rev 4.0 56 WM8321 Production Data 14.5 OTP / ICE INTERRUPTS The OTP and ICE memories are associated with two Interrupt event flags. The OTP_CMD_END_EINT interrupt is set each time an OTP / ICE Command has completed or if OTP Auto-Program has completed. (See Section 14.4 for a definition of the OTP and ICE Commands. See Section 14.6.3 for details of the OTP Auto-Program function.) The OTP_ERR_EINT interrupt is set when an OTP / ICE Error has occurred. The errors detected include ICE Read Failure, OTP Verify Failure and attempted OTP Write to a page that has been ‘Finalised’. Each of these secondary interrupts triggers a primary OTP Memory Interrupt, OTP_INT (see Section 23). This can be masked by setting the mask bit(s) as described in Table 25. ADDRESS BIT R16402 (4012h) Interrupt Status 2 5 LABEL OTP_CMD_END_EINT DESCRIPTION OTP / ICE Command End interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 4 OTP_ERR_EINT OTP / ICE Command Fail interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. R16410 (401Ah) 5 IM_OTP_CMD_END_EINT Interrupt mask. 0 = Do not mask interrupt. Interrupt Status 2 Mask 1 = Mask interrupt. Default value is 1 (masked) 4 IM_OTP_ERR_EINT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Table 25 OTP Memory Interrupts 14.6 DCRW MEMORY CONTENTS The DCRW is the ICE/OTP Register Window, as described in Section 14.2. Under normal operating conditions, this memory area is initialised with data from the integrated OTP or an external ICE memory. The DCRW memory addresses range from R30720 (7800h) to R30759 (7827h). The complete register map definition is described in Section 28. The register fields in the DCRW allow the start-up configuration of the DC-DC Converters, the LDO Regulators, GPIO pins 1-6 and Status LED outputs to be programmed. The DCRW also provides control of selected Clocking functions and the Start-Up (SYSOK) voltage threshold. Most of the DCRW contents are duplicates of control registers that exist in the main register area below the DCRW addresses. In theses cases, reading or writing to either address will have the same effect. Some register fields are defined only in the DCRW area; a detailed description of these fields is provided in the following sub-sections. 14.6.1 DCRW PAGE 0 Page 0 of the DCRW occupies register addresses R30720 (7800h) to R30727 (7807h). This contains factory-preset data which is loaded from OTP when an ‘ON’ state transition is scheduled. Page 0 of the DCRW contains a 128-bit unique ID. Note that these fields are Read-Only in the OTP and cannot be changed. w PD, February 2012, Rev 4.0 57 WM8321 Production Data 14.6.2 DCRW PAGE 1 Page 1 of the DCRW occupies register addresses R30728 (7808h) to R30735 (780Fh). This contains factory-preset data which is loaded from OTP when an ‘ON’ state transition is scheduled. Page 1 of the DCRW contains trim parameters that ensure the accuracy of the voltage references and the power management RC oscillator. Note that these fields are Read-Only in the OTP and cannot be changed. 14.6.3 DCRW PAGE 2 Page 2 of the DCRW occupies register addresses R30736 (7810h) to R30743 (7817h). This contains user-programmable data. This page of data is normally loaded from OTP when ‘ON’ state transition is scheduled (except in Development Mode or if RECONFIG_AT_ON = 0). This page of data can also be loaded from OTP using the OTP_READ command; it can be written to the OTP using the OTP_WRITE command. This page of data is loaded from the first page of ICE memory (00h to 0Fh) when ‘ON’ state transition is scheduled in Development Mode (if RECONFIG_AT_ON = 1). This page of data can also be loaded from ICE using the ICE Read command. Note that ICE Address 00h corresponds to bits 15:8 at the start address of DCRW Page 2; ICE Address 01h corresponds to bits 7:0 at the same DCRW address. If the WM8321 configuration data is loaded from external ICE in response to an ‘ON’ state transition request, and the OTP_AUTO_PROG register bit is set, then the WM8321 will program the OTP with the contents Page 2 and Page 3 of the DCRW data, after the ICE data has been loaded and confirmed as valid. The WM8321 will also perform a Margin 1 Verify as part of the auto-program function. The programming supply voltage PROGVDD is required for the OTP_AUTO_PROG command. It is also necessary to overdrive the LDO12VOUT pin from an external supply. See Section 6 for details of the required supply voltages. Using the auto-program function described above, the OTP will be finalised if the OTP_CUST_FINAL bit is set in the ICE data. Completion of the auto-program is indicated using the OTP interrupts, as described in Section 14.5. The auto-program completion is also indicated on the Status LED outputs, as described in Section 22. The OTP_CUST_ID field is used to hold a Customer Identifier for the OTP data contents. Whenever an ‘ON’ state transition is requested, then the OTP_CUST_ID field is checked to confirm valid OTP data. If the OTP_CUST_ID field is set to zero, then the WM8321 remains in the OFF power state. A non-zero OTP_CUST_ID field is used to confirm valid OTP contents. The OTP_CUST_FINAL bit is used to control whether the user-programmable OTP data (Page 2 and Page 3) is finalised. If OTP_CUST_FINAL is set in the OTP and also set in the DCRW, then the WM8321 prevents any further Writes to the OTP. If the DCRW has been loaded from the OTP, then the OTP_CUST_FINAL bit indicates whether any further Write operations are possible. If the DCRW has been loaded from the ICE, and the OTP auto-programming option is selected (see above), then the value of the OTP_CUST_FINAL bit will be copied from the ICE memory to the OTP memory. The above registers are defined in Table 26. ADDRESS BIT LABEL DEFAULT DESCRIPTION R30736 (7810h) 15 OTP_AUTO_ PROG 0 If this bit is set when bootstrap data is loaded from ICE (in development mode), then the ICE contents will be programmed in the OTP. 14:1 OTP_CUST_ ID [13:0] 0000h 0 OTP_CUST_ FINAL 0 Customer OTP ID This field is checked when an ‘ON’ transition is requested. A non-zero value is used to confirm valid data. If OTP_CUST_FINAL is set in the OTP and also set in the DCRW, then no further Writes are possible to the OTP. Table 26 OTP Registers - DCRW Page 2 w PD, February 2012, Rev 4.0 58 WM8321 Production Data The remaining contents of DCRW Page 2 include the registers listed in Table 27, which are defined in other sections of this datasheet. REGISTER DC1_ON_SLOT [2:0] FUNCTION DC-DC Converter 1 REFERENCE See Section 15.11.2 DC1_FREQ [1:0] See Section 15.11.2 DC1_PHASE See Section 15.11.2 DC1_ON_VSEL [6:2] See Section 15.11.2 DC1_CAP [1:0] See Section 15.11.2 DC2_ON_SLOT [2:0] DC-DC Converter 2 See Section 15.11.2 DC2_FREQ [1:0] See Section 15.11.2 DC2_PHASE See Section 15.11.2 DC2_ON_VSEL [6:2] See Section 15.11.2 DC2_CAP [1:0] DC3_ON_SLOT [2:0] See Section 15.11.2 DC-DC Converter 3 See Section 15.11.2 DC3_PHASE [1:0] See Section 15.11.2 DC3_ON_VSEL [6:2] See Section 15.11.2 DC3_CAP [1:0] DC4_ON_SLOT [2:0] See Section 15.11.2 DC-DC Converter 4 See Section 15.11.2 DC4_PHASE [1:0] See Section 15.11.2 DC4_ON_VSEL [6:2] See Section 15.11.2 DC4_CAP [1:0] LDO1_ON_SLOT [2:0] See Section 15.11.2 LDO Regulator 1 LDO1_ON_VSEL [4:0] LDO2_ON_SLOT [2:0] LDO Regulator 2 LDO2_ON_VSEL [4:0] LDO3_ON_SLOT [2:0] LDO Regulator 3 LDO Regulator 4 LDO Regulator 5 LDO Regulator 6 LDO8_ON_VSEL [4:0] See Section 15.11.3 See Section 15.11.3 LDO Regulator 7 LDO7_ON_VSEL [4:0] LDO8_ON_SLOT [2:0] See Section 15.11.3 See Section 15.11.3 LDO6_ON_VSEL [4:0] LDO7_ON_SLOT [2:0] See Section 15.11.3 See Section 15.11.3 LDO5_ON_VSEL [4:0] LDO6_ON_SLOT [2:0] See Section 15.11.3 See Section 15.11.3 LDO4_ON_VSEL [4:0] LDO5_ON_SLOT [2:0] See Section 15.11.3 See Section 15.11.3 LDO3_ON_VSEL [4:0] LDO4_ON_SLOT [2:0] See Section 15.11.3 See Section 15.11.3 See Section 15.11.3 See Section 15.11.3 LDO Regulator 8 See Section 15.11.3 See Section 15.11.3 Table 27 DCRW Page 2 14.6.4 DCRW PAGE 3 Page 3 of the DCRW occupies register addresses R30744 (7818h) to R30751 (781Fh). This contains user-programmable data. This page of data is normally loaded from OTP when ‘ON’ state transition is scheduled (except in Development Mode or if RECONFIG_AT_ON = 0). This page of data can also be loaded from OTP using the OTP_READ command; it can be written to the OTP using the OTP_WRITE command. This page of data is loaded from the second page of ICE memory (10h to 1Fh) when ‘ON’ state transition is scheduled in Development Mode (if RECONFIG_AT_ON = 1). This page of data can also be loaded from ICE using the ICE Read command. Note that ICE Address 10h corresponds to bits 15:8 at the start address of DCRW Page 3; ICE Address 11h corresponds to bits 7:0 at the same DCRW address. The contents of DCRW Page 3 include the registers listed in Table 28. w PD, February 2012, Rev 4.0 59 WM8321 Production Data REGISTER LDO9_ON_SLOT [2:0] FUNCTION LDO Regulator 9 LDO9_ON_VSEL [4:0] LDO10_ON_SLOT [2:0] See Section 15.11.3 LDO Regulator 10 LDO10_ON_VSEL [4:0] LDO11_ON_SLOT [2:0] EPE1_ON_SLOT [2:0] EPE2_ON_SLOT [2:0] GP1_DIR LDO Regulator 11 See Section 15.11.3 See Section 15.11.3 DC-DC Converter 4 See Section 15.6.1 External Power Converter Enable See Section 15.11.4 GPIO1 GP1_PULL [1:0] See Section 15.11.4 See Section 21.3 See Section 21.3 GP1_INT_MODE See Section 21.3 GP1_PWR_DOM See Section 21.3 GP1_POL See Section 21.3 GP1_OD See Section 21.3 GP1_ENA See Section 21.3 GP1_FN [3:0] See Section 21.3 GP2_DIR GPIO2 GP2_PULL [1:0] See Section 21.3 See Section 21.3 GP2_INT_MODE See Section 21.3 GP2_PWR_DOM See Section 21.3 GP2_POL See Section 21.3 GP2_OD See Section 21.3 GP2_ENA See Section 21.3 GP2_FN [3:0] See Section 21.3 GP3_DIR GPIO3 GP3_PULL [1:0] See Section 21.3 See Section 21.3 GP3_INT_MODE See Section 21.3 GP3_PWR_DOM See Section 21.3 GP3_POL See Section 21.3 GP3_OD See Section 21.3 GP3_ENA See Section 21.3 GP3_FN [3:0] See Section 21.3 GP4_DIR GPIO4 GP4_PULL [1:0] See Section 21.3 See Section 21.3 GP4_INT_MODE See Section 21.3 GP4_PWR_DOM See Section 21.3 GP4_POL See Section 21.3 GP4_OD See Section 21.3 GP4_ENA See Section 21.3 GP4_FN [3:0] GP5_DIR See Section 21.3 GPIO5 GP5_PULL [1:0] See Section 21.3 See Section 21.3 GP5_INT_MODE See Section 21.3 GP5_PWR_DOM See Section 21.3 GP5_POL See Section 21.3 GP5_OD See Section 21.3 GP5_ENA See Section 21.3 GP5_FN [3:0] See Section 21.3 GP6_DIR w See Section 15.11.3 See Section 15.11.3 LDO11_ON_VSEL [3:0] DC4_SLV REFERENCE See Section 15.11.3 GPIO6 See Section 21.3 GP6_PULL [1:0] See Section 21.3 GP6_INT_MODE See Section 21.3 PD, February 2012, Rev 4.0 60 WM8321 Production Data REGISTER FUNCTION REFERENCE GP6_PWR_DOM See Section 21.3 GP6_POL See Section 21.3 GP6_OD See Section 21.3 GP6_ENA See Section 21.3 GP6_FN [3:0] See Section 21.3 CLKOUT_SLOT [2:0] Clocking See Section 13.1 XTAL_ENA See Section 13.1 XTAL_INH See Section 13.1 WDOG_ENA Watchdog Timer LED1_SRC [1:0] System Status LED Drivers LED2_SRC [1:0] See Section 25 See Section 22.2 See Section 22.2 SYSOK_THR [2:0] Supply Voltage Monitoring See Section 24.4 Table 28 DCRW Page 3 14.6.5 DCRW PAGE 4 Page 4 of the DCRW occupies register addresses R30752 (7820h) to R30759 (7827h). This page of data is loaded from the third page of ICE memory (20h to 2Fh) when ‘ON’ state transition is scheduled in Development Mode. This page of data can also be loaded from ICE using the ICE Read command. Note that ICE Address 20h corresponds to bits 15:8 at the start address of DCRW Page 4; ICE Address 21h corresponds to bits 7:0 at the same DCRW address. The ICE_VALID_DATA register is used to hold a validation field for the ICE data contents. If the WM8321 configuration data is loaded from the external ICE in response to an ‘ON’ state transition request in Development Mode, then the ICE_VALID_DATA field is checked to confirm valid ICE data. The ICE data is deemed valid if the ICE_VALID_DATA field contains the value A596h. If the ICE is not connected or contains invalid data, then the WM8321 remains in the OFF power state until a Device Reset. The ICE_VALID_DATA register is defined in Table 29. ADDRESS BIT LABEL DEFAULT R30759 (7827h) 15:0 ICE_VALID_ DATA [15:0] 0000h ICE CHECK DATA DESCRIPTION This field is checked in development mode when an ‘ON’ transition is requested. A value of A596h is required to confirm valid data. Table 29 ICE Registers - DCRW Page 5 w PD, February 2012, Rev 4.0 61 WM8321 Production Data 15 POWER MANAGEMENT 15.1 GENERAL DESCRIPTION The WM8321 provides 4 DC-DC synchronous buck converters and 11 LDO regulators. The regulators comprise general purpose LDOs (LDO1 - LDO6) and low-noise analogue LDOs (LDO7 - LDO10). The analogue LDOs offer superior PSRR, noise and load-transient performance. LDO11 is a low power LDO intended for powering “always on” circuits connected to the WM8321; this LDO can be configured to remain enabled in the OFF state. These power management components are designed to support application processors and associated peripherals. DC-DC1 and DC-DC2 are intended to provide power to the processor voltage domains; DC-DC3 is suitable for powering memory circuits or for use as a pre-regulator for the LDOs. The output voltage of each of the buck converters and regulators is programmable in software through control registers. DC-DC3 and DC-DC4 can be ganged together in dual mode, providing an increased current capability for higher power processor voltage domains. The WM8321 can execute programmable sequences of enabling and disabling the DC-DC Converters and LDO Regulators as part of the transitions between the ON, OFF and SLEEP power states. The WM8321 power management circuits can also interface with configurable hardware control functions supported via GPIO pins. These include GPIO inputs for selecting alternate voltages or operating modes, and GPIO outputs for controlling external power management circuits. The configuration of the power management circuits, together with some of the GPIO pins and other functions, may be stored in the integrated OTP memory. This avoids any dependence on a host processor to configure the WM8321 at start-up. See Section 14 for details of the OTP memory. 15.2 DC-DC CONVERTER AND LDO REGULATOR ENABLE The integrated DC-DC Converters and LDO Regulators can each be enabled in the ON or SLEEP power states by setting the DCm_ENA or LDOn_ENA bits as defined in Section 15.11.1. Note that setting the DCm_ENA or LDOn_ENA bits in the OFF state will not enable the DC-DC Converters or LDO Regulators. These bits should not be written to when the WM8321 is in the OFF state; writing to these bits in the OFF state may cause a malfunction. In many applications, there will be no need to write to the DCm_ENA or LDOn_ENA bits, as these bits are controlled by the WM8321 when a power state transition is scheduled. Dynamic, run-time control of the DC-DC Converters or LDO Regulators is also possible by writing to these registers. The DC-DC Converters and LDO Regulators can be assigned to a Hardware Enable (GPIO) input for external enable/disable control. In this case, the converter or regulator is not affected by the associated DCm_ENA or LDOn_ENA bits. See Section 15.3 for further details. The WM8321 can also control other circuits, including external DC-DC Converters or LDO Regulators using the External Power Enable (EPE) outputs. The External Power Enable outputs are alternate functions supported via GPIO - see Section 21. The External Power Enable outputs can be controlled in the same way as the internal DC-DC Converters and LDO Regulators. The associated control bits are EPE1_ENA and EPE2_ENA, as defined in Section 15.11.1. LDO Regulator 11 is a Low Power LDO Regulator, which is configured differently to the other LDOs. It is a low-power LDO intended for “Always-On” functions external to the WM8321 and can be enabled when the WM8321 is in the OFF power state. When LDO11_FRCENA is set, then LDO11 is enabled at all times in the OFF, ON and SLEEP states. Note that LDO11 is always disabled in the BACKUP and NO POWER states. See Section 15.11.3 for the definition of LDO11_FRCENA. The current commanded state of each of the DC-DC Converters, LDO Regulators and EPE outputs is indicated in the DCm_STS, LDOn_STS and EPEn_STS register bits. If a fault condition causes any converter or regulator to be disabled, then the associated _ENA and _STS fields are reset to 0. w PD, February 2012, Rev 4.0 62 WM8321 Production Data 15.3 TIMESLOT CONTROL AND HARDWARE ENABLE (GPIO) CONTROL The DC-DC Converters (1-4) and LDO Regulators (1-11) may be programmed to switch on in a selected timeslot within the ON sequence using the DCm_ON_SLOT or LDOn_ON_SLOT fields. These register fields are defined in Section 15.11.2 and Section 15.11.3. Alternatively, these fields can be used to assign a converter / regulator to one of the Hardware Enable Inputs. (The Hardware Enable Inputs are alternate functions supported via GPIO - see Section 21.) Converters / regulators which are assigned to one of the Hardware Enable Inputs are enabled or disabled according to the logic level of the respective GPIO input in the ON or SLEEP power states. The Hardware Enable Inputs are effective from the end of the ON sequence until the start of the OFF sequence. Note that the GPIO Hardware Enable function is not the same as the GPIO Hardware Control function. Any converters / regulators which are assigned to timeslots within the ON sequence will be disabled in the reverse sequence when an OFF sequence is scheduled. Any converters / regulators which are not assigned to timeslots, or are assigned to Hardware Enable Inputs, will be disabled immediately at the start of the OFF sequence. Each of the converters / regulators may also be programmed to be disabled in a selected timeslot within the SLEEP sequence using the DCm_SLP_SLOT or LDOn_SLP_SLOT fields. In the case of converters / regulators which are not disabled by the SLEEP sequence, these fields determine in which timeslot each converter or regulator enters its SLEEP configuration. Any converters / regulators which are disabled as part of the SLEEP sequence will be enabled in the reverse sequence when a WAKE transition is scheduled. By default, the OFF sequence is the reverse of the ON sequence. Similarly, the WAKE sequence is the reverse of the SLEEP sequence. If a different behaviour is required, this can be achieved by writing to the _ON_SLOT or _SLP_SLOT registers between transitions in order to re-define the sequences. Any converters / regulators which are assigned to Hardware Enable Inputs will remain under control of the Hardware Enable Inputs in the SLEEP power state. In this case, the DCm_SLP_SLOT or LDOn_SLP_SLOT fields determine in which timeslot the converter / regulator enters its SLEEP configuration. The WM8321 will control the DCm_ENA or LDOn_ENA bit (see Section 15.2) for any converter / regulator that is enabled or disabled during the power state transitions. In the case of a converter / regulator assigned to a Hardware Enable (GPIO) input, the DCm_ENA or LDOn_ENA bit is not controlled and the converter / regulator is not affected by this bit. The DC-DC converters include a soft-start feature that limits in-rush current at start-up. However, in order to further reduce supply in-rush current, it is recommended that the individual converters are programmed to start up in different time slots within the start-up sequence, as described in Section 11.3. Similarly, it is recommended that the individual LDO regulators are programmed to start up in different time slots within the start-up sequence, as described in Section 11.3. The External Power Enable (EPE) outputs, EPE1 and EPE2, may also be assigned to timeslots in the ON / SLEEP sequences or assigned to Hardware Enable inputs using the EPEn_ON_SLOT and EPEn_SLP_SLOT fields described in 15.11.4. Note that a transition from the SLEEP state to the OFF state is not a controlled transition. If an ‘OFF’ event occurs whilst in the SLEEP state, then the WM8321 will select the OFF state, but all the enabled converters and regulators will be disabled immediately; the time-controlled sequence is not implemented in this case. See Section 11.3 for details of the WM8321 ‘OFF’ events. w PD, February 2012, Rev 4.0 63 WM8321 Production Data 15.4 OPERATING MODE CONTROL 15.4.1 DC-DC SYNCHRONOUS BUCK CONVERTERS The DC-DC Converters DC-DC1 - DC-DC4 can be configured to operate in four different operating modes. The operating modes are summarised in Table 30. For more detailed information on the DCDC (Buck) Converter operating modes, see Section 15.14.2. DC-DC CONVERTER OPERATING MODE DESCRIPTION Forced Continuous Conduction Mode (FCCM) High performance mode for all static and transient load conditions. Auto Mode: Continuous / Discontinuous Conduction with Pulse-Skipping Mode (CCM/DCM with PS) High efficiency mode for all static and transient load conditions. Performance may be less than FCCM mode for heavy load transients. Hysteretic Mode High efficiency mode for light static and light transient loads only. Maximum load current is restricted; output voltage ripple is increased. LDO Mode Power saving mode for light loads only. High efficiency for ultra light loads. Low current soft-start control. Table 30 DC-DC Synchronous Buck Converter Operating Modes The operating mode of the DC-DC Converters in the ON power state is selected using the DCm_ON_MODE register fields. The operating mode of the DC-DC Converters in the SLEEP power state is selected using the DCm_SLP_MODE register fields. When changing the operating mode of the DC-DC Converters in preparation for an increased load, a set-up time of 100s should be allowed for the operating mode to be established before applying the new load. Note that the operating mode of the DC-DC Converters may also be controlled by the Hardware Control inputs. The Hardware Control inputs are alternate functions supported via GPIO. See Section 15.8 for details of Hardware Control. 15.4.2 LDO REGULATORS The LDO Regulators LDO1 - LDO10 can be configured to operate in Normal operating mode or in Low Power mode. The operating mode of the LDO Regulators in the ON power state is selected using the LDOn_ON_MODE register fields. The operating mode of the LDO Regulators in the SLEEP power state is selected using the LDOn_SLP_MODE register fields. For the standard LDOs, LDO1 - LDO6, two different Low Power modes are provided, offering limited load current capability and reduced quiescent current. When Low Power mode is selected in the ON or SLEEP power states, then the LDOn_LP_MODE register bits determine which Low Power mode is selected. Note that the operating mode and output voltage of the LDO Regulators may also be controlled by the Hardware Control inputs. The Hardware Control inputs are alternate functions supported via GPIO. See Section 15.8 for details of Hardware Control. 15.5 OUTPUT VOLTAGE CONTROL 15.5.1 DC-DC SYNCHRONOUS BUCK CONVERTERS The output voltage of the DC-DC Converters 1-4 in the ON power state is selected using the DCm_ON_VSEL register fields. The output voltage of these converters in the SLEEP power state is selected using the DCm_SLP_VSEL register fields. w PD, February 2012, Rev 4.0 64 WM8321 Production Data DC-DC Converters 1 and 2 support two different switching frequencies, as described in Section 15.6. Note that the supported output voltage range for these converters is restricted in the 4MHz mode; for output voltages greater than 1.4V, the 2MHz mode must be used. The DC-DC Converters are dynamically programmable - the output voltage may be adjusted in software at any time. These converters are step-down converters; their output voltage can therefore be lower than the input voltage, but cannot be higher. Note that the output voltage of DC-DC Converters 1 and 2 may also be controlled using the Dynamic Voltage Scaling features described in Section 15.6. Software control (using register writes) and hardware control (using the Hardware DVS Control inputs supported via GPIO) is supported. Note that the output voltage of the DC-DC Converters may also be controlled by the Hardware Control inputs. The Hardware Control inputs are alternate functions supported via GPIO. See Section 15.8 for details of Hardware Control. When changing the output voltage of DC-DC Converters 1 and 2, the GPIO output “DC-DCm DVS Done” can be used to confirm the DVS Control has completed; see Section 15.6 for details. 15.5.2 LDO REGULATORS 1-10 The output voltage of the LDO Regulators 1-10 in the ON power state is selected using the LDOn_ON_VSEL register fields. The output voltage of the LDO Regulators in the SLEEP power state is selected using the LDOn_SLP_VSEL register fields. The LDO Regulators are dynamically programmable - the output voltage may be adjusted in software at any time. Note that the output voltage of the LDO Regulators may also be controlled by the Hardware Control inputs. The Hardware Control inputs are alternate functions supported via GPIO. See Section 15.8 for details of Hardware Control. 15.5.3 LDO REGULATOR 11 The output voltage of LDO11 can be set in two ways - it can be commanded directly, or it can be commanded to follow the DC-DC Converter 1 output voltage. When LDO11_VSEL_SRC = 0, then the output voltage of LDO11 is set by LDO11_ON_VSEL (in the ON state) or by LDO11_SLP_VSEL (in the SLEEP state) in the same way as the other LDOs. When LDO11_VSEL_SRC = 1, the output voltage of LDO11 follows the output voltage of DC-DC Converter 1. This enables both domains to be changed at the same time, eg. the processor core and processor ‘alive’ domains. In this case, the LDO11 output voltage follows DC1_ON_VSEL or DC1_SLP_VSEL in the ON state or SLEEP state respectively. Note that, when LDO11_VSEL_SRC = 1, the LDO11 regulator adopts the nearest achievable output voltage, which may not be identical to the DC-DC1 voltage, due to the more limited range and resolution of LDO11 - the output voltage of LDO11 is in the range 0.8V to 1.55V in 50mV steps; the output voltage of DC-DC1 is in the range 0.6V to 1.8V in 12.5mV steps. If DC-DC1 is disabled, then the LDO11 voltage tracking feature is not supported, and the LDO11 output voltage will be 0.8V. 15.6 DC-DC SYNCHRONOUS BUCK CONVERTER CONTROL Soft-Start control is provided for each of the DC-DC synchronous buck converters, using the DCm_SOFT_START register fields. When a DC-DC Converter is switched on, the soft-start circuit will apply current limiting in order to control the in-rush current. For DC-DC1 and DC-DC2, the current limit is increased through up to 8 stages to the full load condition. The DCm_SOFT_START registers select the duration of these stages. (Note that, under light loads, the full start-up may be achieved in fewer than 8 stages.) A similar function is provided for DC-DC3 and DC-DC4, but only 3 intermediate stages are implemented for these converters. When DC-DC3 or DC-DC4 is operating in Hysteretic Mode, the maximum DC output current can be set using the DC3_STNBY_LIM and DC4_STNBY_LIM registers. See Section 15.4.1 for details of the DC-DC3 and DC-DC4 operating modes. w PD, February 2012, Rev 4.0 65 WM8321 Production Data To ensure stable operation, the register fields DCm_CAP must be set for each of the DC-DC Converters according to the output capacitance. (Note that these fields are set via OTP/ICE settings only; they cannot be changed by writing to the control register.) The choice of output capacitor is described in Section 30.3. When a DC-DC Converter is disabled, the output pin can be configured to be floating or to be actively discharged. This is selected using DCm_FLT. DC-DC Converters 1 and 2 also support selectable switching frequency. This can either be 2MHz or 4MHz, according to the DCm_FREQ register field. (Note that these fields are set via OTP/ICE settings only; they cannot be changed by writing to the control register.) The switching frequency of DC-DC3 is fixed at 2MHz. Note that the supported output voltage range for DC-DC Converters 1 and 2 is restricted in the 4MHz mode; for output voltages greater than 1.4V, the 2MHz mode must be used. The switching phase of each DC-DC converter can be set using the DCm_PHASE bits. Where two converters are operating at the same switching frequency, the supply current ripple can be minimised by selecting a different switching phase for each converter. The Dynamic Voltage Scaling (DVS) feature on DC-DC1 and DC-DC2 enables hardware or software selection of an alternate output voltage, DCm_DVS_VSEL. This may be useful if a short-term variation in output voltage is required. The DVS voltage (set by DCm_DVS_VSEL) may be selected by setting DCm_DVS_SRC = 01. Alternatively, the DVS voltage may be selected under control of one of the Hardware DVS Control inputs supported via the GPIO pins. See Section 21 for details of configuring the GPIO pins as Hardware DVS Control inputs. Whenever the DVS voltage is selected by any method, the DVS selection takes precedence over the ON, SLEEP or Hardware Control (HWC) configuration. See Section 15.8 for details of Hardware Control options. The output voltage ramp rate is selectable for DC-DC Converters 1 and 2. The DCm_RATE field selects the rate of change of output voltage, whether this is in response to an operating mode transition, or any hardware or software command. Note that the DCm_RATE field is accurate in Forced Continuous Conduction Mode (FCCM); in other modes, the actual slew rate may be longer in the case of a decreasing output voltage selection, especially under light load conditions. The WM8321 can indicate the status of the Dynamic Voltage Scaling via a GPIO pin configured as a “DC-DC1 DVS Done” or “DC-DC2 DVS Done” output (see Section 21). When a GPIO pin is configured to indicate the DVS status, this signal is temporarily de-asserted during a DVS transition on the associated DC-DC Converter, and is subsequently asserted to indicate the transition has completed. Note that the GPIO DVS outputs indicate the progress of all output voltage slews; they are not limited to transitions associated with DCm_DVS_SRC; the GPIO DVS output also indicates the status of a slew caused by a write to the DCm_ON_VSEL register, or a slew to the DCm_SLP_VSEL voltage. Note also that the GPIO DVS outputs are indicators of the DVS control mechanism only; they do not confirm the output voltage accuracy. The output voltage can be checked using the voltage status bits if required (see Section 15.2). 15.6.1 DC-DC3 / DC-DC4 DUAL MODE DC-DC Converters 3 and 4 can be configured to operate in ‘Dual’ mode, where the two converters are ganged together to support an increased current capability. In this mode, the two converters employ a common voltage feedback circuit in order to ensure the two outputs are accurately aligned.The dual mode is selected by configuring DC-DC4 as a ‘Slave’ to DC-DC3. When the DC4_SLV register is set, then DC-DC4 comes under the control of the DC-DC3 registers, and both converters are controlled together. All other DC-DC4 control registers have no effect when DC4_SLV is set. Note that the DC4_SLV register can only be controlled via OTP/ICE configuration; it cannot be changed by writing to the control register. w PD, February 2012, Rev 4.0 66 WM8321 Production Data Note that, when DC-DC3 and DC-DC4 are operating in dual mode, then discontinuous conduction mode operation is not possible. If the selected operating mode of DC-DC3 is Auto mode (Continuous / Discontinuous Conduction with Pulse Skipping), then Forced Continuous Conduction mode (FCCM) will be implemented. In Forced Continuous Conduction mode, the dual ganged converters support an increased current capability, as detailed in the Electrical Characteristics - see Section 7.1. In the Hysteretic and LDO operating modes, the current limit of the dual-ganged converters is the same as for a single buck converter, DC-DC3. 15.7 LDO REGULATOR CONTROL The LDO Regulators 1-10 can be configured to act as Current Limited Switches by setting the LDOn_SWI field. When this bit is selected, there is no voltage regulation and the operating mode and output voltage controls of the corresponding LDO are ignored. In Switch mode, the switch is enabled (closed) and disabled (opened) by enabling or disabling the LDO. Note that Switch mode cannot be selected via the OTP memory settings, and must be configured after the WM8321 has entered the ON state. When the LDO Regulator is disabled (and Switch mode is not selected), the output pin can be configured to be floating or to be actively discharged. This is selected using LDOn_FLT. 15.8 HARDWARE CONTROL (GPIO) The DC-DC Converters, LDO Regulators and EPE outputs may be controlled by the Hardware Control inputs supported via the GPIO pins. The DCm_HWC_SRC, LDOn_HWC_SRC or EPEn_HWC_SRC fields determine which of these Hardware Control inputs is effective. See Section 21 for details of configuring the GPIO pins as Hardware Control inputs. Note that the GPIO Hardware Control function is not the same as the GPIO Hardware Enable function. Hardware Control is only possible when the applicable DCm_ENA, LDOn_ENA or EPEn_ENA control bit is set (see Section 15.2), or if a Hardware Enable has been assigned to the relevant function and is asserted. The action taken in response to the selected Hardware Control inputs is configurable for each DC-DC Converter, LDO Regulator or EPE output. The available options are described below. When a Hardware Control input is assigned to a DC-DC Buck Converter, and is asserted, the operating mode and output voltage of the relevant DC-DC Converter is determined by the DCm_HWC_VSEL and DCm_HWC_MODE fields; this takes precedence over the normal ON or SLEEP settings. Note that the Hardware Control input can be used to disable a DC-DC Buck Converter if required, by setting DCm_HWC_MODE = 01. When a Hardware Control input is assigned to LDO Regulators 1-10, and is asserted, the operating mode and output voltage of the relevant LDO Regulators is determined by the LDOn_HWC_VSEL and LDOn_HWC_MODE fields; this takes precedence over the normal ON or SLEEP settings. Note that, for the standard LDOs (LDO1 - LDO6), when Low Power Mode is selected (LDOn_HWC_MODE = 00 or 10), then the Low Power mode type is determined by the LDOn_LP_MODE register bits. When a Hardware Control input is assigned to the External Power Enable (EPE) outputs, and is asserted, the relevant EPE outputs are controlled as determined by the EPEn_HWC_ENA field; this takes precedence over the normal ON or SLEEP settings. The available options are to de-assert the EPE, or for the EPE to remain under control of EPEn_ENA. w PD, February 2012, Rev 4.0 67 WM8321 Production Data 15.9 FAULT PROTECTION Each of the DC-DC Buck Converters (1 to 4) is monitored for voltage accuracy and fault conditions. An undervoltage condition is set if the output voltage falls below the required level by more than the applicable undervoltage margin, as specified in Section 7.1. Each LDO Regulator (1 to 10) is monitored for voltage accuracy and fault conditions. An undervoltage condition is set if the output voltage falls below the required level by more than the undervoltage margin, as specified in Section 7.2. The DCm_ERR_ACT and LDOn_ERR_ACT fields configure the fault response to an Undervoltage condition. An Interrupt is always triggered under this condition (see Section 15.12); additional action can also be selected independently for each converter / regulator. The options are to ignore the fault, shut down the converter, or to shut down the system. To prevent false alarms during short current surges, faults are only signalled if the fault condition persists. If a fault condition is detected, and the selected response is to shut down the converter or regulator, then the associated _ENA and _STS fields are reset to 0, as described in Section 15.2. If a fault condition is detected, and the selected response is to shut down the system, then a Device Reset is triggered, as described in Section 24.1, forcing a transition to the OFF state. The WM8321 will automatically return to the ON state after performing the Device Reset. Note that, if the fault condition persists, then a maximum of 6 Device Resets will be attempted to initiate the start-up sequence. If the sequence fails more than 6 times, the WM8321 will remain in the OFF state until the next valid ON state transition event occurs. Note that DC-DC1 and DC-DC2 overvoltage and high current conditions can be detected and reported as described in Section 15.10. The DCm_ERR_ACT fields have no relation to these conditions. The DC-DC3 and DC-DC4 Converters have a selectable overvoltage protection feature, controlled by DC3_OVP or DC4_OVP. This affects the converter response when the applicable converter is enabled or when its output voltage is increased. When the overvoltage protection is enabled, there is less overshoot in the output voltage, but some oscillation may occur as the voltage settles. This function should only be enabled if steep load transients are present on the output of the DC-DC Converter and if voltage overshoot is critical. 15.10 MONITORING AND FAULT REPORTING Each of the DC-DC Converters (1 to 4) and LDOs (1 to 10) is monitored for voltage accuracy and fault conditions. An undervoltage condition is detected if the voltage falls below the required level by more than a pre-determined tolerance. If an undervoltage condition occurs, then this is indicated using the corresponding status bit(s) defined in Section 15.11.5. An undervoltage condition also triggers an Undervoltage Interrupt (see Section 15.12). Additional actions to shut down the converter or perform a Device Reset may also be selected. The Internal LDO (LDO13) is also monitored for voltage accuracy and fault conditions. An undervoltage condition in LDO13 is indicated using the INTLDO_UV_STS bit. This undervoltage condition also causes an OFF transition to be scheduled, as described in Section 11.3. DC-DC Converters 1 and 2 are monitored for overvoltage conditions. An overvoltage condition is set if the voltage is more than 100mV above the required level. If an overvoltage condition occurs, then this is indicated using the corresponding status bit(s). Note that there is no Interrupt or other selectable response to an overvoltage condition. The current draw on DC-DC Converters 1 and 2 can be monitored against user-programmable thresholds in order to detect a high current condition. This feature is enabled using DCm_HC_IND_ENA and the current threshold is set using DCm_HC_THR. Note that the high current threshold is not the same as the maximum current capability of the DC-DC Converters, but is set according to the application requirements. If a high current condition occurs, then this is indicated using the corresponding status bit(s). A high current condition also triggers a High Current Interrupt (see Section 15.12). w PD, February 2012, Rev 4.0 68 WM8321 Production Data 15.11 POWER MANAGEMENT REGISTER DEFINITIONS 15.11.1 DC-DC CONVERTER AND LDO REGULATOR ENABLE The Enable and Status register bits for the DC-DC Converters and LDO Regulators are defined in Table 31. ADDRESS BIT LABEL R16464 (4050h) 3:0 DCm_ENA DEFAULT 0 DCDC Enable DESCRIPTION DC-DCm Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in DCm_STS) R16465 (4051h) 10:0 LDOn_ENA 0 LDO Enable LDOn Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in LDOn_STS) R16466 (4052h) 3:0 DCm_STS 0 DCDC Status DC-DCm Status 0 = Disabled 1 = Enabled R16467 (4053h) 10:0 LDOn_STS 0 LDO Status LDOn Status 0 = Disabled 1 = Enabled Notes: 1. n is a number between 1 and 11 that identifies the individual LDO Regulator. 2. m is a number between 1 and 4 that identifies the individual DC-DC Converter. Table 31 DC-DC Converter and LDO Regulator Control The Enable and Status register bits for the External Power Enable (EPE) Controls are defined in Table 32. ADDRESS BIT R16464 (4050h) 7 LABEL DEFAULT EPE2_ENA 0 DCDC Enable DESCRIPTION EPE2 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in EPE2_STS) 6 EPE1_ENA 0 EPE1 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in EPE1_STS) R16466 (4052h) 7 EPE2_STS 0 DCDC Status EPE2 Status 0 = Disabled 1 = Enabled 6 EPE1_STS 0 EPE1 Status 0 = Disabled 1 = Enabled Table 32 External Power Enable (EPE) Control 15.11.2 DC-DC SYNCHRONOUS BUCK CONVERTER CONTROL The register controls for configuring the DC-DC synchronous buck converters 1-4 are defined in Table 33. Note that the DCm_ON_SLOT fields and the 5 MSBs of DCm_ON_VSEL may also be stored in the integrated OTP memory. See Section 14 for details. w PD, February 2012, Rev 4.0 69 WM8321 Production Data ADDRESS BIT R16470 (4056h) 15:14 DC1 Control 1 LABEL DC1_RATE [1:0] DEFAULT 10 DESCRIPTION DC-DC1 Voltage Ramp rate 00 = 1 step every 32us 01 = 1 step every 16us 10 = 1 step every 8us 11 = Immediate voltage change 12 DC1_PHASE 0 DC-DC1 Clock Phase Control 0 = Normal 1 = Inverted 9:8 DC1_FREQ [1:0] 00 DC-DC1 Switching Frequency 00 = Reserved 01 = 2.0MHz (2.2uH output inductor) 10 = 4.0MHz (1uH output inductor) 11 = 4.0MHz (0.5uH output inductor) This field can only be written to by loading configuration settings from OTP/ICE. In all other cases, this field is Read Only. 7 DC1_FLT 0 DC-DC1 Output float 0 = DC-DC1 output discharged when disabled 1 = DC-DC1 output floating when disabled 5:4 DC1_SOFT_ START [1:0] 00 DC-DC1 Soft-Start Control (Duration in each of the 8 startup current limiting steps.) 00 = 32us steps 01 = 64us steps 10 = 128us steps 11 = 256us steps 1:0 DC1_CAP [1:0] 00 DC-DC1 Output Capacitor 00 = 4.7uF to 20uF 01 = Reserved 10 = 22uF to 47uF 11 = Reserved This field can only be written to by loading configuration settings from OTP/ICE. In all other cases, this field is Read Only. R16471 (4057h) 15:14 DC1 Control 2 DC1_ERR_A CT [1:0] 00 DC-DC1 Error Action (Undervoltage) 00 = Ignore 01 = Shut down converter 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. 12:11 DC1_HWC_ SRC [1:0] 00 DC-DC1 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 10 DC1_HWC_ VSEL 0 DC-DC1 Hardware Control Voltage select 0 = Set by DC1_ON_VSEL 1 = Set by DC1_SLP_VSEL w PD, February 2012, Rev 4.0 70 WM8321 Production Data ADDRESS BIT LABEL DEFAULT DESCRIPTION 9:8 DC1_HWC_ MODE [1:0] 11 DC-DC1 Hardware Control Operating Mode 00 = Forced Continuous Conduction Mode 01 = Disabled 10 = LDO Mode 11 = Hysteretic Mode 6:4 DC1_HC_TH R [2:0] 000 DC-DC1 High Current threshold 000 = 125mA 001 = 250mA 010 = 375mA 011 = 500mA 100 = 625mA 101 = 750mA 110 = 875mA 111 = 1000mA 0 DC1_HC_IN D_ENA 0 DC1_ON_SL OT [2:0] 000 DC-DC1 High Current detect enable 0 = Disabled 1 = Enabled R16472 (4058h) 15:13 DC1 ON Config DC-DC1 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 9:8 DC1_ON_M ODE [1:0] 00 DC-DC1 ON Operating Mode 00 = Forced Continuous Conduction Mode 01 = Auto Mode (Continuous / Discontinuous Conduction with PulseSkipping) 10 = LDO Mode 11 = Hysteretic Mode 6:2 w DC1_ON_VS EL [6:2] 00000 DC-DC1 ON Voltage select PD, February 2012, Rev 4.0 71 WM8321 Production Data ADDRESS BIT LABEL DEFAULT DESCRIPTION 1:0 DC1_ON_VS EL [1:0] 00 DC1_ON_VSEL[6:0] selects the DCDC1 output voltage from 0.6V to 1.8V in 12.5mV steps. DC1_ON_VSEL[6:2] also exist in ICE/OTP memory, controlling the voltage in 50mV steps. DC1_ON_VSEL[6:0] is coded as follows: 00h to 08h = 0.6V 09h = 0.6125V … 48h = 1.4V (see note) … 67h = 1.7875V 68h to 7Fh = 1.8V Note - Maximum output voltage selection in 4MHz switching mode is 48h (1.4V). R16473 (4059h) 15:13 DC1 SLEEP Control DC1_SLP_S LOT [2:0] 000 DC-DC1 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If DC-DC1 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the converter enters its SLEEP condition. 9:8 DC1_SLP_M ODE [1:0] 00 DC-DC1 SLEEP Operating Mode 00 = Forced Continuous Conduction Mode 01 = Auto Mode (Continuous / Discontinuous Conduction with PulseSkipping) 10 = LDO Mode 11 = Hysteretic Mode 6:0 DC1_SLP_V SEL [6:0] 000_0000 DC-DC1 SLEEP Voltage select 0.6V to 1.8V in 12.5mV steps 00h to 08h = 0.6V 09h = 0.6125V … 48h = 1.4V (see note) … 67h = 1.7875V 68h to 7Fh = 1.8V Note - Maximum output voltage selection in 4MHz switching mode is 48h (1.4V). w PD, February 2012, Rev 4.0 72 WM8321 Production Data ADDRESS BIT LABEL DEFAULT R16474 (405Ah) 12:11 DC1_DVS_S RC [1:0] 00 DC1 DVS Control DESCRIPTION DC-DC1 DVS Control Source 00 = Disabled 01 = Enabled 10 = Controlled by Hardware DVS1 11 = Controlled by Hardware DVS2 6:0 DC1_DVS_V SEL [6:0] 000_0000 DC-DC1 DVS Voltage select 0.6V to 1.8V in 12.5mV steps 00h to 08h = 0.6V 09h = 0.6125V … 48h = 1.4V (see note) … 67h = 1.7875V 68h to 7Fh = 1.8V Note - Maximum output voltage selection in 4MHz switching mode is 48h (1.4V). R16475 (405Bh) 15:14 DC2 Control 1 DC2_PHASE 0 Same as DC-DC1 DC2_FREQ [1:0] 00 Same as DC-DC1 DC2_FLT 0 Same as DC-DC1 5:4 DC2_SOFT_ START [1:0] 00 Same as DC-DC1 1:0 DC2_CAP [1:0] 00 Same as DC-DC1 15:14 DC2_ERR_A CT [1:0] 00 Same as DC-DC1 12:11 DC2_HWC_ SRC [1:0] 00 Same as DC-DC1 10 DC2_HWC_ VSEL 0 Same as DC-DC1 9:8 DC2_HWC_ MODE [1:0] 11 Same as DC-DC1 6:4 DC2_HC_TH R [2:0] 000 Same as DC-DC1 0 DC2_HC_IN D_ENA 0 Same as DC-DC1 15:13 DC2_ON_SL OT [2:0] 000 Same as DC-DC1 9:8 DC2_ON_M ODE [1:0] 00 Same as DC-DC1 6:2 DC2_ON_VS EL [6:2] 00000 Same as DC-DC1 1:0 DC2_ON_VS EL [1:0] 00 15:13 DC2_SLP_S LOT [2:0] 000 Same as DC-DC1 9:8 DC2_SLP_M ODE [1:0] 00 Same as DC-DC1 6:0 DC2_SLP_V SEL [6:0] 000_0000 Same as DC-DC1 12:11 DC2_DVS_S RC [1:0] 00 Same as DC-DC1 DC2 ON Config R16478 (405Eh) DC2 SLEEP Control R16479 (405Fh) w Same as DC-DC1 12 DC2 Control 2 R16477 (405Dh) 10 9:8 7 R16476 (405Ch) DC2_RATE [1:0] PD, February 2012, Rev 4.0 73 WM8321 Production Data BIT LABEL DEFAULT DC2 DVS Control ADDRESS 6:0 DC2_DVS_V SEL [6:0] 000_0000 Same as DC-DC1 R16480 (4060h) 12 DC3_PHASE 0 Same as DC-DC1 DC3 Control 1 7 DC3_FLT 0 Same as DC-DC1 DC3_SOFT_ START [1:0] 01 DC-DC3 Soft-Start Control 5:4 DESCRIPTION (Duration in each of the 3 intermediate startup current limiting steps.) 00 = Immediate start-up 01 = 512us steps 10 = 4.096ms steps 11 = 32.768ms steps 3:2 DC3_STNBY _LIM [1:0] 01 DC-DC3 Current Limit Sets the maximum DC output current in Hysteretic Mode. 00 = 50mA 01 = 100mA 10 = 200mA 11 = 400mA Protected by user key 1:0 DC3_CAP [1:0] 00 DC-DC3 Output Capacitor 00 = 10uF to 20uF 01 = 10uF to 20uF 10 = 22uF to 45uF 11 = 47uF to 100uF This field can only be written to by loading configuration settings from OTP/ICE. In all other cases, this field is Read Only. R16481 (4061h) 15:14 DC3_ERR_A CT [1:0] 00 Same as DC-DC1 12:11 DC3_HWC_ SRC [1:0] 00 Same as DC-DC1 10 DC3_HWC_ VSEL 0 Same as DC-DC1 9:8 DC3_HWC_ MODE [1:0] 11 Same as DC-DC1 DC3_OVP 0 DC-DC3 Overvoltage Protection DC3 Control 2 7 0 = Disabled 1 = Enabled R16482 (4062h) 15:13 DC3_ON_SL OT [2:0] 000 Same as DC-DC1 9:8 DC3_ON_M ODE [1:0] 00 Same as DC-DC1 6:2 DC3_ON_VS EL [6:2] 00000 DC3 ON Config w DC-DC3 ON Voltage select PD, February 2012, Rev 4.0 74 WM8321 Production Data ADDRESS BIT LABEL DEFAULT 1:0 DC3_ON_VS EL [1:0] 00 DESCRIPTION DC3_ON_VSEL[6:0] selects the DCDC3 output voltage from 0.85V to 3.4V in 25mV steps. DC3_ON_VSEL[6:2] also exist in ICE/OTP memory, controlling the voltage in 100mV steps. DC3_ON_VSEL[6:0] is coded as follows: 00h = 0.85V 01h = 0.875V … 65h = 3.375V 66h to 7Fh = 3.4V R16483 (4063h) DC3 SLEEP Control 15:13 DC3_SLP_S LOT [2:0] 000 Same as DC-DC1 9:8 DC3_SLP_M ODE [1:0] 00 Same as DC-DC1 6:0 DC3_SLP_V SEL [6:0] 000_0000 DC-DC3 SLEEP Voltage select 0.85V to 3.4V in 25mV steps 00h = 0.85V 01h = 0.875V … 65h = 3.375V 66h to 7Fh = 3.4V R16484 (4064h) 13 DC4_SLV 0 DC4 Control 1 DC-DC4 Slave Mode select 0 = Disabled 1 = Enabled DC4_SLV = 1, then DC-DC4 is a slave to DC-DC3, and both converters are controlled by the DCDC3 registers. This field can only be written to by loading configuration settings from OTP/ICE. In all other cases, this field is Read Only. R16485 (4065h) 12 DC4_PHASE 0 7 DC4_FLT 0 Same as DC-DC1 5:4 DC4_SOFT_ START [1:0] 01 Same as DC-DC3 3:2 DC4_STNBY _LIM [1:0] 01 Same as DC-DC3 1:0 DC4_CAP [1:0] 00 Same as DC-DC3 15:14 DC4_ERR_A CT [1:0] 00 Same as DC-DC1 12:11 DC4_HWC_ SRC [1:0] 00 Same as DC-DC1 10 DC4_HWC_ VSEL 0 Same as DC-DC1 9:8 DC4_HWC_ MODE [1:0] 11 Same as DC-DC1 DC4 Control 2 7 R16486 (4066h) 0 Same as DC-DC3 15:13 DC4_ON_SL OT [2:0] 000 Same as DC-DC1 9:8 DC4_ON_M ODE [1:0] 00 Same as DC-DC1 DC4 ON Config w DC4_OVP Same as DC-DC1 PD, February 2012, Rev 4.0 75 WM8321 Production Data ADDRESS R16487 (4067h) DC4 SLEEP Control BIT LABEL DEFAULT 6:2 DC4_ON_VS EL [6:2] 00000 Same as DC-DC3 DESCRIPTION 1:0 DC4_ON_VS EL [1:0] 00 Same as DC-DC3 15:13 DC4_SLP_S LOT [2:0] 000 Same as DC-DC1 9:8 DC4_SLP_M ODE [1:0] 00 Same as DC-DC1 6:0 DC4_SLP_V SEL [6:0] 000_0000 Same as DC-DC3 Table 33 DC-DC Converter Control 15.11.3 LDO REGULATOR CONTROL The register controls for configuring the LDO Regulators 1-6 are defined in Table 34. Note that the LDOn_ON_SLOT and LDOn_ON_VSEL fields may also be stored in the integrated OTP memory. See Section 14 for details. ADDRESS BIT LABEL DEFAULT R16488 (4068h) 15:14 LDO1_ERR_ ACT [1:0] 00 LDO1 Control DESCRIPTION LDO1 Error Action (Undervoltage) 00 = Ignore 01 = Shut down regulator 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. 12:11 LDO1_HWC _SRC [1:0] 00 LDO1 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 10 LDO1_HWC _VSEL 0 LDO1 Hardware Control Voltage select 0 = Set by LDO1_ON_VSEL 1 = Set by LDO1_SLP_VSEL 9:8 LDO1_HWC _MODE 10 LDO1 Hardware Control Operating Mode 00 = Low Power mode 01 = Turn converter off 10 = Low Power mode 11 = Set by LDO1_ON_MODE 7 LDO1_FLT 0 LDO1 Output float 0 = LDO1 output discharged when disabled 1 = LDO1 output floating when disabled 6 LDO1_SWI 0 LDO1 Switch Mode 0 = LDO mode 1 = Switch mode w PD, February 2012, Rev 4.0 76 WM8321 Production Data ADDRESS BIT LABEL DEFAULT 0 LDO1_LP_M ODE 0 DESCRIPTION LDO1 Low Power Mode Select 0 = 50mA (reduced quiescent current) 1 = 20mA (minimum quiescent current) Selects which Low Power mode is used in ON, SLEEP, or under HWC modes. R16489 (4069h) 15:13 LDO1 ON Control LDO1_ON_S LOT [2:0] 000 LDO1 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 8 LDO1_ON_ MODE 0 LDO1 ON Operating Mode 0 = Normal mode 1 = Low Power mode 4:0 LDO1_ON_V SEL [4:0] 00000 LDO1 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V … 0Eh = 1.60V 0Fh = 1.70V … 1Eh = 3.20V 1Fh = 3.30V R16490 (406Ah) 15:13 LDO1 SLEEP Control LDO1_SLP_ SLOT [2:0] 000 LDO1 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO1 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. 8 LDO1_SLP_ MODE 0 LDO1 SLEEP Operating Mode 0 = Normal mode 1 = Low Power mode w PD, February 2012, Rev 4.0 77 WM8321 Production Data ADDRESS BIT LABEL DEFAULT 4:0 LDO1_SLP_ VSEL [4:0] 00000 DESCRIPTION LDO1 SLEEP Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V … 0Eh = 1.60V 0Fh = 1.70V … 1Eh = 3.20V 1Fh = 3.30V R16491 (406Bh) 15:14 LDO2_ERR_ ACT [1:0] 00 Same as LDO1 12:11 LDO2_HWC _SRC [1:0] 00 Same as LDO1 10 LDO2_HWC _VSEL 0 Same as LDO1 9:8 LDO2_HWC _MODE 10 Same as LDO1 7 LDO2_FLT 0 Same as LDO1 6 LDO2_SWI 0 Same as LDO1 0 LDO2_LP_M ODE 0 Same as LDO1 15:13 LDO2_ON_S LOT [2:0] 000 Same as LDO1 0 Same as LDO1 LDO2 Control R16492 (406Ch) LDO2 ON Control R16493 (406Dh) LDO2 SLEEP Control R16494 (406Eh) 8 4:0 LDO2_ON_V SEL [4:0] 00000 Same as LDO1 15:13 LDO2_SLP_ SLOT [2:0] 000 Same as LDO1 8 LDO2_SLP_ MODE 0 Same as LDO1 4:0 LDO2_SLP_ VSEL [4:0] 00000 Same as LDO1 15:14 LDO3_ERR_ ACT [1:0] 00 Same as LDO1 12:11 LDO3_HWC _SRC [1:0] 00 Same as LDO1 10 LDO3_HWC _VSEL 0 Same as LDO1 9:8 LDO3_HWC _MODE 10 Same as LDO1 7 LDO3_FLT 0 Same as LDO1 6 LDO3_SWI 0 Same as LDO1 0 LDO3_LP_M ODE 0 Same as LDO1 15:13 LDO3_ON_S LOT [2:0] 000 Same as LDO1 0 Same as LDO1 LDO3 Control R16495 (406Fh) LDO3 ON Control R16496 (4070h) w LDO2_ON_ MODE 8 LDO3_ON_ MODE 4:0 LDO3_ON_V SEL [4:0] 00000 Same as LDO1 15:13 LDO3_SLP_ SLOT [2:0] 000 Same as LDO1 PD, February 2012, Rev 4.0 78 WM8321 Production Data ADDRESS LDO3 SLEEP Control R16497 (4071h) BIT LABEL DEFAULT 8 LDO3_SLP_ MODE 0 Same as LDO1 4:0 LDO3_SLP_ VSEL [4:0] 00000 Same as LDO1 15:14 LDO4_ERR_ ACT [1:0] 00 Same as LDO1 12:11 LDO4_HWC _SRC [1:0] 00 Same as LDO1 10 LDO4_HWC _VSEL 0 Same as LDO1 9:8 LDO4_HWC _MODE 10 Same as LDO1 7 LDO4_FLT 0 Same as LDO1 6 LDO4_SWI 0 Same as LDO1 0 LDO4_LP_M ODE 0 Same as LDO1 15:13 LDO4_ON_S LOT [2:0] 000 Same as LDO1 0 Same as LDO1 LDO4 Control R16498 (4072h) LDO4 ON Control R16499 (4073h) LDO4 SLEEP Control R16500 (4074h) 8 4:0 LDO4_ON_V SEL [4:0] 00000 Same as LDO1 15:13 LDO4_SLP_ SLOT [2:0] 000 Same as LDO1 8 LDO4_SLP_ MODE 0 Same as LDO1 4:0 LDO4_SLP_ VSEL [4:0] 00000 Same as LDO1 15:14 LDO5_ERR_ ACT [1:0] 00 Same as LDO1 12:11 LDO5_HWC _SRC [1:0] 00 Same as LDO1 10 LDO5_HWC _VSEL 0 Same as LDO1 9:8 LDO5_HWC _MODE 10 Same as LDO1 7 LDO5_FLT 0 Same as LDO1 6 LDO5_SWI 0 Same as LDO1 0 LDO5_LP_M ODE 0 Same as LDO1 15:13 LDO5_ON_S LOT [2:0] 000 Same as LDO1 0 Same as LDO1 LDO5 Control R16501 (4075h) LDO5 ON Control R16502 (4076h) LDO5 SLEEP Control R16503 (4077h) 8 LDO5_ON_ MODE 4:0 LDO5_ON_V SEL [4:0] 00000 Same as LDO1 15:13 LDO5_SLP_ SLOT [2:0] 000 Same as LDO1 8 LDO5_SLP_ MODE 0 Same as LDO1 4:0 LDO5_SLP_ VSEL [4:0] 00000 Same as LDO1 15:14 LDO6_ERR_ ACT [1:0] 00 Same as LDO1 12:11 LDO6_HWC _SRC [1:0] 00 Same as LDO1 10 LDO6_HWC _VSEL 0 Same as LDO1 LDO6 Control w LDO4_ON_ MODE DESCRIPTION PD, February 2012, Rev 4.0 79 WM8321 Production Data ADDRESS R16504 (4078h) LDO6 ON Control R16505 (4079h) LDO6 SLEEP Control BIT LABEL DEFAULT 9:8 LDO6_HWC _MODE 10 Same as LDO1 7 LDO6_FLT 0 Same as LDO1 6 LDO6_SWI 0 Same as LDO1 0 LDO6_LP_M ODE 0 Same as LDO1 15:13 LDO6_ON_S LOT [2:0] 000 Same as LDO1 0 Same as LDO1 8 LDO6_ON_ MODE DESCRIPTION 4:0 LDO6_ON_V SEL [4:0] 00000 Same as LDO1 15:13 LDO6_SLP_ SLOT [2:0] 000 Same as LDO1 8 LDO6_SLP_ MODE 0 Same as LDO1 4:0 LDO6_SLP_ VSEL [4:0] 00000 Same as LDO1 Table 34 LDO Regulators 1-6 Control The register controls for configuring the LDO Regulators 7-10 are defined in Table 35. Note that the LDOn_ON_SLOT and LDOn_ON_VSEL fields may also be stored in the integrated OTP memory. See Section 14 for details. ADDRESS BIT LABEL DEFAULT R16506 (407Ah) 15:14 LDO7_ERR_ ACT [1:0] 00 LDO7 Control DESCRIPTION LDO7 Error Action (Undervoltage) 00 = Ignore 01 = Shut down regulator 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. 12:11 LDO7_HWC _SRC [1:0] 00 LDO7 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 10 LDO7_HWC _VSEL 0 LDO7 Hardware Control Voltage select 0 = Set by LDO7_ON_VSEL 1 = Set by LDO7_SLP_VSEL 9:8 LDO7_HWC _MODE 00 LDO7 Hardware Control Operating Mode 00 = Low Power mode 01 = Turn converter off 10 = Low Power mode 11 = Set by LDO7_ON_MODE 7 LDO7_FLT 0 LDO7 Output float 0 = LDO7 output discharged when disabled 1 = LDO7 output floating when disabled w PD, February 2012, Rev 4.0 80 WM8321 Production Data ADDRESS BIT 6 LABEL LDO7_SWI DEFAULT 0 DESCRIPTION LDO7 Switch Mode 0 = LDO mode 1 = Switch mode R16507 (407Bh) 15:13 LDO7 ON Control LDO7_ON_S LOT [2:0] 000 LDO7 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 8 LDO7_ON_ MODE 0 LDO7 ON Operating Mode 0 = Normal mode 1 = Low Power mode 4:0 LDO7_ON_V SEL [4:0] 00000 LDO7 ON Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V … 0Ch = 1.60V 0Dh = 1.70V … 1Eh = 3.40V 1Fh = 3.50V R16508 (407Ch) 15:13 LDO7 SLEEP Control LDO7_SLP_ SLOT [2:0] 000 LDO7 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO7 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. 8 LDO7_SLP_ MODE 0 LDO7 SLEEP Operating Mode 0 = Normal mode 1 = Low Power mode w PD, February 2012, Rev 4.0 81 WM8321 Production Data ADDRESS BIT LABEL DEFAULT 4:0 LDO7_SLP_ VSEL [4:0] 00000 DESCRIPTION LDO7 SLEEP Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V … 0Ch = 1.60V 0Dh = 1.70V … 1Eh = 3.40V 1Fh = 3.50V R16509 (407Dh) 15:14 LDO8_ERR_ ACT [1:0] 00 Same as LDO7 12:11 LDO8_HWC _SRC [1:0] 00 Same as LDO7 10 LDO8_HWC _VSEL 0 Same as LDO7 9:8 LDO8_HWC _MODE 00 Same as LDO7 7 LDO8_FLT 0 Same as LDO7 6 LDO8_SWI 0 Same as LDO7 000 Same as LDO7 0 Same as LDO7 LDO8 Control R16510 (407Eh) LDO8 ON Control R16511 (407Fh) LDO8 SLEEP Control R16512 (4080h) 15:13 8 LDO9 ON Control R16514 (4082h) LDO9 SLEEP Control w LDO8_ON_ MODE 4:0 LDO8_ON_V SEL [4:0] 00000 Same as LDO7 15:13 LDO8_SLP_ SLOT [2:0] 000 Same as LDO7 8 LDO8_SLP_ MODE 0 Same as LDO7 4:0 LDO8_SLP_ VSEL [4:0] 00000 Same as LDO7 15:14 LDO9_ERR_ ACT [1:0] 00 Same as LDO7 12:11 LDO9_HWC _SRC [1:0] 00 Same as LDO7 10 LDO9_HWC _VSEL 0 Same as LDO7 9:8 LDO9_HWC _MODE 00 Same as LDO7 7 LDO9_FLT 0 Same as LDO7 6 LDO9_SWI 0 Same as LDO7 000 Same as LDO7 0 Same as LDO7 LDO9 Control R16513 (4081h) LDO8_ON_S LOT [2:0] 15:13 8 LDO9_ON_S LOT [2:0] LDO9_ON_ MODE 4:0 LDO9_ON_V SEL [4:0] 00000 Same as LDO7 15:13 LDO9_SLP_ SLOT [2:0] 000 Same as LDO7 8 LDO9_SLP_ MODE 0 Same as LDO7 4:0 LDO9_SLP_ VSEL [4:0] 00000 Same as LDO7 PD, February 2012, Rev 4.0 82 WM8321 Production Data ADDRESS BIT LABEL DEFAULT R16515 (4083h) 15:14 LDO10_ERR _ACT [1:0] 00 Same as LDO7 12:11 LDO10_HW C_SRC [1:0] 00 Same as LDO7 10 LDO10_HW C_VSEL 0 Same as LDO7 9:8 LDO10_HW C_MODE 00 Same as LDO7 7 LDO10_FLT 0 Same as LDO7 6 LDO10_SWI 0 Same as LDO7 15:13 LDO10_ON_ SLOT [2:0] 000 Same as LDO7 8 LDO10_ON_ MODE 0 Same as LDO7 4:0 LDO10_ON_ VSEL [4:0] 00000 Same as LDO7 R16517 (4085h) 15:13 LDO10_SLP _SLOT [2:0] 000 Same as LDO7 LDO10 SLEEP Control 8 LDO10_SLP _MODE 0 Same as LDO7 4:0 LDO10_SLP _VSEL [4:0] 00000 Same as LDO7 LDO10 Control R16516 (4084h) LDO10 ON Control DESCRIPTION Table 35 LDO Regulators 7-10 Control The register controls for configuring the LDO Regulator 11 are defined in Table 36. Note that the LDO11_ON_SLOT and LDO11_ON_VSEL fields may also be stored in the integrated OTP memory. See Section 14 for details. ADDRESS BIT LABEL DEFAULT R16519 (4087h) 15:13 LDO11_ON_ SLOT [2:0] 000 LDO11 ON Control DESCRIPTION LDO11 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 12 LDO11_FRC ENA 0 LDO11 Force Enable (forces LDO11 to be enabled at all times in the OFF, ON and SLEEP states) 0 = Disabled 1 = Enabled 7 LDO11_VSE L_SRC 0 LDO11 Voltage Select source 0 = Normal (LDO11 settings) 1 = Same as DC-DC Converter 1 w PD, February 2012, Rev 4.0 83 WM8321 Production Data ADDRESS BIT LABEL 3:0 LDO11_ON_ VSEL [3:0] DEFAULT DESCRIPTION LDO11 ON Voltage select 0.80V to 1.55V in 50mV steps 0h = 0.80V 1h = 0.85V 2h = 0.90V … Eh = 1.50V Fh = 1.55V R16520 (4088h) 15:13 LDO11 SLEEP Control LDO11_SLP _SLOT [2:0] 000 LDO11 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO11 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. 3:0 LDO11_SLP _VSEL [3:0] LDO11 SLEEP Voltage select 0.80V to 1.55V in 50mV steps 0h = 0.80V 1h = 0.85V 2h = 0.90V … Eh = 1.50V Fh = 1.55V Table 36 LDO Regulator 11 Control 15.11.4 EXTERNAL POWER ENABLE (EPE) CONTROL The register controls for configuring the External Power Enable (EPE) outputs are defined in Table 37. Note that the EPE1_ON_SLOT and EPE2_ON_SLOT fields may also be stored in the integrated OTP memory. See Section 14 for details. ADDRESS BIT LABEL DEFAULT R16521 (4089h) 15:13 EPE1_ON_S LOT [2:0] 000 EPE1 Control DESCRIPTION EPE1 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 w PD, February 2012, Rev 4.0 84 WM8321 Production Data ADDRESS BIT LABEL DEFAULT 12:11 EPE1_HWC _SRC [1:0] 00 DESCRIPTION EPE1 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 8 EPE1_HWC ENA 0 EPE1 Hardware Control Enable 0 = EPE1 is controlled by EPE1_ENA (Hardware Control input(s) are ignored) 1 = EPE1 is controlled by HWC inputs (Hardware Control input(s) force EPE1 to be de-asserted) EPE1_SLP_ SLOT [2:0] 000 EPE1 SLEEP Slot select 15:13 EPE2_ON_S LOT [2:0] 000 000 = No action 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = No action 111 = No action Same as EPE1 12:11 EPE2_HWC _SRC [1:0] 00 Same as EPE1 8 EPE2_HWC ENA 0 Same as EPE1 7:5 EPE2_SLP_ SLOT [2:0] 000 Same as EPE1 7:5 R1652 (408Ah) EPE2 Control Table 37 External Power Enable (EPE) Control 15.11.5 MONITORING AND FAULT REPORTING The overvoltage, undervoltage and high current status registers are defined in Table 38. ADDRESS BIT LABEL DEFAULT R16468 (4054h) 13 DC2_OV_ST S 0 DC1_OV_ST S 0 DC2_HC_ST S 0 DC1_HC_ST S 0 DCm_UV_S TS 0 INTLDO_UV _STS 0 DCDC UV Status DESCRIPTION DC-DC2 Overvoltage Status 0 = Normal 1 = Overvoltage 12 DC-DC1 Overvoltage Status 0 = Normal 1 = Overvoltage 9 DC-DC2 High Current Status 0 = Normal 1 = High Current 8 DC-DC1 High Current Status 0 = Normal 1 = High Current 3:0 DC-DCm Undervoltage Status 0 = Normal 1 = Undervoltage R16469 (4055h) LDO UV Status 15 LDO13 (Internal LDO) Undervoltage Status 0 = Normal 1 = Undervoltage w PD, February 2012, Rev 4.0 85 WM8321 Production Data ADDRESS BIT LABEL DEFAULT 9:0 LDOn_UV_S TS 0 DESCRIPTION LDOn Undervoltage Status 0 = Normal 1 = Undervoltage Notes: 1. n is a number between 1 and 10 that identifies the individual LDO Regulator (LDO1 - 10). 2. m is a number between 1 and 4 that identifies the individual DC-DC Converter (DC-DC1 - 4). Table 38 DC Converter and LDO Regulator Status 15.12 POWER MANAGEMENT INTERRUPTS Undervoltage monitoring is provided on all DC-DC Converters and LDO Regulators, as described in Section 15.10. The associated interrupt flags indicate an undervoltage condition in each individual DC-DC Converter or LDO Regulator. Each of these secondary interrupts triggers a primary Undervoltage Interrupt, UV_INT (see Section 23). This can be masked by setting the mask bit(s) as described in Table 39. Current monitoring is provided on DC-DC1 and DC-DC2, as described in Section 15.10. The interrupt flags HC_DC1_EINT and HC_DC2_EINT indicate a high current condition in DC-DC1 and DC-DC2 respectively. Each of these secondary interrupts triggers a primary High Current Interrupt, HC_INT (see Section 23). This can be masked by setting the mask bit(s) as described in Table 39. The high current thresholds are programmable; these are set by DC1_HC_THR and DC2_HC_THR for DC-DC1 and DC-DC2 respectively. See Section 15.11.2 for details of these register fields. Note that these functions are for current monitoring; they do not equate to the DC-DC Converter maximum current limit. ADDRESS R16403 (4013h) BIT 9:0 LABEL UV_LDOn_EINT (Rising Edge triggered) Interrupt Status 3 R16404 (4014h) Interrupt Status 4 DESCRIPTION LDOn Undervoltage interrupt Note: Cleared when a ‘1’ is written. 9 HC_DC2_EINT DC-DC2 High current interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 8 HC_DC1_EINT DC-DC1 High current interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 3:0 UV_DCm_EINT DC-DCm Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. R16411 (401Bh) 9:0 IM_UV_LDOn_EINT 0 = Do not mask interrupt. Interrupt Status 3 Mask R16412 (401Ch) Interrupt mask. 1 = Mask interrupt. Default value is 1 (masked) 9 IM_HC_DC2_EINT Interrupt mask. 0 = Do not mask interrupt. Interrupt Status 4 Mask 1 = Mask interrupt. Default value is 1 (masked) 8 IM_HC_DC1_EINT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 3:0 IM_UV_DCm_EINT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. w PD, February 2012, Rev 4.0 86 WM8321 Production Data ADDRESS BIT LABEL DESCRIPTION Default value is 1 (masked) Notes: 1. n is a number between 1 and 10 that identifies the individual LDO Regulator (LDO1 - 10). 2. m is a number between 1 and 4 that identifies the individual DC-DC Converter (DC-DC1 - 4). Table 39 Power Management Interrupts 15.13 POWER GOOD INDICATION The WM8321 can indicate the status of the DC-DC Converters and LDO Regulators via a GPIO pin configured as a “PWR_GOOD” output (see Section 21). Each DC-DC Converter and LDO Regulator to be monitored in this way must be individually enabled as an input to the PWR_GOOD function using the register bits defined in Table 40. When a GPIO pin is configured as a “PWR_GOOD” output, this signal is asserted when all selected DC-DC Converters and LDO Regulators are operating correctly. If any of the enabled DC-DC Converters or LDO Regulators is undervoltage, then the PWR_GOOD will be de-asserted. In this event, the host processor should read the Undervoltage Interrupt fields to determine which DC-DC Converter or LDO Regulator is affected. Note that an Undervoltage condition may lead to a Converter being switched off automatically. In this case, the disabled Converter will not indicate the fault condition via PWR_GOOD. Accordingly, the PWR_GOOD signal may not be a reliable output in cases where the WM8321 is configured to shut down any Converters automatically under Undervoltage conditions. It is recommended that the host processor should read the Undervoltage Interrupts in response to PWR_GOOD being de-asserted. The host processor can then initiate the most appropriate response. w PD, February 2012, Rev 4.0 87 WM8321 Production Data ADDRESS R16526 (408Eh) BIT DEFAULT DESCRIPTION 3 DC4_OK LABEL 0 2 DC3_OK 1 1 DC2_OK 1 0 DC1_OK 1 9 LDO10_OK 1 8 LDO9_OK 1 7 LDO8_OK 1 6 LDO7_OK 1 5 LDO6_OK 1 4 LDO5_OK 1 3 LDO4_OK 1 2 LDO3_OK 1 1 LDO2_OK 1 0 LDO1_OK 1 DC-DC4 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled DC-DC3 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled DC-DC2 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled DC-DC1 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO10 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO9 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO8 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO7 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO6 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO5 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO4 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO3 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO2 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO1 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled Power Good Source 1 R16527 (408Fh) Power Good Source 2 Table 40 PWR_GOOD (GPIO) Configuration w PD, February 2012, Rev 4.0 88 WM8321 Production Data 15.14 DC-DC SYNCHRONOUS BUCK CONVERTER OPERATION 15.14.1 OVERVIEW The WM8321 provides four DC-DC switching converters. Each of these is a synchronous buck (stepdown) converter. The principal characteristics of each DC-DC converter are shown below. Converters DC-DC3 and DC-DC4 can either be operated as single converters, or may be ganged together in ‘dual’ mode to provide an increased current capability. DC-DC1 / DC-DC2 Converter Type Buck (step-down) DC-DC3 / DC-DC4 DC-DC3 / DC-DC4 (SINGLE MODE) (DUAL MODE) Buck (step-down) Buck (step-down) Input Voltage Range 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V Output Voltage Range 0.6V to 1.8V 0.85V to 3.4V 0.85V to 3.4V Load Current Rating Up to 1250mA Up to 1000mA Up to 1600mA Switching Frequency 2MHz or 4MHz 2MHz 2MHz Table 41 DC-DC Converter Overview 15.14.2 DC-DC SYNCHRONOUS BUCK CONVERTERS DC-DC Converters 1, 2, 3 and 4 are synchronous buck converters which deliver high performance and high efficiency across a wide variety of operating conditions. The high switching frequency, together with the current mode architecture, delivers exceptional transient performance suitable for supplying processor power domains and similar applications requiring high stability through fast-changing load (or line) conditions. The current mode architecture enables extended bandwidth of the control loop, allowing the DC-DC converter to adapt for changes in input or output conditions more rapidly than can be achieved using other feedback mechanisms. This improves the converter’s performance under transient load conditions. The flexible design of the DC-DC Converters allows a selection of different operating configurations, which can be chosen according to the performance, efficiency, space or external component cost requirements. The DC-DC Converter design achieves high performance with a small inductor component. This is highly advantageous in size-critical designs for portable applications. In the case of DC-DC1 and DCDC2, the switching frequency is selectable (2MHz or 4MHz). The higher frequency supports best transient performance and the smallest external inductor, whilst the lower rate supports best power efficiency. It should be noted that the supported output voltage range is restricted in the 4MHz mode; for output voltages greater than 1.4V, the 2MHz mode must be used. The DC-DC Converters are compatible with a range of external output capacitors. A larger capacitor (eg. 47F) will deliver best transient performance, whilst a smaller capacitor (eg. 4.7F) may be preferred for size or cost reasons. Four different operating modes can be selected, allowing the user to configure the converter performance and efficiency according to different demands. This includes power-saving modes for light load conditions and a high performance mode for best transient load performance. A low power LDO regulator mode is also provided. The DC-DC Converters maintain output voltage regulation when switching between operating modes. Forced Continuous Conduction Mode (FCCM) This mode delivers the best load transient performance across the entire operating load range of the converter. It also provides the best EMI characteristics due to the fixed, regular switching pattern. For normal DC-DC buck converter operation, there is an inductor charging phase followed by a discharging phase. Under light load conditions, the inductor current may be positive or negative during this cycle. (Note that the load current corresponds to the average inductor current.) The negative portion of the cycle corresponds to inefficient operation, as the output capacitor is discharged unnecessarily by the converter circuit. Accordingly, this mode is not optimally efficient for light load conditions. w PD, February 2012, Rev 4.0 89 WM8321 Production Data This mode offers excellent performance under transient load conditions. It exceeds the performance of the other operating modes in the event of a decreasing current demand or a decreasing voltage selection. This is because FCCM mode can actively pull down the output voltage to the required level, whilst other modes rely on the load to pull the converter voltage down under these conditions. Another important benefit of this mode is that the switching pattern is fixed, regardless of load conditions. This provides best compatibility with noise-sensitive circuits where the noise frequency spectrum must be well-defined. Although this mode is not optimally efficient for light loads, it delivers the best possible transient load performance and fixed frequency switching. This mode should be selected when best performance is required, delivering minimum output voltage ripple across all static or transient load conditions. Auto Mode: Continuous / Discontinuous Conduction with Pulse-Skipping (CCM/DCM with PS) This is an automatic mode that selects different control modes according to the load conditions. The converter supports the full range of load conditions in this mode, and automatically selects powersaving mechanisms when the load conditions are suitable. Under light load conditions, the efficiency in this mode is superior to the FCCM mode. The transient load performance may be slightly worse than FCCM mode. The converter operates in Continuous Conduction Mode (CCM) for heavy load conditions, and Discontinuous Conduction Mode (DCM) under lighter loads. Discontinuous conduction is when the inductor current falls to zero during the discharge phase, and the converter disables the synchronous rectifier transistor in order that the inductor current remains at zero until the next charge phase. Negative inductor current is blocked in this mode, eliminating the associated losses, and improving efficiency. The transient response in this mode varies according to the operating conditions; it differs from FCCM in the case of a decreasing current demand or a decreasing voltage, as the converter uses the load to pull the output voltage down to the required level. A light load will result in a slow response time. A minimum inductor charge time is applied in DCM mode; this leads to a minimum average inductor current when operating as described above. Under very light load conditions, pulse skipping is used to reduce the average inductor current to the level required by the load. In pulse-skipping mode, the charge phase of selected cycles is not scheduled, and the load is supported by the output capacitor over more than one cycle of the switching frequency. As well as supporting very light load current conditions, this mechanism offers power savings, as the switching losses associated with the skipped pulses are eliminated. A disadvantage of this is that the transient response is degraded even further with respect to DCM. When the pulse-skipping behaviour is invoked, an increased output voltage ripple may be observed under some load conditions. This mode is suitable for a wide range of operating conditions. It supports the full range of load currents, and offers efficiency savings under light load conditions. Hysteretic Mode Hysteretic mode is a power-saving mode. It does not support the full load capability of the DC-DC converter, but offers efficiency improvements over the FCCM and Auto (CCM/DCM with PS) modes. The control circuit in Hysteretic mode operates very differently to the Pulse-Skipping mode that is available in Auto mode. In Pulse-Skipping mode, selected switching cycles are dropped in order to reduce the output current to match a light load condition, whilst maintaining good output voltage ripple as far as possible. In Hysteretic mode, the converter uses switched operation on an adaptive intermittent basis to deliver the required average current to the load. In the switched operation portion of the Hysteretic mode, the converter drives the output voltage up; this is followed by a power-saving period in which the control circuit is largely disabled whilst the load pulls the output voltage down again over a period of many switching cycles. The duration of the fixed frequency bursts and the time between bursts is adapted automatically by the output voltage monitoring circuit. w PD, February 2012, Rev 4.0 90 WM8321 Production Data In this mode, the power dissipation is reduced to a very low level by disabling parts of the control circuitry for the duration of selected switching cycles. This improves the overall efficiency, but also leads to output voltage ripple and limited performance. This mode produces a larger output voltage ripple than the Pulse-Skipping mode. In order to limit the degradation of the DC-DC converter performance in Hysteretic mode, the control circuit is designed for a restricted range of load conditions only. Note that the irregular switching pattern also results in degraded EMI behaviour. Hysteretic mode and Pulse Skipping mode are both Pulse Frequency Modulation (PFM)-type modes, where the switching pulse frequency is adjusted dynamically according to the load requirements. A consequence of this frequency modulation is that the circuit’s EMI characteristics are less predictable. In Hysteretic mode in particular, the EMI effects arising from the DC-DC switching are present across a wider frequency band than is the case in CCM and DCM. It is more difficult to effectively suppress the wide band interference, and this factor may result in Hysteretic mode being unsuitable for some operating conditions. Hysteretic mode is suitable for light load conditions only, and only suitable for operating modes that are not sensitive to wide band RF/EMI effects. The output voltage ripple (and frequency) is load dependent, and is generally worse than Pulse-Skipping operation in the Auto mode. Provided that the EMI and voltage ripple can be tolerated, the Hysteretic mode offers an efficiency advantage over the Auto (CCM/DCM with PS) mode. LDO Mode In this mode, there is no FET switching at all, and the converter operates as a Low Drop-Out (LDO) regulator. In this mode, the FET switching losses are eliminated, as is the power consumption of the DC-DC control circuit. Under suitable operating conditions, this provides the most efficient option for light loads, without any of the EMI or voltage ripple limitations of Hysteretic mode. As with any LDO, the output voltage is constant, and there is no internal source of voltage ripple. Unlike the switching modes, the power efficiency of the LDO mode is highly dependent on the input and output voltages; the LDO is most efficient when the voltage drop between input and output is small. The power dissipated as heat loss by an LDO increases rapidly as the input - output voltage difference increases. LDO mode is suitable for light loads, and provides a ripple-free output. The LDO mode features a very low start-up current; this mode can be used to avoid the higher in-rush current that occurs in the switching converter modes. The efficiency is dependent on the input - output voltage configuration; the LDO mode can be highly efficient, but may also be unacceptably inefficient. If an improvement in power efficiency is required, then Hysteretic mode may be the preferred choice or, for better EMI and voltage ripple, the Auto (CCM/DCM with PS) mode may be the optimum selection. Operating Mode Summary MODE DESCRIPTION APPLICATION Forced Continuous Conduction Mode (FCCM) Buck converter operation where inductor current is continuous at all times. High performance for all static and transient load conditions. Fixed frequency switching offers best compatibility with sensitive circuits. Auto Mode: Continuous / Discontinuous Conduction with Pulse-Skipping Mode (CCM/DCM with PS) Buck converter operation where inductor current may be discontinuous under reduced loads; pulse-skipping also enabled under lighter loads. High efficiency for all static and transient load conditions. Performance may be less than FCCM mode for heavy load transients. Hysteretic Mode The converter uses a hysteretic control scheme with pulsed switching operation. The control circuitry is disabled intermittently for power saving. High efficiency for light static and light transient loads only. Maximum load current is restricted; output voltage ripple is increased. LDO Mode No FET switching at all; linear regulator operation. Power saving mode for light loads only. High efficiency for ultra light loads. Low current soft-start control. Table 42 DC-DCSynchronous Buck Converter Operating Modes Summary w PD, February 2012, Rev 4.0 91 WM8321 Production Data Typical Connections The typical connections to DC-DC Converter 1 are illustrated in Figure 20. The equivalent circuit applies to DC-DC Converters 2, 3 and 4 also. The input voltage connection to DC-DC Converters 1-4 is provided on DC1VDD, DC2VDD, DC3VDD and DC3VDD respectively; these pins must be connected to the PVDD power supply voltage node. Figure 20 DC-DC Synchonous Buck Converter Connections The recommended output capacitor COUT varies according to the required transient response. Note that the DCm_CAP register field must be set according to the output capacitance on each DC-DC Converter in order to achieve best performance. In the case of DC-DC1 and DC-DC2, the recommended inductor component varies according to the DCm_FREQ register field. This register allows a choice of different switching frequencies and inductor components. See Section 30.3 for details of specific recommended external components. DC-DC3 / DC-DC4 Dual Mode DC-DC Converters 3 and 4 can be configured to operate in ‘Dual’ mode, where the two converters are ganged together to support an increased current capability. This mode is selected by setting the DC4_SLV bit in the OTP/ICE memory configuration registers. When DC-DC3 and DC-DC4 are operating in dual mode, the external component configuration for each converter is the same as previously noted for single converters. The output load connection points (Vo) are simply connected together as shown in Figure 21. w PD, February 2012, Rev 4.0 92 WM8321 Production Data 2.7V – 5.5V DC3VDD DC3FB CIN DC3LX L VO COUT DC3GND WM8321 DC4_SLV = 1 DC4VDD DC4FB CIN DC4LX L VO COUT Load DC4GND Figure 21 DC-DC3 / DC-DC4 Dual Mode Converter Connections The recommended output capacitor COUT varies according to the required transient response. Note that the DCm_CAP register field must be set according to the output capacitance on each DC-DC Converter in order to achieve best performance. See Section 30.3 for details of specific recommended external components. 15.15 LDO REGULATOR OPERATION 15.15.1 OVERVIEW The WM8321 provides 11 LDO Regulators. Four of these are low-noise analogue LDOs. One of the LDO Regulators (LDO11) can be configured to be enabled even when the WM8321 is in the OFF state. The principal characteristics of the LDO Regulators are shown below. Converter Type Input Voltage Range LDO1 LDO2, 3 LDO4, 5, 6 LDO7, 8 LDO9, 10 LDO11 General Purpose General Purpose General Purpose Analogue Analogue General Purpose 1.71V to 5.5V 1.71V to 5.5V 1.8V to 5.5V 1.5V to 5.5V 1.5V to 5.5V 1.5V to 5.5V Output Voltage Range 0.9V to 3.3V 0.9V to 3.3V 0.9V to 3.3V 1.0V to 3.5V 1.0V to 3.5V 0.8V to 1.55V Load Current Rating Up to 300mA Up to 200mA Up to 100mA Up to 200mA Up to 150mA Up to 25mA Pass device impedance @ 2.5V 1 1 2 1 2 n/a Table 43 LDO Regulator Overview w PD, February 2012, Rev 4.0 93 WM8321 Production Data 15.15.2 LDO REGULATORS The LDO Regulators are configurable circuits which generate accurate, low-noise supply voltages for various system components. The LDO Regulators are dynamically programmable and can be reconfigured at any time. Two low power modes are provided for the general purpose LDOs 1-6; a single low power mode is provided for the analogue LDOs 7-10; this enables the overall device power consumption to be minimised at all times. The LDOs 1-10 can also operate as current-limited switches, with no voltage regulation; this is useful for ‘Hot Swap’ outputs, i.e. supply rails for external devices that are plugged in when the system is already powered up - the current-limiting function prevents the in-rush current into the external device from disturbing other system power supplies. The input voltage to these LDOs is provided on pins LDO3VDD, LDO4VDD, LDO5VDD, LDO6VDD for LDO3 through to LDO6 respectively. The other LDO inputs are shared on pins LDO1_2VDD, LDO7_8VDD and LDO9_10VDD for each corresponding pair of LDOs. The LDO input supply pins may be connected to the PVDD power supply voltage node, or else can be connected to the output pin of one of the DC-DC buck converters. Note that the LDO input supply pins must not be connected to a voltage higher than PVDD. LDO11 is a configurable LDO intended for ‘always-on’ functions external to the WM8321. The WM8321 contains a further two non-configurable LDOs which support internal functions only. The connections to LDO Regulator 1 are illustrated in Figure 22. The equivalent circuit applies to LDO2 through to LDO10. Figure 22 LDO Regulator Connections An input and output capacitor are recommended for each LDO Regulator, as illustrated above. See Section 30.4 for details of specific recommended external components. w PD, February 2012, Rev 4.0 94 Production Data WM8321 16 RESERVED w PD, February 2012, Rev 4.0 95 WM8321 Production Data 17 POWER SUPPLY CONTROL 17.1 GENERAL DESCRIPTION The primary power supply to the WM8321 is provided via the PVDD pin. This supply is required for normal device functionality. The PVDD voltage is monitored internally to detect a low voltage condition where the device can no longer operate. A Power Path Management Interrupt is raised when PVDD falls below an undervoltage threshold, as described in Section 17.2. A backup power source may be provided for the WM8321. This enables the Real Time Clock (RTC) and other selected registers to be maintained when PVDD is not available. This is described in Section 17.3. 17.2 POWER PATH MANAGEMENT INTERRUPTS The Power Path Management circuit is associated with an Interrupt event flag. The PPM_SYSLO_EINT interrupt bit is set when the internal signal SYSLO is asserted. This indicates a PVDD undervoltage condition, described in Section 24.4. This secondary interrupt triggers a primary Power Path Management Interrupt, PPM_INT (see Section 23). This can be masked by setting the mask bit as described in Table 44. ADDRESS R16401 (4011h) BIT 15 LABEL PPM_SYSLO_EINT (Rising Edge triggered) Interrupt Status 1 R16409 (4019h) DESCRIPTION Power Path SYSLO interrupt Note: Cleared when a ‘1’ is written. 15 IM_PPM_SYSLO_EINT Interrupt Status 1 Mask Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Table 44 Power Path Management Interrupt 17.3 BACKUP POWER As an option, a backup power source can be provided for the WM8321. This is provided using a coin cell, super/gold capacitor, or else a standard capacitor, connected to the LDO12VOUT pin. Note that a 22kΩ series resistor should also be connected to the backup power source. The LDO12VOUT pin provides a constant voltage output for charging the backup power source whenever the PVDD power domain is available. The purpose of the backup is to power the always-on functions such as the crystal oscillator, RTC and ALARM control registers. The backup power also maintains a ‘software scratch’ memory area in the register map - see Section 12.6. Maintaining these functions at all times provides system continuity even when the main battery is removed and no other power supply is available. The backup duration will vary depending upon the backup power source characteristics. A typical coin cell can provide power to the WM8321 in BACKUP mode for a month or more whilst also maintaining the RTC and the ‘software scratch’ register. If a standard capacitor is used as the backup power source, then it is particularly important to minimise the device power consumption in the BACKUP state. A 22F capacitor will maintain the device settings for up to 5 minutes in ‘unclocked’ mode, where power consumption is minimised by stopping the RTC in the BACKUP state. The RTC is unclocked in the BACKUP state if the XTAL_BKUPENA register field is set to 0, as described in Section 20.5. w PD, February 2012, Rev 4.0 96 WM8321 Production Data 18 AUXILIARY ADC 18.1 GENERAL DESCRIPTION The WM8321 incorporates a 12-bit Auxiliary ADC (AUXADC). This can be used to perform a number of system measurements (including supply voltages and battery temperature) and can also be used to measure analogue voltages from external sources and sensors. External inputs to the AUXADC should be connected to the pins GPIO10, GPIO11 and GPIO12. The maximum voltage that can be measured is determined by the power domain associated with each; this is selectable on a pin by pin basis as described in Section 21.3. Note that, when GPIO10, GPIO11 or GPIO12 is used as an input to the AUXADC, then the normal GPIO functionality cannot be supported on the affected pin(s). In this case, it is recommended that the respective GPIO(s) are tri-stated, as described in Section 21.3. 18.2 AUXADC CONTROL The AUXADC is enabled by setting the AUX_ENA register bit. By default, the AUXADC is not enabled in the SLEEP state, but this can be selected using the AUX_SLPENA field. The AUXADC measurements can be initiated manually or automatically. For automatic operation, the AUX_RATE register is set according to the required conversion rate, and conversions are enabled by setting the AUX_CVT_ENA bit. For manual operation, the AUX_RATE register is set to 00h, and each manual conversion is initiated by setting the AUX_CVT_ENA bit. In manual mode, the AUX_CVT_ENA bit is reset by the WM8321 after each conversion. (Note that the conversion result is not available for readback until the AUXADC interrupt is asserted, as described in Section 18.5.) The AUXADC has 5 available input sources. Each of these inputs is enabled by setting the respective bit in the AuxADC Source Register (R16431). For each AUXADC measurement event (in Manual or Automatic modes), the WM8321 selects the next enabled input source. Any number of inputs may be selected simultaneously; the AUXADC will measure each one in turn. Note that only a single AUXADC measurement is made on any Manual or Automatic trigger. For example, if the GPIO10, GPIO12 and PVDD voltages are enabled for AUXADC measurement, then GPIO10 would be measured in the first instance, and GPIO12 then PVDD would be measured on the next manual or automatic AUXADC triggers. In this case, a total of three manual or automatic AUXADC triggers would be required to measure all of the selected inputs. The control fields associated with initiating AUXADC measurements are defined in Table 45. ADDRESS R16430 (402Eh) BIT 15 LABEL AUX_ENA DEFAULT 0 DESCRIPTION AUXADC Enable 0 = Disabled AuxADC Control 1 = Enabled Note - this bit is reset to 0 when the OFF power state is entered. 14 AUX_CVT_ENA 0 AUXADC Conversion Enable 0 = Disabled 1 = Enabled In automatic mode, conversions are enabled by setting this bit. In manual mode (AUX_RATE = 0), setting this bit will initiate a conversion; the bit is reset automatically after each conversion. 12 AUX_SLPENA 0 AUXADC SLEEP Enable 0 = Disabled 1 = Controlled by AUX_ENA w PD, February 2012, Rev 4.0 97 WM8321 Production Data ADDRESS BIT 5:0 LABEL AUX_RATE [5:0] DEFAULT 00_0000 DESCRIPTION AUXADC Conversion Rate 0 = Manual 1 = 2 samples/s 2 = 4 samples/s 3 = 6 samples/s … 31 = 62 samples/s 32 = Reserved 33 = 16 samples/s 34 = 32 samples/s 35 = 48 samples/s … 63 = 496 samples/s R16431 (402Fh) AuxADC Source 6 AUX_PVDD_SEL 0 AUXADC PVDD input select 0 = Disable PVDD measurement 1 = Enable PVDD measurement 4 AUX_CHIP_TEM P_SEL 0 AUX_GPIO12_SE L 0 AUXADC Chip Temp input select 0 = Disable Chip Temp measurement 1 = Enable Chip Temp measurement 2 AUXADC GPIO12 input select 0 = Disable GPIO12 measurement 1 = Enable GPIO12 measurement 1 AUX_GPIO11_SE L 0 AUXADC GPIO11 input select 0 = Disable GPIO11 measurement 1 = Enable GPIO11 measurement 0 AUX_GPIO10_SE L 0 AUXADC GPIO10 input select 0 = Disable GPIO10 measurement 1 = Enable GPIO10 measurement Table 45 AUXADC Control w PD, February 2012, Rev 4.0 98 WM8321 Production Data 18.3 AUXADC READBACK Measured data from the AUXADC is read via the AuxADC Data Register (R16429), which contains two fields. The AUXADC Data Source is indicated in the AUX_DATA_SRC field; the associated measurement data is contained in the AUX_DATA field. Reading from the AuxADC Data Register returns a 12-bit code which represents the most recent AUXADC measurement on the associated channel. It should be noted that every time an AUXADC measurement is written to the AuxADC Data Register, the previous data is overwritten - the host processor should ensure that data is read from this register before it is overwritten. The AUXADC interrupts can be used to indicate when new data is available - see Section 18.5. The 12-bit AUX_DATA field can be equated to the actual voltage (or temperature) according to the following equations, where AUX_DATA is regarded as an unsigned integer: The maximum voltage that can be measured on the input pins GPIO10, GPIO11 and GPIO12 is determined by the power domain associated with each; this is selectable on a pin by pin basis using the GPn_PWR_DOM register bits described in Section 21.3. The input voltage at the GPIO pin must not exceed the voltage of the respective power domain (ie. DBVDD or PVDD). In a typical application, it is anticipated that the AUXADC Interrupts would be used to control the AUXADC readback - the host processor should read the AUXADC Data Register in response to the AUXADC Interrupt event. See Section 18.5 for details of AUXADC Interrupts. In Automatic AUXADC mode, the processor should complete this action before the next measurement occurs, in order to avoid losing any AUXADC samples. In Manual conversion mode, the interrupt signal provides confirmation that the commanded measurement has been completed. The control fields associated with initiating AUXADC readback are defined in Table 46. ADDRESS R16429 (402Dh) BIT LABEL DEFAULT 15:12 AUX_DATA_SRC [3:0] 000 DESCRIPTION AUXADC Data Source 1 = GPIO10 AuxADC Data 2 = GPIO11 3 = GPIO12 5 = Chip Temperature 7 = PVDD voltage All other values are Reserved 11:0 AUX_DATA [11:0] 000h AUXADC Measurement Data Voltage (mV) = AUX_DATA x 1.465 ChipTemp (C) = (498 - AUX_DATA) / 1.09 Table 46 AUXADC Readback w PD, February 2012, Rev 4.0 99 WM8321 Production Data 18.4 DIGITAL COMPARATORS The WM8321 has four digital comparators which may be used to compare AUXADC measurement data against programmable threshold values. Each comparator has a status bit, and also an associated interrupt flag (described in Section 18.5), which indicates that the associated data is beyond the threshold value. The digital comparators are enabled using the DCMPn_ENA register bits as described in Table 45. After an AUXADC conversion, the measured value is compared with the threshold level of any associated comparator(s). Note that this comparison is only performed following a conversion. The source data for each comparator is selected using the DCMPn_SRC register bits; this selects one of the AUXADC channels for each comparator. If required, the same AUXADC channel may be selected for more than one comparator; this would allow more than one threshold to be monitored on the same AUXADC channel. Note that the Backup Battery voltage input can only be monitored using DCMP4. The DCMPn_GT register bits select whether the status bit and associated interrupt flag will be asserted when the measured value is above the threshold or when the measured value is below the threshold. The output of the most recent threshold comparison is indicated in the DCOMPn_STS fields. The threshold DCMPn_THR is a 12-bit code for each comparator. This field follows the same voltage or temperature coding as the associated AUXADC channel source (see Section 18.3). ADDRESS BIT LABEL DEFAULT R16432 (4030h) 11 DCOMP4_STS 0 Comparator Control DESCRIPTION Digital Comparator 4 status 0 = Comparator 4 threshold not detected 1 = Comparator 4 threshold detected (Trigger is controlled by DCMP4_GT) 10 DCOMP3_STS 0 Digital Comparator 3 status 0 = Comparator 3 threshold not detected 1 = Comparator 3 threshold detected (Trigger is controlled by DCMP3_GT) 9 DCOMP2_STS 0 Digital Comparator 2 status 0 = Comparator 2 threshold not detected 1 = Comparator 2 threshold detected (Trigger is controlled by DCMP2_GT) 8 DCOMP1_STS 0 Digital Comparator 1 status 0 = Comparator 1 threshold not detected 1 = Comparator 1 threshold detected (Trigger is controlled by DCMP1_GT) 3 DCMP4_ENA 0 Digital Comparator 4 Enable 0 = Disabled 1 = Enabled 2 DCMP3_ENA 0 Digital Comparator 3 Enable 0 = Disabled 1 = Enabled 1 DCMP2_ENA 0 Digital Comparator 2 Enable 0 = Disabled 1 = Enabled 0 DCMP1_ENA 0 Digital Comparator 1 Enable 0 = Disabled 1 = Enabled R16433 (4031h) w 15:13 DCMP1_SRC [2:0] 000 Digital Comparator 1 source select PD, February 2012, Rev 4.0 100 WM8321 Production Data ADDRESS BIT LABEL DEFAULT Comparator 1 DESCRIPTION 0 = Reserved 1 = GPIO10 2 = GPIO11 3 = GPIO12 4 = Reserved 5 = Chip Temperature 6 = Reserved 7 = PVDD voltage 12 DCMP1_GT 0 Digital Comparator 1 interrupt control 0 = interrupt when less than threshold 1 = interrupt when greater than or equal to threshold 11:0 DCMP1_THR 000h Digital Comparator 1 threshold (12-bit unsigned binary number; coding is the same as AUX_DATA) R16434 (4032h) 15:13 Comparator 2 DCMP2_SRC [2:0] 000 Digital Comparator 2 source select 0 = Reserved 1 = GPIO10 2 = GPIO11 3 = GPIO12 4 = Reserved 5 = Chip Temperature 6 = Reserved 7 = PVDD voltage 12 DCMP2_GT 0 Digital Comparator 2 interrupt control 0 = interrupt when less than threshold 1 = interrupt when greater than or equal to threshold 11:0 DCMP2_THR 000h Digital Comparator 2 threshold (12-bit unsigned binary number; coding is the same as AUX_DATA) R16435 (4033h) 15:13 Comparator 3 DCMP3_SRC [2:0] 000 Digital Comparator 3 source select 0 = Reserved 1 = GPIO10 2 = GPIO11 3 = GPIO12 4 = Reserved 5 = Chip Temperature 6 = Reserved 7 = PVDD voltage 12 DCMP3_GT 0 Digital Comparator 3 interrupt control 0 = interrupt when less than threshold 1 = interrupt when greater than or equal to threshold 11:0 DCMP3_THR 000h Digital Comparator 3 threshold (12-bit unsigned binary number; coding is the same as AUX_DATA) R16436 (4034h) Comparator 4 15:13 DCMP4_SRC [2:0] 000 Digital Comparator 4 source select 0 = Backup Battery voltage 1 = GPIO10 2 = GPIO11 3 = GPIO12 w PD, February 2012, Rev 4.0 101 WM8321 Production Data ADDRESS BIT LABEL DEFAULT DESCRIPTION 4 = Reserved 5 = Chip Temperature 6 = Reserved 7 = PVDD voltage 12 DCMP4_GT 0 Digital Comparator 4 interrupt control 0 = interrupt when less than threshold 1 = interrupt when greater than or equal to threshold 11:0 DCMP4_THR 000h Digital Comparator 4 threshold (12-bit unsigned binary number; coding is the same as AUX_DATA) Table 47 AUXADC Digital Comparator Control 18.5 AUXADC INTERRUPTS The AUXADC is associated with a number of Interrupt event flags to indicate when new AUXADC data is ready, or to indicate that one or more of the digital comparator thresholds has been crossed. Each of these secondary interrupts triggers a primary AUXADC Interrupt, AUXADC_INT (see Section 23). This can be masked by setting the mask bit(s) as described in Table 48. Note that AUXADC_DATA_EINT is not cleared by reading the measured AUXADC data, it can only be cleared by writing ‘1’ to the AUXADC_DATA_EINT register. The AUXADC interrupts can be programmed using bits in Table 48. ADDRESS R16401 (4011h) Interrupt Status 1 BIT 8 LABEL AUXADC_DATA_EINT DESCRIPTION AUXADC Data Ready interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 7:4 AUXADC_DCOMPn_EINT AUXADC Digital Comparator n interrupt (Trigger is controlled by DCMPn_GT) Note: Cleared when a ‘1’ is written. R16409 (4019h) 8 IM_AUXADC_DATA_EINT Interrupt mask. 0 = Do not mask interrupt. Interrupt Status 1 Mask 1 = Mask interrupt. Default value is 1 (masked) 7:4 IM_AUXADC_DCOMPn_EI NT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Note: n is a number between 1 and 4 that identifies the individual Comparator. Table 48 AUXADC Interrupts w PD, February 2012, Rev 4.0 102 Production Data WM8321 19 RESERVED w PD, February 2012, Rev 4.0 103 WM8321 Production Data 20 REAL-TIME CLOCK (RTC) 20.1 GENERAL DESCRIPTION The WM8321 provides a Real Time Clock (RTC) in the form of a 32-bit counter. The RTC uses the 32.768kHz crystal oscillator as its clock source and increments the register value once per second. (Note that a direct CMOS input may be used in place of the crystal oscillator; both options are described in Section 13.) To compensate for errors in the clock frequency, the RTC includes a frequency trim capability. The RTC is enabled at all times, including when the WM8321 is in the BACKUP state. When required, the RTC can be maintained via a backup battery in the absence of any other power supply. In the absence of a backup battery, the RTC contents can be held (unclocked) for a limited period of up to 5 minutes via a 22F capacitor. The RTC incorporates an Alarm function. The Alarm time is held in a 32-bit register. When the RTC counter matches the Alarm time, a selectable response will be actioned. For digital rights management purposes, the RTC includes security features designed to detect unauthorised modifications to the RTC counter. 20.2 RTC CONTROL The 32-bit RTC counter value, RTC_TIME is held in two 16-bit registers, R16417 (4021h) and R16418 (4022h). The value of RTC_TIME is incremented by the WM8321 once per second. On initial power-up (from the NO POWER state), these registers will be initialised to default values. Once either of these registers has been written to, the RTC_VALID bit is set to indicate that the RTC_TIME registers contain valid data. When RTC registers are updated, the RTC_SYNC_BUSY bit indicates that the RTC is busy. The RTC registers should not be written to when RTC_SYNC_BUSY = 1. The RTC_WR_CNT field is provided as a security feature for the RTC. After initialisation, this field is updated on every write to R16417 (4021h) or to R16418 (4022h). This enables the host processor to detect unauthorised modifications to the RTC counter value. See Section 20.4 for more details. For additional security, the WM8321 does not allow the RTC to be updated more than 8 times in a one-hour period. Additional write attempts will be ignored. The RTC Alarm time is held in registers R16419 (4023h) and R16420 (4024h). The Alarm function is enabled when RTC_ALM_ENA is set. When the Alarm is enabled, and the RTC counter matches the Alarm time, the RTC Alarm Interrupt is triggered, as described in Section 20.3. If the RTC Alarm occurs in the SLEEP power state, then a WAKE transition request is generated. If the RTC Alarm occurs in the OFF power state, then an ON transition request is generated. See Section 11.3 for details. When updating the RTC Alarm time, it is recommended to disable the Alarm first, by setting RTC_ALM_ENA = 0. The RTC Alarm registers should not be written to when RTC_SYNC_BUSY = 1. The RTC has a frequency trim feature to allow compensation for known and constant errors in the crystal oscillator frequency up to ±8Hz. The RTC_TRIM field is a 10-bit fixed point 2’s complement number. MSB scaling = -8Hz. To compensate for errors in the clock frequency, this register should be set to the error (in Hz) with respect to the ideal (32768Hz) of the input crystal frequency. For example, if the actual crystal frequency = 32769.00Hz, then the frequency error = +1Hz. The value of RTC_TRIM in this case is 0001_000000. For example, if the actual crystal frequency = 32763.78Hz, then the frequency error = -4.218750Hz. The value of RTC_TRIM in this case is 1011_110010. Note that the RTC_TRIM control register is locked by the WM8321 User Key. This register can only be changed by writing the appropriate code to the Security register, as described in Section 12.4. w PD, February 2012, Rev 4.0 104 WM8321 Production Data ADDRESS R16416 (4020h) BIT 15:0 LABEL RTC_WR_CNT DEFAULT 0000h This random number is updated on every write to the RTC_TIME registers. RTC Write Counter R16417 (4021h) 15:0 RTC_TIME [31:16] 0000h 15:0 RTC_TIME [15:0] 0000h RTC Seconds counter (LSW) RTC_TIME increments by 1 every second. This is the 16 LSBs. RTC Time 2 R16419 (4023h) RTC Seconds counter (MSW) RTC_TIME increments by 1 every second. This is the 16 MSBs. RTC Time 1 R16418 (4022h) DESCRIPTION RTC Write Counter. 15:0 RTC_ALM [31:16] 0000h RTC Alarm time (MSW) 16 MSBs of RTC_ALM RTC Alarm 1 R16420 (4024h) 15:0 RTC_ALM [15:0] 0000h RTC Alarm time (LSW) 16 LSBs of RTC_ALM RTC Alarm 2 R16421 (4025h) 15 RTC_VALID 0 RTC Valid status 0 = RTC_TIME has not been set since Power On Reset RTC Control 1 = RTC_TIME has been written to since Power On Reset 14 RTC_SYNC_BUS Y 0 RTC Busy status 0 = Normal 1 = Busy The RTC registers should not be written to when RTC_SYNC_BUSY = 1. 10 RTC_ALM_ENA 0 RTC Alarm Enable 0 = Disabled 1 = Enabled R16422 (4026h) 9:0 RTC_TRIM RTC Trim 000h RTC frequency trim. Value is a 10bit fixed point <4,6> 2’s complement number. MSB Scaling = -8Hz. The register indicates the error (in Hz) with respect to the ideal 32768Hz) of the input crystal frequency. Protected by user key Table 49 Real Time Clock (RTC) Control w PD, February 2012, Rev 4.0 105 WM8321 Production Data 20.3 RTC INTERRUPTS The Real Time Clock (RTC) is associated with two Interrupt event flags. The RTC_PER_EINT interrupt is set each time a periodic timeout occurs. The periodic timeout is configured using the RTC_PINT_FREQ field described in Table 51. The RTC_ALM_EINT interrupt is set when the RTC Alarm is triggered. The RTC Alarm time is configured as described in Section 20.2. Each of these secondary interrupts triggers a primary Real Time Clock Interrupt, RTC_INT (see Section 23). This can be masked by setting the mask bit(s) as described in Table 50. ADDRESS R16401 (4011h) Interrupt Status 1 BIT 3 LABEL DESCRIPTION RTC_PER_EINT RTC Periodic interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 2 RTC_ALM_EINT RTC Alarm interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. R16409 (4019h) 3 IM_RTC_PER_EINT Interrupt mask. 0 = Do not mask interrupt. Interrupt Status 1 Mask 1 = Mask interrupt. Default value is 1 (masked) 2 IM_RTC_ALM_EINT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Table 50 Real Time Clock (RTC) Interrupts The frequency of the RTC periodic interrupts is set by the RTC_PINT_FREQ field, as described in Table 51. ADDRESS R16421 (4025h) BIT LABEL DEFAULT DESCRIPTION 6:4 RTC_PINT_FREQ [2:0] 000 RTC Periodic Interrupt timeout period RTC Control 000 = Disabled 001 = 2s 010 = 4s 011 = 8s 100 = 16s 101 = 32s 110 = 64s 111 = 128s Table 51 Real Time Clock (RTC) Periodic Interrupt Control w PD, February 2012, Rev 4.0 106 WM8321 Production Data 20.4 DIGITAL RIGHTS MANAGEMENT The Real Time Clock (RTC) maintains a continuous record of the time; this is maintained at all times, including when the WM8321 is powered down and the RTC function is maintained by the backup battery. It is highly desirable to be able to write to the RTC counter in order to configure it for logical translation into hours/minutes and to support calendar functions. However, for digital rights management purposes, it is important that malicious modification of the RTC is either prevented or detected. The security measure implemented on the WM8321 is the RTC Write Counter. This register is initialised to 0000h during Power On Reset, and is updated automatically whenever a Write operation is scheduled on either of the RTC_TIME registers. Note that, when the RTC Write Counter is updated, the new value is generated at random; it is not a sequential counter. It is assumed that legitimate updates to the RTC_TIME are only those initiated by the Application Processor (AP). When the AP makes an update to the RTC_TIME, the AP can also read the new value of the RTC Write Counter, and should store the value in non-volatile memory. If the AP detects a change in value of the RTC Write Counter, and this was not caused by the AP itself writing to the RTC_TIME, this means that an unauthorised write to the RTC_TIME registers has occurred. In order to make it difficult for an unauthorised RTC_TIME update to be masked by simply writing to the RTC Write Counter, the RTC_WR_CNT field is generated at random by the WM8321 whenever the RTC_TIME field is updated. For additional security, the WM8321 does not allow the RTC to be updated more than 8 times in a one-hour period. Additional write attempts will be ignored. The RTC Control registers are described in Table 49. 20.5 BACKUP MODE CLOCKING OPTIONS The BACKUP state is entered when the PVDD power supply is below the reset threshold of the device. Typically, this means that the PVDD supply has been removed. Most of the device functions and registers are reset in this state. The RTC and oscillator and a ‘software scratch’ memory area can be maintained from a backup power source in the BACKUP state. This is provided using a coin cell, super/gold capacitor, or else a standard capacitor, connected to the LDO12VOUT pin via a 22kΩ resistor. See Section 17.3 for further details. The RTC and oscillator can be disabled in the BACKUP state by setting the XTAL_BKUPENA register bit to 0. This feature may be used to minimise the device power consumption in the BACKUP state. A 22F capacitor connected to LDO12VOUT can maintain the RTC value, unclocked, for up to 5 minutes in BACKUP if the oscillator is disabled. The XTAL_BKUPENA register bit is defined in Section 13.1. For more details on backup power, see Section 17.3. w PD, February 2012, Rev 4.0 107 WM8321 Production Data 21 GENERAL PURPOSE INPUTS / OUTPUTS (GPIO) 21.1 GENERAL DESCRIPTION The WM8321 has 12 general-purpose input/output (GPIO) pins, GPIO1 - GPIO12. These can be configured as inputs or outputs, active high or active low, with optional on-chip pull-up or pull-down resistors. GPIO outputs can either be CMOS driven or Open Drain configuration. Each GPIO pin can be tri-stated and can also be used to trigger Interrupts. The function of each GPIO pin is selected individually. Different voltage power domains are selectable on a pin by pin basis for GPIOs 1-12. Input de-bounce is automatically implemented on selected GPIO functions. Note that, when GPIO10, GPIO11 or GPIO12 is used as an input to the AUXADC (see Section 18), then the normal GPIO functionality cannot be supported on the affected pin(s). It is recommended that the respective GPIO(s) are tri-stated, as described in Section 21.3. 21.2 GPIO FUNCTIONS The list of GPIO functions supported by the WM8321 is contained in Table 52 (for input functions) and Table 53 (for output functions). The input functions are selected when the respective GPn_DIR register bit is 1. The output functions are selected when the respective GPn_DIR register bit is 0. The selected function for each GPIO pin is selected by writing to the respective GPn_FN register bits. All functions are available on all GPIO pins. The polarity of each input or output GPIO function can be selected using the applicable GPn_POL register bit. The available power domains for each pin are specific to different GPIOs. The de-bounce time for the GPIO input functions is determined by the GPn_FN field. Some of the input functions allow a choice of de-bounce times, as detailed in Table 52. The register controls for configuring the GPIO pins are defined in Section 21.3. GPn_FN 0h GPIO INPUT FUNCTION DE-BOUNCE TIME GPIO GPIO input. Logic level is read from the GPn_LVL register bits. See Section 21.3. 32s to 64s ON/OFF Request Control input for requesting an ON/OFF state transition. See Section 11.3. 32ms 64ms 1h 2h DESCRIPTION 4ms to 8ms Under default polarity (GPn_POL=1), a rising edge requests the ON state and a falling edge requests the OFF state. 3h 4h SLEEP/WAKE Request Control input for requesting a SLEEP/WAKE state transition. See Section 11.3. 32s to 64s 32ms to 64ms Under default polarity (GPn_POL=1), a rising edge requests the SLEEP state and a falling edge requests the WAKE transition to the ON state. 5h SLEEP Request Control input for requesting a SLEEP state transition. See Section 11.3. 32s to 64s Under default polarity (GPn_POL=1), a rising edge requests the SLEEP state and a falling edge has no effect. 6h ON Request Control input for requesting an ON state transition. See Section 11.3. 32s to 64s Under default polarity (GPn_POL=1), a rising edge requests the ON state and a falling edge has no effect. 7h w Watchdog Reset Control input for resetting the Watchdog Timer. See Section 25. 32s to 64s PD, February 2012, Rev 4.0 108 WM8321 Production Data GPn_FN GPIO INPUT FUNCTION DESCRIPTION DE-BOUNCE TIME 8h Hardware DVS control 1 Control input for selecting the DVS output voltage in one or more DC-DC Converters. See Section 15.6. None 9h Hardware DVS control 2 Control input for selecting the DVS output voltage in one or more DC-DC Converters. See Section 15.6. None Ah Hardware Enable 1 Control input for enabling one or more DC-DC Converters and LDO Regulators. See Section 15. 32s to 64s Bh Hardware Enable 2 Control input for enabling one or more DC-DC Converters and LDO Regulators. See Section 15. 32s to 64s Ch Hardware Control input 1 Control input for selecting the operating mode and/or output voltage of one or more DC-DC Converters and LDO Regulators. See Section 15. 32s to 64s Dh Hardware Control input 2 Control input for selecting the operating mode and/or output voltage of one or more DC-DC Converters and LDO Regulators. See Section 15. 32s to 64s Eh Hardware Control input 1 Control input for selecting the operating mode and/or output voltage of one or more DC-DC Converters and LDO Regulators. See Section 15. 32ms to 64ms Fh Hardware Control input 2 Control input for selecting the operating mode and/or output voltage of one or more DC-DC Converters and LDO Regulators. See Section 15. 32ms to 64ms Table 52 List of GPIO Input Functions Further details of the GPIO input de-bounce time are noted in Section 21.3. GPn_FN GPIO OUTPUT FUNCTION DESCRIPTION 0h GPIO GPIO output. Logic level is set by writing to the GPn_LVL register bits. See Section 21.3. 1h Oscillator clock 32.768kHz clock output. See Section 13. 2h ON state Logic output indicating that the WM8321 is in the ON state. See Section 11.5. 3h SLEEP state Logic output indicating that the WM8321 is in the SLEEP state. See Section 11.5. 4h Power State Change Logic output asserted whenever a Power On Reset, or an ON, OFF, SLEEP or WAKE transition has completed. Under default polarity (GPn_POL=1), the logic level is the same as the PS_INT interrupt status flag. Note that, if any of the associated Secondary interrupts is masked, then the respective event will not affect the Power State Change GPIO output. See Section 11.2 and Section 11.4. w 8h DC-DC1 DVS Done Logic output indicating that DC-DC1 buck converter DVS slew has been completed. This signal is temporarily de-asserted during voltage transitions (including non-DVS transitions). See Section 15.6. 9h DC-DC2 DVS Done Logic output indicating that DC-DC1 buck converter DVS slew has been completed. This signal is temporarily de-asserted during voltage transitions (including non-DVS transitions). See Section 15.6. PD, February 2012, Rev 4.0 109 WM8321 Production Data GPn_FN GPIO OUTPUT FUNCTION DESCRIPTION Ah External Power Enable 1 Logic output assigned to one of the timeslots in the ON/OFF and SLEEP/WAKE sequences. This can be used for sequenced control of external circuits. See Section 15.3. Bh External Power Enable 2 Logic output assigned to one of the timeslots in the ON/OFF and SLEEP/WAKE sequences. This can be used for sequenced control of external circuits. See Section 15.3. Ch System Supply Good (PVDD Good) Logic output from PVDD monitoring circuit. This function represents the internal SYSOK signal. See Section 24.4. Dh Converter Power Good (PWR_GOOD) Status output indicating that all selected DC-DC converters and LDO regulators are operating correctly. Only asserted in ON and SLEEP modes. See Section 15.13. Eh External Power Clock 2MHz clock output suitable for clocking external DC-DC converters. This clock signal is synchronized with the WM8321 DC Converters clocking signal. See Section 13. This clock output is only enabled when either of the External Power Enable signals (EPE1 or EPE2) is asserted. These signals can be assigned to one of the timeslots in the ON/OFF and SLEEP/WAKE sequences. See Section 15.3. Fh Auxiliary Reset Logic output indicating a Reset condition. This signal is asserted in the OFF state. The status in SLEEP mode is configurable. See Section 11.7. Note that the default polarity for this function (GPn_POL=1) is “Active High”. Setting GPn_POL=0 will select “Active Low” function. Table 53 List of GPIO Output Functions 21.3 CONFIGURING GPIO PINS The GPIO pins are configured using the Resister fields defined in Table 54. The function of each GPIO is selected using the GPn_FN register field. The pin direction field GPn_DIR selects between input functions and output functions. See Section 21.2 for a summary of the available GPIO functions. The polarity of each GPIO can be configured using the GPn_POL bits. This inversion is effective both on GPIO inputs and outputs. When GPn_POL = 1, the non-inverted ‘Active High’ polarity applies. The opposite logic can be selected by setting GPn_POL = 0. The voltage power domain of each GPIO is determined by the GPn_PWR_DOM register. Note that the available options vary between different GPIO pins, as described in Table 56. A GPIO output may be either CMOS driven or Open Drain. This is selected using the GPn_OD bits. Internal pull-up or pull-down resistors can be enabled on each pin using the GPn_PULL field. Both resistors are available for use when the associated GPIO is an input. When the GPIO pin is configured as an Open Drain output, the internal pull-up resistor may be required if no external pull-up resistors are present. A GPIO pin may be tri-stated using the GPn_ENA register field. When GPn_ENA = 0, the respective pin is tri-stated. A tri-stated pin exhibits high impedance to any external circuit and is disconnected from the internal GPIO circuits. The pull-up and pull-down resistors are disabled when a GPIO pin is tri-stated. GPIO pins can generate an interrupt (see Section 21.4). The GPn_INT_MODE field selects whether the interrupt occurs on a single active edge only, or else on both rising and falling edges. When single edge is selected, the active edge is the rising edge (when GPn_POL = 1) or the falling edge (when GPn_POL = 0). When GPIO10, GPIO11 or GPIO12 is used as an input to the AUXADC (see Section 18), it is recommended that the respective GPIO(s) are tri-stated (ie. GPn_ENA = 0). The normal GPIO functionality cannot be supported on a GPIO pin that is enabled as an input to the AUXADC. w PD, February 2012, Rev 4.0 110 WM8321 Production Data ADDRESS R16440 (4038h) BIT 15 LABEL GPn_DIR DEFAULT 1 DESCRIPTION GPIOn pin direction 0 = Output 1 = Input to 14:13 GPn_PULL [1:0] 01 R16451 (4043h) GPIOn Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved 12 GPn_INT_M ODE 0 GPIOn Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GPn_POL=1) or falling edge triggered (if GPn_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges 11 GPn_PWR_D OM 0 10 GPn_POL 1 GPIOn Power Domain See Table 56. GPIOn Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) 9 GPn_OD 0 GPIOn Output pin configuration 0 = CMOS 1 = Open Drain 7 GPn_ENA 0 GPIOn Enable control 0 = GPIO pin is tri-stated 1 = Normal operation 3:0 GPn_FN [3:0] 0000 GPIOn Pin Function See Table 57. Note: n is a number between 1 and 12 that identifies the individual GPIO. Note: The default values noted are valid when the WM8321 powers up to the OFF state, or if the Register Map is reset following a Device Reset or Software Reset event. In the case of GPIO pins 1 to 6, these registers are overwritten with the respective ICE or OTP memory contents when an ON transition is scheduled. Table 54 GPIO Pin Configuration When the GPIO output function is selected (GPn_FN = 0h, GPn_DIR = 0), the state of a GPIO output is controlled by writing to the corresponding GPn_LVL register bit, as defined in Table 55. The logic level of a GPIO input is determined by reading the corresponding GPn_LVL register bit. If GPn_POL is set, then the read value of the GPn_LVL field for a GPIO input is the inverse of the external signal. Note that, when the GPIO input level changes, the logic level of GPn_LVL will only be updated after the maximum de-bounce period, as listed in Table 52. An input pulse that is shorter than the minimum de-bounce period will be filtered by the de-bounce function and will be ignored. If a GPIO is configured as a CMOS output (ie. GPn_OD = 0), then the read value of the GPn_LVL field will indicate the logic level of that output. If GPn_POL is set, then the read value of the GPn_LVL field for a GPIO output is the inverse of the level on the external pad. If a GPIO is configured as an Open Drain output, then the read value of GPn_LVL is only valid when the internal pull-up resistor is enabled on the pin (ie. when GPn_PULL = 10). The read value is also affected by the GPn_POL bit, as described above for the CMOS case. If a GPIO is tri-stated (GPn_ENA = 0), then the read value of the corresponding GPn_LVL field is invalid. w PD, February 2012, Rev 4.0 111 WM8321 Production Data ADDRESS BIT LABEL DEFAULT DESCRIPTION R16396 (400Ch) 11 GP12_LVL 0 GPIOn level. 10 GP11_LVL 0 GPIO Level 9 GP10_LVL 0 8 GP9_LVL 0 When GPn_FN = 0h and GPn_DIR = 0, write to this bit to set a GPIO output. 7 GP8_LVL 0 6 GP7_LVL 0 5 GP6_LVL 0 4 GP5_LVL 0 3 GP4_LVL 0 2 GP3_LVL 0 1 GP2_LVL 0 0 GP1_LVL 0 Read from this bit to read GPIO input level. When GPn_POL is 0, the register contains the opposite logic level to the external pin. Table 55 GPIO Level Register The power domain for each GPIO is controlled using the GPn_PWR_DOM registers as described in Table 56. The selected power domain for each GPIO affects the maximum input voltage that can be supported on the respective pin(s). Note that this is also applicable when GPIO10, GPIO11 or GPIO12 are used as inputs to the AUXADC (see Section 18). The input voltage at the GPIO pin must not exceed the voltage of the respective power domain. ADDRESS R16440 (4038h) BIT LABEL DEFAULT 11 GP1_PWR_DO M 0 0 = DBVDD GPIO1 Control R16441 (4039h) 1 = VPMIC (LDO12) 11 GP2_PWR_DO M 0 GP3_PWR_DO M 0 GP4_PWR_DO M 0 GP5_PWR_DO M 0 GP6_PWR_DO M 0 GP7_PWR_DO M 0 GP8_PWR_DO M 0 GP9_PWR_DO M 0 GP10_PWR_D OM 0 1 = VPMIC (LDO12) 11 1 = VPMIC (LDO12) 11 1 = PVDD 11 1 = PVDD 11 1 = PVDD 11 1 = VPMIC (LDO12) 11 1 = VPMIC (LDO12) 11 GPIO10 Control w GPIO9 Power Domain select 0 = DBVDD GPIO9 Control R16449 (4041h) GPIO8 Power Domain select 0 = DBVDD GPIO8 Control R16448 (4040h) GPIO7 Power Domain select 0 = DBVDD GPIO7 Control R16447 (403Fh) GPIO6 Power Domain select 0 = DBVDD GPIO6 Control R16446 (403Eh) GPIO5 Power Domain select 0 = DBVDD GPIO5 Control R16445 (403Dh) GPIO4 Power Domain select 0 = DBVDD GPIO4 Control R16444 (403Ch) GPIO3 Power Domain select 0 = DBVDD GPIO3 Control R16443 (403Bh) GPIO2 Power Domain select 0 = DBVDD GPIO2 Control R16442 (403Ah) DESCRIPTION GPIO1 Power Domain select 1 = VPMIC (LDO12) 11 GPIO10 Power Domain select 0 = DBVDD 1 = PVDD PD, February 2012, Rev 4.0 112 WM8321 Production Data ADDRESS R16450 (4042h) BIT LABEL DEFAULT 11 GP11_PWR_D OM 0 0 = DBVDD GPIO11 Control R16451 (4043h) DESCRIPTION GPIO11 Power Domain select 1 = PVDD 11 GP12_PWR_D OM 0 GPIO12 Power Domain select 0 = DBVDD GPIO12 Control 1 = PVDD Table 56 GPIO Power Domain Registers The function of each GPIO is controlled using the GPn_FN registers defined in Table 57. Note that the selected function also depends on the associated GPn_DIR field described in Table 54. See also Section 21.2 for additional details of each GPIO function, including the applicable de-bounce times for GPIO input functions. ADDRESS R16440 (4038h) BIT 3:0 LABEL GP1_FN [3:0] DEFAULT 0000 0h = GPIO input (long de-bounce) GPIO1 Control R16441 (4039h) 1h = GPIO input 3:0 GP2_FN [3:0] 0000 3:0 GP3_FN [3:0] 0000 6h = Power On request 3:0 GP4_FN [3:0] 0000 3:0 GP5_FN [3:0] 0000 3:0 GP6_FN [3:0] 0000 GPIO6 Control R16446 (403Eh) 3:0 GP7_FN [3:0] 0000 3:0 GP8_FN [3:0] 0000 GPIO7 Control R16447 (403Fh) 3:0 GP9_FN [3:0] 0000 3:0 GP10_FN [3:0] 0000 Eh = HW Control1 input (long debounce) Fh = HW Control2 input (long debounce) Output functions: 1h = 32.768kHz oscillator output 2h = ON state 4h = Power State Change 5h = Reserved 7h = Reserved 3:0 GP11_FN [3:0] 0000 8h = DC1 DVS Done 9h = DC2 DVS Done GPIO11 Control R16451 (4043h) Dh = HW Control2 input 6h = Reserved GPIO10 Control R16450 (4042h) Ch = HW Control1 input 3h = SLEEP state GPIO9 Control R16449 (4041h) Ah = HW Enable1 input 0h = GPIO output GPIO8 Control R16448 (4040h) 9h = DVS2 input Bh = HW Enable2 input GPIO5 Control R16445 (403Dh) 7h = Watchdog Reset input 8h = DVS1 input GPIO4 Control R16444 (403Ch) 4h = Sleep/Wake request (long debounce) 5h = Sleep request GPIO3 Control R16443 (403Bh) 2h = Power On/Off request 3h = Sleep/Wake request GPIO2 Control R16442 (403Ah) DESCRIPTION Input functions: Ah = External Power Enable1 Bh = External Power Enable2 3:0 GP12_FN [3:0] GPIO12 Control 0000 Ch = System Supply Good (SYSOK) Dh = Converter Power Good (PWR_GOOD) Eh = External Power Clock (2MHz) Fh = Auxiliary Reset Table 57 GPIO Function Select Registers w PD, February 2012, Rev 4.0 113 WM8321 Production Data Note that GPIO input functions 2h, 3h, 4h, 5h and 6h are edge-triggered only. The associated state transition(s) are scheduled only when a rising or falling edge is detected on the respective GPIO pin. At other times, it is possible that other state transition events may cause a state transition regardless of the state of the GPIO input. See Section 11.3 for details of all the state transition events. 21.4 GPIO INTERRUPTS Each GPIO pin has an associated interrupt flag, GPn_EINT, in Register R16405 (4015h). Each of these secondary interrupts triggers a primary GPIO Interrupt, GP_INT (see Section 23). This can be masked by setting the mask bit(s) as described in Table 58. See Section 28 and Section 29 for a definition of the register bit positions applicable to each GPIO. ADDRESS R16405 (4015h) BIT 15:0 LABEL GPn_EINT (Trigger is controlled by GPn_INT_MODE) Interrupt Status 5 R16413 (401Dh) DESCRIPTION GPIO interrupt. Note: Cleared when a ‘1’ is written. 15:0 Interrupt Status 5 Mask IM_GPn_EINT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Note: n is a number between 1 and 12 that identifies the individual GPIO. Table 58 GPIO Interrupts w PD, February 2012, Rev 4.0 114 WM8321 Production Data 22 SYSTEM STATUS LED DRIVERS 22.1 GENERAL DESCRIPTION The WM8321 provides two System Status LED Drivers. These are digital outputs intended for driving LEDs directly. The LED outputs can be assigned to indicate OTP Program status or Power State status. They can also be commanded directly via register control, in order to provide any other required functionality. 22.2 LED DRIVER CONTROL LED Drivers are configurable in the ON and SLEEP power states only. The functionality of the LED Drivers is controlled by the LEDn_SRC register bits, as described in Table 59. ADDRESS R16460 (404Ch) BIT 15:14 LABEL LED1_SRC [1:0] DEFAULT 11 DESCRIPTION LED1 Source (Selects the LED1 function.) Status LED1 00 = Off 01 = Power State Status 10 = Reserved 11 = Manual Mode Note - LED1 also indicates completion of OTP Auto Program R16461 (404Dh) 15:14 LED2_SRC [1:0] 11 LED2 Source (Selects the LED2 function.) Status LED2 00 = Off 01 = Power State Status 10 = Reserved 11 = Manual Mode Note - LED2 also indicates an OTP Auto Progam Error condition Table 59 System Status LED Control 22.2.1 OTP PROGAM STATUS The LED drivers indicate the status of the OTP Auto Program function, where the contents of the external InstantConfig™ EEPROM (ICE) memory are automatically programmed into the OTP. See Section 14.6.3 for further details of the OTP Auto Program function. When the OTP Auto Program function is executed, the System Status LED drivers follow the functionality defined in Table 60. LED DRIVER DESCRIPTION DRIVE MODE LED ‘ON’ TIME ON:OFF DUTY CYCLE LED1 OTP Auto Program Complete Constant n/a n/a LED2 OTP Auto Progam Error Constant n/a n/a Table 60 System Status LED Outputs - OTP Program Status The OTP Program Status LED outputs will continue until a Device Reset. Note that the OTP Program Status is always indicated via the LED outputs, regardless of the LEDn_SRC register fields. w PD, February 2012, Rev 4.0 115 WM8321 Production Data 22.2.2 POWER STATE STATUS Setting LEDn_SRC = 01 configures the associated LED to indicate Power State status. Under this selection, four different conditions may be indicated, as defined in Table 61. LED DRIVER LED1 or LED2 DESCRIPTION DRIVE MODE LED ‘ON’ TIME ON:OFF DUTY CYCLE Power Sequence Failure Pulsed sequence (4 pulses) 1s 1:1 PVDD Low Continuous pulsed 250ms 1:3 ON state Constant n/a n/a SLEEP state Continuous pulsed 250ms 1:7 Table 61 System Status LED Outputs - Power State Status If more than one of the conditions listed occurs simultaneously, then the LED output pattern is controlled by the condition in the highest position within the list above. For example, if the PVDD Low condition occurs while in the ON or SLEEP states, then the LED output follows the pattern defined for the PVDD Low condition. The PVDD Low indication is asserted if PVDD is less than the user-selectable threshold SYSLO_THR, as described in Section 24.4. Note that, in the case of Power Sequence Failure, the transition to OFF occurs after the 4 LED pulses have been emitted. 22.2.3 MANUAL MODE Setting LEDn_SRC = 11 configures the associated LED to operate in Manual Mode, which is configured using additional register fields. In Manual Mode, the LED output can be commanded as Off, On (Constant), Continuous Pulsed or Pulsed Sequence. The selected operation is determined by the LEDn_MODE registers as described in Table 62. In Continuous Pulsed mode and Pulsed Sequence mode, the ‘On’ time and the Duty Cycle can be configured using the LEDn_DUR and LEDn_DUTY_CYC registers respectively. In Pulsed Sequence mode, the number of pulses in the sequence can be selected using the LEDn_SEQ_LEN register. On completion of the commanded number of pulses, the LED remains off until LEDn_MODE or LEDn_SRC is changed to another value. ADDRESS R16460 (404Ch) BIT 9:8 LABEL LED1_MODE [1:0] DEFAULT 00 DESCRIPTION LED1 Mode (Controls LED1 in Manual Mode only.) Status LED1 00 = Off 01 = Constant 10 = Continuous Pulsed 11 = Pulsed Sequence 5:4 LED1_SEQ_LE N [1:0] 10 LED1 Pulse Sequence Length (when LED1_MODE = Pulsed Sequence) 00 = 1 pulse 01 = 2 pulses 10 = 4 pulses 11 = 7 pulses w PD, February 2012, Rev 4.0 116 WM8321 Production Data ADDRESS BIT LABEL 3:2 LED1_DUR [1:0] DEFAULT 01 DESCRIPTION LED1 On time (when LED1_MODE = Continuous Pulsed or Pulsed Sequence) 00 = 1 second 01 = 250ms 10 = 125ms 11 = 62.5ms 1:0 LED1_DUTY_C YC [1:0] 10 LED1 Duty Cycle (On:Off ratio) (when LED1_MODE = Continuous Pulsed or Pulsed Sequence) 00 = 1:1 (50% on) 01 = 1:2:(33.3% on) 10 = 1:3 (25% on) 11 = 1:7 (12.5% on) R16461 (404Dh) 9:8 LED2_MODE [1:0] 00 LED2 Mode (Controls LED2 in Manual Mode only.) Status LED2 00 = Off 01 = Constant 10 = Continuous Pulsed 11 = Pulsed Sequence 5:4 LED2_SEQ_LE N [1:0] 10 LED2 Pulse Sequence Length (when LED2_MODE = Pulsed Sequence) 00 = 1 pulse 01 = 2 pulses 10 = 4 pulses 11 = 7 pulses 3:2 LED2_DUR [1:0] 01 LED2 On time (when LED2_MODE = Continuous Pulsed or Pulsed Sequence) 00 = 1 second 01 = 250ms 10 = 125ms 11 = 62.5ms 1:0 LED2_DUTY_C YC [1:0] 10 LED2 Duty Cycle (On:Off ratio) (when LED2_MODE = Continuous Pulsed or Pulsed Sequence) 00 = 1:1 (50% on) 01 = 1:2:(33.3% on) 10 = 1:3 (25% on) 11 = 1:7 (12.5% on) Table 62 System Status LED Outputs - Manual Mode Control w PD, February 2012, Rev 4.0 117 WM8321 Production Data 22.3 LED DRIVER CONNECTIONS The recommended connection for System Status LEDs is illustrated in Figure 23. The LED outputs are referenced to the PVDD power domain. A series resistor may be required, depending on the LED characteristics and the PVDD voltage. Figure 23 System Status LED Connections w PD, February 2012, Rev 4.0 118 WM8321 Production Data 23 INTERRUPT CONTROLLER The WM8321 has a comprehensive Interrupt logic capability. The dedicated IRQ ¯¯¯ pin can be used to alert a host processor to selected events or fault conditions. Each of the interrupt conditions can be individually enabled or masked. Following an interrupt event, the host processor should read the interrupt registers in order to determine what caused the interrupt, and take appropriate action if required. The WM8321 interrupt controller has two levels: Secondary interrupts indicate a single event in one of the circuit blocks. The event is indicated by setting a register bit. This bit is a latching bit - once it is set, it remains at logic 1 even if the trigger condition is cleared. The secondary interrupts are cleared by writing a logic 1 to the relevant register bit. Note that reading the register does not clear the secondary interrupt. Primary interrupts are the logical OR of the associated secondary interrupts (usually all the interrupts associated with one particular circuit block). Each of the secondary interrupts can be individually masked or enabled as an input to the corresponding primary interrupt. The primary interrupt register R16400 (4010h) is read-only. The status of the IRQ ¯¯¯ pin reflects the logical NOR of the primary interrupts. A logic 0 indicates that one or more of the primary interrupts is asserted. Each of the primary interrupts can be individually masked or enabled as an input to the IRQ ¯¯¯ pin output. The IRQ ¯¯¯ pin output can either be CMOS driven or Open Drain (integrated pull-up) configuration, as determined by the IRQ_OD register bit. When the IRQ ¯¯¯ pin is Open Drain, it is actively driven low when asserted; the pull-up causes a logic high output when not asserted. The Open Drain configuration enables multiple devices to share a common Interrupt line with the host processor. The IRQ ¯¯¯ pin output can be masked by setting the IM_IRQ register bit. When the IRQ ¯¯¯ pin is masked, it is held in the logic 1 (or Open Drain) state regardless of any internal interrupt event. Note that the secondary interrupt bits are always valid - they are set as normal, regardless of whether the bit is enabled or masked as an input to the corresponding primary interrupt. The primary interrupt bits are set and cleared as normal in response to any unmasked secondary interrupt, regardless of whether the primary interrupt bit is enabled or masked as an input to the IRQ ¯¯¯ pin output. Note also that if any internal condition is configured to trigger an event other than an Interrupt (eg. the Watchdog timer triggers Reset), these events are always actioned, regardless of the state of any interrupt mask bits. The IRQ ¯¯¯ pin output is configured using the register bits described in Table 63. ADDRESS R16407 (4017h) BIT 1 LABEL IRQ_OD DESCRIPTION IRQ pin configuration 0 = CMOS IRQ Config 1 = Open Drain (integrated pull-up) 0 IM_IRQ IRQ pin output mask 0 = Normal 1 = IRQ output is masked Table 63 IRQ Pin Configuration w PD, February 2012, Rev 4.0 119 WM8321 Production Data The interrupt logic is illustrated in Figure 24. event / fault condition sets secondary interrupt e.g. RTC Alarm “mask” register bit (read/write) “mask” register bit (read/write) e.g. IM_RTC_ALM_EINT e.g. IM_RTC_INT IRQ mask bit IM_IRQ AND AND OR event-level register bit (read only) OR NOR IRQ pin e.g. RTC_ALM_EINT Primary interrupt register bit (read only) e.g. RTC_INT Writing ‘1’ to this bit clears the secondary interrupt other secondary interrupts other primary interrupts e.g. WDOG_INT, AUXADC_INT e.g. RTC_PER_EINT Figure 24 Interrupt Logic Following the assertion of the IRQ ¯¯¯ pin to indicate an Interrupt event, the host processor can determine which primary interrupt caused the event by reading the primary interrupt register R16400 (4010h). This register is defined in Section 23.1. After reading the primary interrupt register, the host processor must read the corresponding secondary interrupt register(s) in order to determine which specific event caused the IRQ ¯¯¯ pin to be asserted. The host processor clears the secondary interrupt bit by writing a logic 1 to that bit. 23.1 PRIMARY INTERRUPTS The primary interrupts are defined in Table 64. These bits are Read Only. They are set when any of the associated unmasked secondary interrupts is set. They can only be reset when all of the associated secondary resets are cleared or masked. Each primary interrupt can be masked. When a mask bit is set, the corresponding primary interrupt is masked and does not cause the IRQ ¯¯¯ pin to be asserted. The primary interrupt bits in R16408 (4018h) are valid regardless of whether the mask bit is set. The primary interrupts are all masked by default. ADDRESS R16400 (4010h) System Interrupts BIT 15 LABEL PS_INT DESCRIPTION Power State primary interrupt 0 = No interrupt 1 = Interrupt is asserted 14 TEMP_INT Thermal primary interrupt 0 = No interrupt 1 = Interrupt is asserted 13 GP_INT GPIO primary interrupt 0 = No interrupt 1 = Interrupt is asserted 12 ON_PIN_INT ON Pin primary interrupt 0 = No interrupt 1 = Interrupt is asserted 11 WDOG_INT Watchdog primary interrupt 0 = No interrupt 1 = Interrupt is asserted 8 AUXADC_INT AUXADC primary interrupt 0 = No interrupt 1 = Interrupt is asserted w PD, February 2012, Rev 4.0 120 WM8321 Production Data ADDRESS BIT 7 LABEL PPM_INT DESCRIPTION Power Path Management primary interrupt 0 = No interrupt 1 = Interrupt is asserted 5 RTC_INT Real Time Clock and Crystal Oscillator primary interrupt 0 = No interrupt 1 = Interrupt is asserted 4 OTP_INT OTP Memory primary interrupt 0 = No interrupt 1 = Interrupt is asserted 1 HC_INT High Current primary interrupt 0 = No interrupt 1 = Interrupt is asserted 0 UV_INT Undervoltage primary interrupt 0 = No interrupt 1 = Interrupt is asserted R16408 (4018h) System Interrupts Mask 15 IM_PS_INT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 14 IM_TEMP_INT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 13 IM_GP_INT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 12 IM_ON_PIN_INT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 11 IM_WDOG_INT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 8 IM_AUXADC_INT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 7 IM_PPM_INT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 5 IM_RTC_INT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 4 IM_OTP_INT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) w PD, February 2012, Rev 4.0 121 WM8321 Production Data ADDRESS BIT 1 LABEL IM_HC_INT DESCRIPTION Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 0 IM_UV_INT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Table 64 Primary Interrupt Status and Mask Bits 23.2 SECONDARY INTERRUPTS The following sections define the secondary interrupt status and control bits associated with each of the primary interrupt bits defined in Table 64. 23.2.1 POWER STATE INTERRUPT The primary PS_INT interrupt comprises three secondary interrupts as described in Section 11.4. The secondary interrupt bits are defined in Table 65. Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt event is masked and does not trigger a PS_INT interrupt. The secondary interrupt bits in R16402 (4012h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked by default. ADDRESS R16402 (4012h) Interrupt Status 2 BIT 2 LABEL PS_POR_EINT DESCRIPTION Power On Reset interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 1 PS_SLEEP_OFF_EINT SLEEP or OFF interrupt (Power state transition to SLEEP or OFF states) (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 0 PS_ON_WAKE_EINT ON or WAKE interrupt (Power state transition to ON state) (Rising Edge triggered) Note: Cleared when a ‘1’ is written. R16410 (401Ah) 2 IM_PS_POR_EINT Interrupt mask. 0 = Do not mask interrupt. Interrupt Status 2 Mask 1 = Mask interrupt. Default value is 1 (masked) 1 IM_PS_SLEEP_OFF_EINT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 0 IM_PS_ON_WAKE_EINT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Table 65 Power State Interrupts w PD, February 2012, Rev 4.0 122 WM8321 Production Data 23.2.2 THERMAL INTERRUPTS The primary TEMP_INT interrupt comprises a single secondary interrupt as described in Section 26. The secondary interrupt bit is defined in Table 66. The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event is masked and does not trigger a TEMP_INT interrupt. The secondary interrupt bit in R16401 (4011h) is valid regardless of whether the mask bit is set. The secondary interrupt is masked by default. ADDRESS BIT R16401 (4011h) 1 LABEL TEMP_THW_CINT Interrupt Status 1 R16410 (4019h) DESCRIPTION Thermal Warning interrupt (Rising and Falling Edge triggered) Note: Cleared when a ‘1’ is written. 1 IM_TEMP_THW_CINT Interrupt mask. 0 = Do not mask interrupt. Interrupt Status 1 Mask 1 = Mask interrupt. Default value is 1 (masked) Table 66 Thermal Interrupts 23.2.3 GPIO INTERRUPTS The primary GP_INT interrupt comprises sixteen secondary interrupts as described in Section 21.4. The secondary interrupt bits are defined in Table 67. Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt event is masked and does not trigger a GP_INT interrupt. The secondary interrupt bits in R16405 (4015h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked by default. ADDRESS BIT R16405 (4015h) 15:0 LABEL GPn_EINT Interrupt Status 5 DESCRIPTION GPIO interrupt. (Trigger is controlled by GPn_INT_MODE) Note: Cleared when a ‘1’ is written. R16413 (401Dh) 15:0 IM_GPn_EINT Interrupt mask. 0 = Do not mask interrupt. Interrupt Status 5 Mask 1 = Mask interrupt. Default value is 1 (masked) Note: n is a number between 1 and 12 that identifies the individual GPIO. Table 67 GPIO Interrupts 23.2.4 ON PIN INTERRUPTS The primary ON_PIN_INT interrupt comprises a single secondary interrupt as described in Section 11.6. The secondary interrupt bit is defined in Table 68. The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event is masked and does not trigger an ON_PIN_INT interrupt. The secondary interrupt bit in R16401 (4011h) is valid regardless of whether the mask bit is set. The secondary interrupt is masked by default. ADDRESS BIT R16401 (4011h) 12 LABEL ON_PIN_CINT Interrupt Status 1 R16409 (4019h) DESCRIPTION ON pin interrupt. (Rising and Falling Edge triggered) Note: Cleared when a ‘1’ is written. 12 Interrupt Status 1 Mask IM_ON_PIN_CINT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Table 68 ON Pin Interrupt w PD, February 2012, Rev 4.0 123 WM8321 Production Data 23.2.5 WATCHDOG INTERRUPTS The primary WDOG_INT interrupt comprises a single secondary interrupt as described in Section 25. The secondary interrupt bit is defined in Table 69. The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event is masked and does not trigger a WDOG_INT interrupt. The secondary interrupt bit in R16401 (4011h) is valid regardless of whether the mask bit is set. The secondary interrupt is masked by default. ADDRESS R16401 (4011h) BIT LABEL DESCRIPTION 11 WDOG_TO_EINT Watchdog timeout interrupt. (Rising Edge triggered) Interrupt Status 1 R16409 (4019h) Note: Cleared when a ‘1’ is written. 11 IM_WDOG_TO_EINT Interrupt mask. 0 = Do not mask interrupt. Interrupt Status 1 Mask 1 = Mask interrupt. Default value is 1 (masked) Table 69 Watchdog Timer Interrupts 23.2.6 AUXADC INTERRUPTS The primary AUXADC_INT interrupt comprises five secondary interrupts as described in Section 18.5. The secondary interrupt bits are defined in Table 70. Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt event is masked and does not trigger a AUXADC_INT interrupt. The secondary interrupt bits in R16401 (4011h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked by default. ADDRESS R16401 (4011h) Interrupt Status 1 BIT 8 LABEL AUXADC_DATA_EINT DESCRIPTION AUXADC Data Ready interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 7:4 AUXADC_DCOMPn_EINT AUXADC Digital Comparator n interrupt (Trigger is controlled by DCMPn_GT) Note: Cleared when a ‘1’ is written. R16409 (4019h) 8 IM_AUXADC_DATA_EINT Interrupt mask. 0 = Do not mask interrupt. Interrupt Status 1 Mask 1 = Mask interrupt. Default value is 1 (masked) 7:4 IM_AUXADC_DCOMPn_EI NT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Note: n is a number between 1 and 4 that identifies the individual Comparator. Table 70 AUXADC Interrupts 23.2.7 POWER PATH MANAGEMENT INTERRUPTS The primary PPM_INT interrupt comprises a single secondary interrupt as described in Section 17.2. The secondary interrupt bit is defined in Table 71. The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event is masked and does not trigger a PPM_INT interrupt. The secondary interrupt bit in R16401 (4011h) are valid regardless of whether the mask bit is set. The secondary interrupt is masked by default. w PD, February 2012, Rev 4.0 124 WM8321 Production Data ADDRESS R16401 (4011h) BIT 15 LABEL PPM_SYSLO_EINT (Rising Edge triggered) Interrupt Status 1 R16409 (4019h) DESCRIPTION Power Path SYSLO interrupt Note: Cleared when a ‘1’ is written. 15 IM_PPM_SYSLO_EINT Interrupt mask. 0 = Do not mask interrupt. Interrupt Status 1 Mask 1 = Mask interrupt. Default value is 1 (masked) Table 71 Power Path Management Interrupts 23.2.8 REAL TIME CLOCK AND CRYSTAL OSCILLATOR INTERRUPTS The primary RTC_INT interrupt comprises four secondary interrupts as described in Section 20.3. The secondary interrupt bits are defined in Table 72. Each of the secondary interrupts can be masked except for XTAL_TAMPER_EINT, which cannot be masked. When a mask bit is set, the corresponding interrupt event is masked and does not trigger a RTC_INT interrupt. The secondary interrupt bits in R16401 (4011h) and R16404 (4014h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked by default, except for XTAL_TAMPER_EINT, which cannot be masked. ADDRESS R16401 (4011h) Interrupt Status 1 BIT 3 LABEL RTC_PER_EINT DESCRIPTION RTC Periodic interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 2 RTC_ALM_EINT RTC Alarm interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. R16404 (4014h) Interrupt Status 4 7 XTAL_START_EINT Crystal Oscillator Start Failure interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 6 XTAL_TAMPER_EINT Crystal Oscillator Tamper interrupt (Rising and Falling Edge triggered) Note: Cleared when a ‘1’ is written. R16409 (4019h) 3 IM_RTC_PER_EINT Interrupt mask. 0 = Do not mask interrupt. Interrupt Status 1 Mask 1 = Mask interrupt. Default value is 1 (masked) 2 IM_RTC_ALM_EINT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) R16412 (401Ch) Interrupt Status 4 Mask 7 IM_XTAL_START_EINT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Table 72 Real Time Clock (RTC) and Crystal Oscillator (XTAL) Interrupts w PD, February 2012, Rev 4.0 125 WM8321 Production Data 23.2.9 OTP MEMORY INTERRUPTS The primary OTP_INT interrupt comprises two secondary interrupts as described in Section 14.5. The secondary interrupt bits are defined in Table 73. Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt event is masked and does not trigger a OTP_INT interrupt. The secondary interrupt bits in R16402 (4012h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked by default. ADDRESS R16402 (4012h) Interrupt Status 2 BIT 5 LABEL OTP_CMD_END_EINT DESCRIPTION OTP / ICE Command End interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 4 OTP_ERR_EINT OTP / ICE Command Fail interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. R16410 (401Ah) 5 IM_OTP_CMD_END_EINT Interrupt mask. 0 = Do not mask interrupt. Interrupt Status 2 Mask 1 = Mask interrupt. Default value is 1 (masked) 4 IM_OTP_ERR_EINT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Table 73 OTP Memory Interrupts 23.2.10 HIGH CURRENT INTERRUPTS The primary HC_INT interrupt comprises two secondary interrupts as described in Section 15.12. The secondary interrupt bits are defined in Table 74. Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt event is masked and does not trigger a HC_INT interrupt. The secondary interrupt bits in R16404 (4014h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked by default. ADDRESS R16404 (4014h) Interrupt Status 4 BIT 9 LABEL HC_DC2_EINT DESCRIPTION DC-DC2 High Current interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 8 HC_DC1_EINT DC-DC1 High Current interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. R16412 (401Ch) 9 IM_HC_DC2_EINT Interrupt mask. 0 = Do not mask interrupt. Interrupt Status 4 Mask 1 = Mask interrupt. Default value is 1 (masked) 8 IM_HC_DC1_EINT Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Table 74 Overcurrent Interrupts w PD, February 2012, Rev 4.0 126 WM8321 Production Data 23.2.11 UNDERVOLTAGE INTERRUPTS The primary UV_INT interrupt comprises fourteen secondary interrupts as described in Section 15.12). The secondary interrupt bits are defined in Table 75. Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt event is masked and does not trigger a UV_INT interrupt. The secondary interrupt bits in R16403 (4013h) and R16404 (4014h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked by default. ADDRESS R16403 (4013h) BIT 9:0 LABEL UV_LDOn_EINT (Rising Edge triggered) Interrupt Status 3 R16404 (4014h) Note: Cleared when a ‘1’ is written. 3:0 UV_DCm_EINT Note: Cleared when a ‘1’ is written. 9:0 IM_UV_LDOn_EINT Interrupt mask. 0 = Do not mask interrupt. Interrupt Status 3 Mask R16412 (401Ch) DC-DCm Undervoltage interrupt (Rising Edge triggered) Interrupt Status 4 R16411 (401Bh) DESCRIPTION LDOn Undervoltage interrupt 1 = Mask interrupt. Default value is 1 (masked) 3:0 IM_UV_DCm_EINT Interrupt Status 4 Mask Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Notes: 1. n is a number between 1 and 10 that identifies the individual LDO Regulator (LDO1-LDO10). 2. m is a number between 1 and 4 that identifies the individual DC-DC Converter (DC1-DC4). Table 75 Undervoltage Interrupts w PD, February 2012, Rev 4.0 127 WM8321 Production Data 24 RESETS AND SUPPLY VOLTAGE MONITORING 24.1 RESETS The WM8321 provides hardware and software monitoring functions as inputs to a Reset management system. These functions enable the device to take appropriate action when power supplies are critically low or if a hardware or software fault condition is detected. There are different levels of Resets, providing different response mechanisms according to the condition that caused the Reset event. Where applicable, the WM8321 will automatically return to the ON state and resume normal operation as quickly as possible following a Reset. A System Reset occurs in the event of a Power Sequence Failure, Device overtemperature, PVDD undervoltage, Software ‘OFF’ request or VPMIC (LDO12) undervoltage condition. Under these conditions, the WM8321 asserts the RESET ¯¯¯¯¯¯ pin and transitions to the OFF state. In the case of VPMIC undervoltage, the WM8321 enters the BACKUP state. The contents of the Register map are not reset under System Reset conditions. A Device Reset occurs in the event of a Watchdog Timeout, Hardware Reset request or Converter (LDO or DC-DC) Undervoltage condition. Under these conditions, the WM8321 asserts the RESET ¯¯¯¯¯¯ pin and transitions to the OFF state. The contents of the Register map are cleared to default values, except for the RTC and software scratch registers, which are maintained. The WM8321 will automatically return to the ON state after performing the Device Reset. A Software Reset occurs when any value is written to Register 0000h, as described in Section 12.5. In this event, the WM8321 asserts the RESET ¯¯¯¯¯¯ pin and transitions to the OFF state. The Register map contents may or may not be affected, depending on the value of the SW_RESET_CFG field. See Section 24.3 for further details of Software Reset configuration. The WM8321 will automatically return to the ON state after performing the Software Reset. A Power-On Reset occurs when the supply voltage is less than the Power-On Reset threshold, as described in Section 24.4. In this event, the WM8321 is forced into the NO POWER state, as described in Section 11.2. All the contents of the Register map are lost in the NO POWER state. w PD, February 2012, Rev 4.0 128 WM8321 Production Data A summary of the WM8321 Resets is contained in Table 76 . RESET TYPE System Reset RESET CONDITION DESCRIPTION Power Sequence Failure DC Converters, LDOs or CLKOUT circuits have failed to start up within the permitted time. See Section 11.3. RESPONSE Assert RESET ¯¯¯¯¯¯ pin. AUTOMATIC RECOVERY No Select OFF state. If the Reset Condition is VPMIC (LDO12) undervoltage, then the WM8321 enters the BACKUP state. Device overtemperature An overtemperature condition has been detected. See Section 26. No PVDD undervoltage (1) PVDD is less than the userselectable threshold SYSLO_THR and SYSLO_ERR_ACT is configured to select OFF in this condition. See Section 24.4. PVDD undervoltage (2) PVDD is less than the SHUTDOWN voltage. See Section 24.4. No Software OFF request OFF has been commanded by writing CHIP_ON = 0. No No See Section 11.3 Device Reset The WM8321 supply voltage is less than the System Reset threshold. See Section 24.4. Watchdog timeout Watchdog timer has expired and the selected response is to generate a Device Reset. Assert RESET ¯¯¯¯¯¯ pin. See Section 25. Reset Register map (Note the RTC and software scratch registers are not reset.) Hardware Reset The RESET ¯¯¯¯¯¯ pin has been pulled low by an external source. See Section 24.2. Software Reset No VPMIC (LDO12) undervoltage Converter (LDO or DCDC) Undervoltage An undervoltage condition has been detected and the selected response is “Shut down system (Device Reset)” See Section 15. Software Reset Software Reset has been commanded by writing to Register 0000h. See Section 12.5. Yes Shutdown and restart the WM8321. Yes Yes Assert RESET ¯¯¯¯¯¯ pin. Yes Shutdown and restart the WM8321. See Section 24.3 for configurable options regarding the Register Map contents. Power On Reset Power On Reset The WM8321 supply voltage is less than the Power-On Reset (POR) threshold. See Section 24.4. The WM8321 is in the NO POWER state. No All register contents are lost. Table 76 Resets Summary In the cases where Automatic Recovery is supported (as noted in Table 76 ), the WM8321 will re-start the WM8321 following the Reset, and return the device to the ON state. The particular Reset condition which caused the return to the ON state will be indicated in the “ON Source” register - see Section 11.3. Note that, if a Watchdog timeout or Converter undervoltage fault persists, a maximum of 6 Device Resets will be attempted to initiate the start-up sequence. Similarly, a maximum of 6 Software Resets is permitted. If these limits are exceeded, the WM8321 will remain in the OFF state until the next valid ON state transition event occurs. The WM8321 asserts the RESET ¯¯¯¯¯¯ low as soon as the device begins the shutdown sequence. RESET ¯¯¯¯¯¯ is held low for the duration of the shutdown sequence and is held low in the OFF state. In the cases where Automatic Recovery is supported, RESET ¯¯¯¯¯¯ is automatically cleared (high) after successful completion of the startup sequence. The duration of the RESET ¯¯¯¯¯¯ low period after the startup sequence has completed is governed by the RST_DUR register field described in Section 11.7. w PD, February 2012, Rev 4.0 129 WM8321 Production Data 24.2 HARDWARE RESET A Hardware Reset is triggered when an external source pulls the RESET ¯¯¯¯¯¯ pin low. Under this condition, the WM8321 transitions to the OFF state. The contents of the Register map are cleared to default values, except for the RTC and software scratch registers, which are maintained. The WM8321 will then automatically schedule an ON state transition to resume normal operation. If the external source continues to pull the RESET ¯¯¯¯¯¯ pin low, then the WM8321 cannot fully complete the ON state transition following the Hardware Reset. In this case, the WM8321 will mask the external reset for up to 32 seconds. If the RESET ¯¯¯¯¯¯ pin is released (ie. it returns to logic ‘1’) during this time, then the ON state transition is completed and the Hardware Reset input is valid again from this point. If the RESET ¯¯¯¯¯¯ pin is not released, then the WM8321 will force an OFF condition on expiry of the 32 seconds timeout. Recovery from this forced OFF condition cannot occur until the external reset condition is de-asserted, followed by a valid ON event. If an ON event occurs before the external reset is de-asserted, then start-up will be attempted, but the transition will be unsuccessful, causing a return to the OFF state. It is possible to mask the RESET ¯¯¯¯¯¯ pin input in the SLEEP state by setting the RST_SLP_MSK register bit as described in Section 11.7. 24.3 SOFTWARE RESET A Software Reset is triggered by writing to Register 0000h, as described in Section 12.5. In this event, the WM8321 asserts the RESET ¯¯¯¯¯¯ pin and transitions to the OFF state. If the Reset occurred in the ON state, then the WM8321 will automatically return to the ON state following the Reset. The SWRST_DLY register field determines whether a time delay is applied between the Software Reset command and the resultant shutdown and start-up sequences. When the SWRST_DLY bit is set, the programmable time delay PWRSTATE_DLY is applied before commencing the shutdown sequence. The timing of the Software Reset is illustrated in Figure 25. See Section 11.3 for a definition of the PWRSTATE_DLY register. The SW_RESET_CFG register field determines if the Register Map is reset under a Software Reset condition. Note that the SW_RESET_CFG control register is locked by the WM8321 User Key. This register can only be changed by writing the appropriate code to the Security register, as described in Section 12.4. ADDRESS R16387 (4003h) BIT 9 LABEL SWRST_DLY DEFAULT 0 0 = No delay Power State R16390 (4006h) DESCRIPTION Software Reset Delay 1 = Software Reset is delayed by PWRSTATE_DLY following the Software Reset command 10 SW_RESET_C FG Reset Control 1 Software Reset Configuration. Selects whether the register map is reset to default values when Software Reset occurs. 0 = All registers except RTC and Software Scratch registers are reset by Software Reset 1 = Register Map is not affected by Software Reset Protected by user key Table 77 Software Reset Configuration w PD, February 2012, Rev 4.0 130 WM8321 Production Data Power State ON Software Reset (shutdown / start-up) RESET is de-asserted ON transition completes ON transition starts SW Reset command The timing details of the Software Reset are illustrated in Figure 25. ON RESET pin Time Time delay set by SWRST_DLY and PWRSTATE_DELAY 0ms, 1ms or 10ms OFF transition then ON transition Nominal duration = 10 x 2ms RESET delay set by RST_DUR 3ms, 11ms, 51ms or 101ms Figure 25 Software Reset Timing w PD, February 2012, Rev 4.0 131 WM8321 Production Data 24.4 SUPPLY VOLTAGE MONITORING The WM8321 includes a number of mechanisms to prevent the system from starting up, or to force it to shut down, when the power sources are critically low. The internal regulator LDO12 is powered from an internal domain equivalent to PVDD and generates an internal supply (VPMIC) to support various “always-on” functions. In the absence of the PVDD supply, LDO12 can be powered from a backup battery. (Note that PVDD is not maintained by the backup battery.) The VPMIC monitoring function controls the Power-On Reset circuit, which sets the threshold below which the WM8321 cannot operate. The operation of the VPMIC monitoring circuit is illustrated in Figure 26. The internal signal PORRST ¯¯¯¯¯¯¯ is governed by the VPOR thresholds. These determine when the WM8321 is kept in the NO POWER state. The internal signal PMICRST ¯¯¯¯¯¯¯¯ is governed by the VRES thresholds. These determine when the WM8321 is kept in the BACKUP state. NO POWER BACKUP BACKUP NO POWER The VPMIC monitoring thresholds illustrated in Figure 26 are fixed. The voltage levels are defined in the Electrical Characteristics - see Section 7.3. Figure 26 VPMIC Monitoring The operation of the PVDD monitoring circuit is illustrated in Figure 27. The VSHUTDOWN threshold is the voltage below which the WM8321 forces an OFF transition. This threshold voltage is fixed and is defined in the Electrical Characteristics - see Section 7.3. The VSYSOK threshold is the level at which the internal signal SYSOK is asserted. Any ON request will be inhibited if SYSOK is not set. The VSYSOK threshold can be set using the SYSOK_THR register field in accordance with the minimum voltage requirements of the application. Note that a hysteresis margin is added to the SYSOK_THR setting; see Section 7.3 for details. The VSYSLO threshold is the level at which the internal signal SYSLO is asserted. This indicates a PVDD undervoltage condition, at which a selectable response can be initiated. The VSYSLO threshold can be set using the SYSLO_THR register field. The action taken under this undervoltage condition is selected using the SYSLO_ERR_ACT register field, as defined in Table 78. An Interrupt event is associated with the SYSLO condition - see Section 17.2. The SYSLO status can be read from the SYSLO_STS register bit. This bit is asserted when PVDD is below the SYSLO threshold. w PD, February 2012, Rev 4.0 132 WM8321 Production Data The WM8321 can also indicate the status of the SYSOK signal via a GPIO pin configured as a “PVDD Good” output (see Section 21). A GPIO pin configured as “PVDD Good” output will be asserted when the PVDD is above the SYSOK threshold. Figure 27 PVDD Monitoring ADDRESS R16385 (4001h) BIT LABEL DEFAULT 15:14 SYSLO_ERR_ ACT 00 DESCRIPTION SYSLO Error Action Selects the action taken when SYSLO is asserted PVDD Control 00 = Interrupt 01 = WAKE transition 10 = Reserved 11 = OFF transition 11 SYSLO_STS 0 SYSLO Status 0 = Normal 1 = PVDD is below SYSLO threshold 6:4 SYSLO_THR [2:0] 010 SYSLO threshold (falling PVDD) This is the falling PVDD voltage at which SYSLO will be asserted 000 = 2.8V 001 = 2.9V … 111 = 3.5V 2:0 SYSOK_THR [2:0] 101 SYSOK threshold (rising PVDD) This is the rising PVDD voltage at which SYSOK will be asserted 000 = 2.8V 001 = 2.9V … 111 = 3.5V Note that the SYSOK hysteresis margin is added to these threshold levels. Table 78 PVDD Monitoring Control w PD, February 2012, Rev 4.0 133 WM8321 Production Data 25 WATCHDOG TIMER The WM8321 includes a Watchdog Timer designed to detect a possible software fault condition where the host processor has locked up. The Watchdog Timer is a free-running counter driven by the internal RC oscillator. The Watchdog Timer is enabled by default; it can be enabled or disabled by writing to the WDOG_ENA register bit. The Watchdog behaviour in SLEEP is configurable; it can either be set to continue as normal or to be disabled. The Watchdog behaviour in SLEEP is determined by the WDOG_SLPENA bit. The watchdog timer duration is set using WDOG_TO. The watchdog timer can be halted for debug purposes using the WDOG_DEBUG bit. The Watchdog reset source is selectable between Software and Hardware triggers. (Note that the deselected reset source has no effect.) If the Watchdog is not reset within a programmable timeout period, this is interpreted by the WM8321 as a fault condition. The Watchdog Timer then either triggers a Device Reset, or issues a WAKE request or raises an Interrupt. This primary action is determined by the WDOG_PRIMACT register field. If the Watchdog is not reset within a further timeout period of the Watchdog counter, a secondary action is triggered. The secondary action taken at this point is determined by the WDOG_SECACT register field. The Watchdog reset source is selected using the WDOG_RST_SRC register bit. When Software WDOG reset source is selected, the Watchdog is reset by writing a ‘1’ to the WDOG_RESET field. When Hardware WDOG reset source is selected, the Watchdog is reset by toggling a GPIO pin that has been configured as a Watchdog Reset Input (see Section 21). If a Device Reset is triggered by the watchdog timeout, the WM8321 asserts the RESET ¯¯¯¯¯¯ pin, resets the internal control registers (excluding the RTC) and initiates a start-up sequence. Note that, following a Device Reset, the action taken on subsequent timeout of the Watchdog Timer will be determined by the WDOG_PRIMACT register. If the watchdog timeout fault persists, then a maximum of 6 Device Reset attempts will be made. See Section 24. If the watchdog timeout occurs more than 6 times, the WM8321 will remain in the OFF state until the next valid ON state transition event occurs. Note that the Watchdog control registers are locked by the WM8321 User Key. These registers can only be changed by writing the appropriate code to the Security register, as described in Section 12.4. ADDRESS R16388 (4004h) BIT 15 LABEL WDOG_ENA DEFAULT 1 DESCRIPTION Watchdog Timer Enable 0 = Disabled Watchdog 1 = Enabled (enables the watchdog; does not reset it) Protected by user key 14 WDOG_DEBU G 0 Watchdog Pause 0 = Disabled 1 = Enabled (halts the Watchdog timer for system debugging) Protected by user key 13 WDOG_RST_S RC 1 Watchdog Reset Source 0 = Hardware only 1 = Software only Protected by user key 12 WDOG_SLPE NA 0 Watchdog SLEEP Enable 0 = Disabled 1 = Controlled by WDOG_ENA Protected by user key 11 WDOG_RESE T 0 Watchdog Software Reset 0 = Normal 1 = Watchdog Reset (resets the watchdog, if WDOG_RST_SRC = 1) Protected by user key w PD, February 2012, Rev 4.0 134 WM8321 Production Data ADDRESS BIT LABEL DEFAULT 9:8 WDOG_SECA CT 10 DESCRIPTION Secondary action of Watchdog timeout (taken after 2 timeout periods) 00 = No action 01 = Interrupt 10 = Device Reset 11 = WAKE transition Protected by user key WDOG_PRIMA CT 5:4 01 Primary action of Watchdog timeout 00 = No action 01 = Interrupt 10 = Device Reset 11 = WAKE transition Protected by user key WDOG_TO [2:0] 2:0 111 Watchdog timeout period 000 = 0.256s 001 = 0.512s 010 = 1.024s 011 = 2.048s 100 = 4.096s 101 = 8.192s 110 = 16.384s 111 = 32.768s Protected by user key Table 79 Controlling the Watchdog Timer The Watchdog timeout interrupt event is indicated by the WDOG_TO_EINT register field. This secondary interrupt triggers a primary Watchdog Interrupt, WDOG_INT (see Section 23). This can be masked by setting the mask bit as described in Table 80. ADDRESS R16401 (4011h) BIT LABEL DESCRIPTION 11 WDOG_TO_EINT Watchdog timeout interrupt. (Rising Edge triggered) Interrupt Status 1 R16409 (4019h) Note: Cleared when a ‘1’ is written. 11 IM_WDOG_TO_EINT Interrupt Status 1 Mask Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Table 80 Watchdog Timer Interrupts w PD, February 2012, Rev 4.0 135 WM8321 Production Data 26 TEMPERATURE SENSING The WM8321 provides temperature monitoring as status information and also for self-protection of the device. Temperature monitoring is always enabled in the ON and SLEEP states. The thermal warning temperature can be set using the THW_TEMP register field. The thermal warning hysteresis ensures that the THW_TEMP is not reset until the device temperature has dropped below the threshold by a suitable margin. The extent of the hysteresis can be selected using the THW_HYST register field. The Thermal Warning condition can be read using the THW_STS register bit. An overtemperature condition causes the thermal warning interrupt (TEMP_THW_CINT) to be set. The thermal warning interrupt is also set when the overtemperature condition clears, ie. when the device has returned to its normal operating limits. The thermal shutdown temperature is set at a fixed level. If a thermal shutdown condition is detected whilst in the ON or SLEEP states, then a System Reset is triggered, as described in Section 24.1, forcing a transition to the OFF state. The temperature sensing circuit is configured and monitored using the register fields described in Table 81. ADDRESS R16386 (4002h) BIT LABEL DEFAULT THW_HYST 3 1 DESCRIPTION Thermal Warning hysteresis 0 = 8 degrees C 1 = 16 degrees C THW_TEMP [1:0] 1:0 10 Thermal Warning temperature 00 = 90 degrees C 01 = 100 degrees C 10 = 110 degrees C 11 = 120 degrees C R16397 (400Dh) THW_STS 15 0 Thermal Warning status 0 = Normal 1 = Overtemperature Warning (warning temperature is set by THW_TEMP) Table 81 Temperature Sensing Control The thermal warning interrupt event is indicated by the TEMP_THW_CINT register field. This secondary interrupt triggers a primary Thermal Interrupt, TEMP_INT (see Section 23). This can be masked by setting the mask bit as described in Table 82. ADDRESS R16401 (4011h) BIT 1 LABEL TEMP_THW_CINT (Rising and Falling Edge triggered) Interrupt Status 1 R16410 (4019h) DESCRIPTION Thermal Warning interrupt Note: Cleared when a ‘1’ is written. 1 IM_TEMP_THW_CINT Interrupt Status 1 Mask Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Table 82 Thermal Interrupts w PD, February 2012, Rev 4.0 136 WM8321 Production Data 27 VOLTAGE AND CURRENT REFERENCES 27.1 VOLTAGE REFERENCE (VREF) The main voltage reference generated by the WM8321 is bonded to the VREFC pin. The accuracy of this reference is optimised by factory-set trim registers. The voltage reference (VREF) requires an external decoupling capacitor; a 100nF X5R capacitor is recommended, as noted in Section 30.2. Omitting this capacitor will result in increased noise on the voltage reference; this will particularly affect the analogue LDOs. The voltage reference circuit includes a low-power mode, which enables power consumption to be minimised where appropriate. The low-power reference mode may lead to increased noise on the voltage reference; this mode should only be selected when minimum power consumption is more important than voltage stability. Note that the Low Power Reference mode is not supported when the Auxiliary ADC function is enabled. The Low Power Reference mode is enabled when REF_LP register is set. The Low Power Reference mode should only be enabled when the Auxiliary ADC is disabled. Enabling the Low Power Reference mode will lead to a malfunction of the Auxiliary ADC function. ADDRESS R16387 (4003h) BIT 12 LABEL REF_LP DEFAULT 0 DESCRIPTION Low Power Voltage Reference Control 0 = Normal 1 = Low Power Reference Mode select Note that Low Power Reference Mode is only supported when the Auxiliary ADC is disabled. Table 83 Low Power Voltage Reference Control 27.2 CURRENT REFERENCE (IREF) The Power Management circuits of the WM8321 use an integrated current reference. This current reference (IREF) requires the connection of an external resistor to the IREFR pin; a 100k (1%) resistor is recommended, as noted in Section 30.2. The WM8321 will malfunction if this resistor is omitted. w PD, February 2012, Rev 4.0 137 w 4014 16404 4017 4013 16403 16407 4012 16402 4015 4011 16401 4016 4010 16400 16406 400F 16405 400E 16398 16399 4008 16392 400D 4007 16391 16397 4006 16390 400C 4005 16389 400B 4004 16388 16396 4003 16387 16395 4002 16386 4009 4001 16385 400A 4000 16384 16394 0007 7 16393 0006 6 0003 3 0004 0002 2 0005 0001 1 4 0000 0 5 Hex Addr Dec Addr Name 0 Reserved CHIP_SLP 0 RECONFIG_ AT_ON 0 Reset Control Control Interface 0 0 0 11 REF_LP 0 0 0 0 0 0 0 0 0 0 0 0 ON_PIN_PRIMACT[1:0] 0 0 0 0 0 0 0 Interrupt Status 3 Interrupt Status 4 Interrupt Status 5 Reserved IRQ Config 0 0 0 0 0 0 0 Interrupt Status 2 0 0 0 TEMP_INT ON_TRANS ON Source OFF Source 0 PS_INT THW_STS System Status 0 0 PPM_SYSLO _EINT 0 GPIO Level Interrupt Status 1 0 Security Key 2 0 System Interrupts OTP_PROG OTP Control 0 0 0 0 0 0 0 0 0 0 0 0 GP_INT 0 0 0 0 0 0 0 0 0 GP12_EINT 0 0 0 0 0 GP11_EINT 0 0 0 0 0 OFF_PVDD ON_SYSLO 0 GP11_LVL ON_PIN_CI WDOG_TO_ NT EINT OFF_GPIO ON_GPIO 0 GP12_LVL 0 0 0 0 PPM_INT AUXADC_IN T 0 0 0 GP5_LVL 0 0 GP3_LVL 0 0 0 GP1_LVL 0 OTP_PAGE[1:0] 0 RST_DUR[1:0] ON_PIN_TO[1:0] GP2_LVL MAIN_STATE[4:0] GP4_LVL 0 AUTOINC 0 WDOG_TO[2:0] Bin Default 0000_0000_0000_0100 1000_0100_0111_0011 0000_0001_0000_0000 1010_P010_0001_0111 UU00_1000_0000_0000 0000_0000_0000_1010 0000_0000_0010_0101 0110_0010_0100_0110 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0 OFF_SW_R EQ RTC_INT 0 OTP_INT OFF_ON_PI N 0 0 0 0 HC_INT 0 UV_INT 0 0 0 GP10_EINT 0 0 GP9_EINT 0 0 GP8_EINT 0 0 GP7_EINT 0 0 GP6_EINT 0 0 GP5_EINT 0 0 0 GP4_EINT 0 0 GP3_EINT IRQ_OD 0 GP2_EINT IM_IRQ 0 GP1_EINT 0000_0000_0000_0010 0000_0000_0000_0000 0000_PPPP_PPPP_PPPP 0000_00PP_PP00_PPPP 0 0000_00PP_PPPP_PPPP HC_DC2_EI HC_DC1_EI XTAL_STRT XTAL_TAMP NT NT _EINT ER_EINT UV_DC4_EI UV_DC3_EI UV_DC2_EI UV_DC1_EI NT NT NT NT 0000_0000_00PP_0PPP P00P_P00P_PPPP_PPP0 PPPP_P00P_P0PP_P0PP 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 U010_0000_0000_0000 UV_LDO10_ UV_LDO9_E UV_LDO8_E UV_LDO7_E UV_LDO6_E UV_LDO5_E UV_LDO4_EI UV_LDO3_ UV_LDO2_E UV_LDO1_E EINT INT INT INT INT INT NT EINT INT INT 0 0 0 GP6_LVL 0 0 0 0 0 0 0 0 THW_TEMP[1:0] SYSOK_THR[2:0] 0 0 0 0 0 0 0 AUXADC_D AUXADC_D AUXADC_D AUXADC_D AUXADC_D RTC_PER_E RTC_ALM_ TEMP_THW 0 COMP4_EIN COMP3_EIN COMP2_EIN COMP1_EIN ATA_EINT INT EINT _CINT T T T T OTP_CMD_ OTP_ERR_E PS_POR_EI PS_SLEEP_ PS_ON_WA 0 0 0 0 END_EINT INT NT OFF_EINT KE_EINT 0 0 0 0 0 0 GP7_LVL 0 0 0 0 0 0 0 0 0 0 0 1 ON_WDOG_ ON_SW_RE ON_RTC_AL RESET_CNV RESET_WD ON_ON_PIN RESET_SW RESET_HW TO Q M _UV OG XTAL_OK GP8_LVL 0 0 GP9_LVL OTP_READ_LVL[1:0] OFF_THER R 0 GP10_LVL 0 OTP_FINAL OTP_VERIFY OTP_WRITE OTP_READ ON_PIN_INT WDOG_INT OFF_INTLD OFF_PWR_ O_ERR SEQ 0 0 0 0 OTP_MEM OTP_BULK 0 ON_PIN_ST S 0 0 THW_HYST 0 0 0 0 0 0 0 2 0000_0000_0000_0000 0 0 0 0 0 0 0 0 0 WDOG_PRIMACT[1:0] 0 0 SYSLO_THR[2:0] 3 CHILD_REV[7:0] 4 AUXRST_SL RST_SLP_M RST_SLPEN PENA SK A 0 0 0 0 0 0 0 0 0 0 5 SW_SCRATCH[15:0] 0 0 0 ON_PIN_SECACT[1:0] 0 SW_RESET_C FG 0 0 WDOG_SECACT[1:0] 0 0 0 0 SWRST_DL Y 0 0 0 0 0 0 0 0 6 Software Scratch 0 0 0 0 0 0 0 0 0 PARENT_ID[15:0] 0 0 0 0 0 0 7 0000_0000_0000_0000 0 0 0 8 CHIP_ID[15:0] 0 0 0 0 0 0 0 0 9 SECURITY[15:0] 0 0 0 0 0 0 0 0 0 0 0 10 PWRSTATE_DLY[1:0] 0 SYSLO_STS 0 0 0 0 0 0 PARENT_REV[7:0] 12 Security Key 0 0 0 ON Pin Control Watchdog CHIP_ON Power State 0 0 0 0 0 0 0 13 WDOG_DEB WDOG_RST WDOG_SLP WDOG_RES WDOG_ENA UG _SRC ENA ET 0 Thermal Monitoring PVDD Control 0 0 0 0 0 0 14 SYSLO_ERR_ACT[1:0] 0 Reserved Parent ID 0 0 Reserved 0 Reserved Reserved 0 15 Reserved Revision Reset ID WM8321 Production Data 28 REGISTER MAP OVERVIEW PD, February 2012, Rev 4.0 138 0 w 1 3 0 2 1 IM_HC_INT 0 IM_UV_INT 0000_0000_0000_0000 RTC_ALM[15:0] 402E 402F 4030 4031 4032 4033 4034 4035 4036 4037 16430 16432 16433 16434 16435 16436 16437 16438 16439 402D 16429 16431 402B 402C 16427 16428 4029 402A 16425 4028 16424 16426 4026 4027 16422 16423 4025 16421 0 0 Reserved Reserved 0 0 Reserved Reserved 0 0 0 0 0 Reserved 0 DCMP4_SRC[2:0] Comparator 4 0 0 0 DCMP3_GT DCMP4_GT DCMP3_SRC[2:0] Comparator 3 0 DCMP2_GT 0 DCMP2_SRC[2:0] 0 0 Comparator 2 0 0 0 AUX_SLPE NA DCMP1_GT 0 Comparator Control 0 AUX_CVT_ ENA 0 0 0 0 0 0 0 0 DCMP1_SRC[2:0] 0 0 0 0 0 0 0 0 0 AUX_DATA_SRC[3:0] 0 0 0 0 0 0 0 RTC_SYNC _BUSY Comparator 1 AUX_ENA AuxADC Control AuxADC Source AuxADC Data 0 0 Reserved 0 Reserved Reserved 0 0 RTC Trim Reserved RTC_VALID RTC Alarm 2 4024 16420 RTC Control 0000_0000_0000_0000 RTC_ALM[31:16] RTC Alarm 1 4023 16419 0 0 0 0 0 0 0 0 0 RTC_ALM_EN A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCOMP4_S DCOMP2_S DCOMP1_S DCOMP3_STS TS TS TS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCMP4_THR[11:0] DCMP3_THR[11:0] DCMP2_THR[11:0] DCMP1_THR[11:0] 0 AUX_PVDD _SEL 0 0 0 0 0 AUX_CHIP_ TEMP_SEL 0 0 0 0 0 0 RTC_TRIM[9:0] RTC_PINT_FREQ[2:0] 0 AUX_DATA[11:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUX_GPIO AUX_GPIO1 AUX_GPIO1 12_SEL 1_SEL 0_SEL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCMP4_EN DCMP3_EN DCMP2_EN DCMP1_EN A A A A 0 AUX_RATE[5:0] 0 0 0 0 0 0 0 0 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0U00_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0 0 0000_0000_0000_0000 0 0 RTC_TIME[15:0] 0 0 RTC_TIME[31:16] 0 0 RTC Time 1 0 0 RTC Time 2 4021 4022 16417 16418 0 0 0000_0000_0000_0000 0 0 RTC_WR_CNT[15:0] 0 0 0 0 Reserved 0 RTC Write Counter 0 401F 0 0 4020 0 0000_1111_1111_1111 0 0000_0011_1000_1111 0 0 0000_0011_1111_1111 0000_0000_0011_0111 1001_1001_1111_1110 16415 0 0 0 IM_HC_DC2 IM_HC_DC1 IM_XTAL_S _EINT _EINT TART_EINT 0 Bin Default 1111_1001_1011_1011 IM_GP12_EI IM_GP11_EIN IM_GP10_EI IM_GP9_EIN IM_GP8_EIN IM_GP7_EIN IM_GP6_EIN IM_GP5_EIN IM_GP4_EIN IM_GP3_EI IM_GP2_EIN IM_GP1_EIN NT T NT T T T T T T NT T T 0 4 IM_UV_DC4 IM_UV_DC IM_UV_DC2 IM_UV_DC1 _EINT 3_EINT _EINT _EINT 0 5 IM_RTC_INT IM_OTP_INT IM_AUXAD IM_AUXAD IM_AUXAD IM_AUXAD IM_AUXAD IM_RTC_PE IM_RTC_AL IM_TEMP_T 0 C_DATA_EI C_DCOMP4 C_DCOMP3 C_DCOMP2 C_DCOMP1 R_EINT M_EINT HW_CINT NT EINT EINT EINT EINT IM_OTP_CM IM_OTP_ER IM_PS_POR IM_PS_SLE IM_PS_ON_ 0 0 0 0 0 EP_OFF_EIN D_END_EIN R_EINT _EINT WAKE_EINT T T IM_UV_LDO IM_UV_LDO IM_UV_LDO IM_UV_LDO IM_UV_LDO IM_UV_LDO IM_UV_LDO IM_UV_LD IM_UV_LDO IM_UV_LDO 10_EINT 9_EINT 8_EINT 7_EINT 6_EINT 5_EINT 4_EINT O3_EINT 2_EINT 1_EINT 0 6 16416 0 0 0 0 7 0 16414 0 0 0 0 8 IM_AUXAD IM_PPM_INT C_INT Reserved 401C 401D 16412 16413 0 0 0 Interrupt Status 3 Mask 0 0 0 9 401E 401B 16411 0 0 0 Interrupt Status 2 Mask 0 0 10 0 401A 16410 0 IM_ON_PIN_ IM_WDOG_ CINT TO_EINT 11 IM_PPM_SY SLO_EINT 12 Interrupt Status 1 Mask 13 0 4019 16409 14 IM_TEMP_IN IM_ON_PIN_ IM_WDOG_I IM_GP_INT T INT NT 15 IM_PS_INT Nam e System Interrupts Mask Interrupt Status 4 Mask 4018 16408 Interrupt Status 5 Mask Hex Addr Dec Addr Production Data WM8321 PD, February 2012, Rev 4.0 139 w 4041 4042 4043 4044 4045 4046 4047 4048 4049 16449 16450 16451 16452 16453 16454 16455 16456 16457 404F 4050 4051 4052 4053 4054 4055 4056 4057 16463 16464 16465 16466 16467 16468 16469 16470 16471 404E 4040 16448 404D 403F 16447 16462 403E 16446 16461 403D 16445 404C 403C 16444 16460 403B 16443 404A 403A 16442 404B 4039 16441 16458 4038 16440 16459 Hex Addr Dec Addr 0 0 Reserved Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTLDO_UV _STS LDO Enable DCDC Status LDO Status DCDC UV Status LDO UV Status 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DC1_RATE[1:0] DC1_ERR_ACT[1:0] DC1 Control 2 0 DC1_HWC_SRC[1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DC1_PHAS E DC2_OV_S DC1_OV_S TS TS 0 0 0 0 0 0 DC1 Control 1 0 0 0 0 0 0 Reserved 0 DCDC Enable 0 Reserved 0 0 Reserved GP12_PULL[1:0] LED2_SRC[1:0] 0 Reserved GP12_INT_ GP12_PWR MODE _DOM GP11_PULL[1:0] Status LED 2 0 Reserved GP12_POL GP11_INT_ GP11_PWR MODE _DOM GP10_PULL[1:0] 0 0 Reserved GP11_POL GP10_INT_ GP10_PWR MODE _DOM GP9_PULL[1:0] 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 LDO10_EN LDO9_ENA A 0 0 0 LED2_MODE[1:0] LED1_MODE[1:0] 0 0 0 0 0 0 0 0 GP12_OD GP11_OD GP10_OD GP9_OD GP8_OD GP7_OD GP6_OD GP5_OD GP4_OD GP3_OD GP2_OD GP1_OD 7 0 LDO8_STS EPE2_STS LDO8_ENA EPE2_ENA 0 0 0 0 0 0 0 0 0 0 0 0 GP12_ENA GP11_ENA GP10_ENA GP9_ENA GP8_ENA GP7_ENA GP6_ENA GP5_ENA GP4_ENA GP3_ENA GP2_ENA GP1_ENA 0 LDO7_STS EPE1_STS LDO7_ENA EPE1_ENA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 LDO6_STS 0 LDO6_ENA 0 0 0 0 LDO5_STS 0 LDO5_ENA 0 0 0 LED2_SEQ_LEN[1:0] LED1_SEQ_LEN[1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 DC1_HWC_MODE[1:0] DC1_HWC_V SEL 0 DC1_FLT 0 DC1_HC_THR[2:0] DC1_SOFT_START[1:0] LDO9_UV_ LDO8_UV_ LDO7_UV_ LDO6_UV_ LDO5_UV_ STS STS STS STS STS DC1_FREQ[1:0] LDO10_UV _STS DC2_HC_ST DC1_HC_ST S S 0 0 0 LDO11_STS LDO10_STS LDO9_STS 0 LDO11_ENA 0 0 0 0 0 0 0 0 0 0 0 0 0 GP10_POL GP9_INT_M GP9_PWR_ ODE DOM GP8_PULL[1:0] 0 GP8_POL GP9_POL GP8_INT_M GP8_PWR_ ODE DOM GP7_PULL[1:0] 0 GP7_POL GP7_INT_M GP7_PWR_ ODE DOM GP6_PULL[1:0] 0 GP6_POL GP6_INT_M GP6_PWR_ ODE DOM GP5_PULL[1:0] 0 GP5_POL GP5_INT_M GP5_PWR_ ODE DOM GP4_PULL[1:0] LED1_SRC[1:0] 0 Reserved GP4_POL GP4_INT_M GP4_PWR_ ODE DOM GP3_PULL[1:0] Status LED 1 0 Reserved GP3_POL GP3_INT_M GP3_PWR_ ODE DOM 0 GP12_DIR GPIO12 Control GP2_POL GP2_INT_M GP2_PWR_ ODE DOM 10 GP2_PULL[1:0] 11 GP1_POL 12 GP1_INT_M GP1_PWR_ ODE DOM 13 GP1_PULL[1:0] 14 0 GP11_DIR GPIO11 Control GP7_DIR GPIO7 Control GP10_DIR GP6_DIR GPIO6 Control GPIO10 Control GP5_DIR GPIO5 Control GP8_DIR GP4_DIR GPIO4 Control GP9_DIR GP3_DIR GPIO3 Control GPIO9 Control GP2_DIR GPIO2 Control GPIO8 Control 15 GP1_DIR Nam e GPIO1 Control 0 0 0 0 0 0 0 0 0 0 DC3_ENA DC2_ENA 0 0 DC3_STS DC2_STS DC1_STS 0 0 0 0 DC1_FAST_ DC1_HC_IN DRV D_ENA DC1_CAP[1:0] LDO4_UV_ LDO3_UV_ LDO2_UV_ LDO1_UV_ STS STS STS STS DC4_UV_ST DC3_UV_S DC2_UV_S DC1_UV_S S TS TS TS LDO4_STS LDO3_STS LDO2_STS LDO1_STS DC4_STS LDO1_ENA DC1_ENA 0 0 LED2_DUTY_CYC[1:0] LDO4_ENA LDO3_ENA LDO2_ENA DC4_ENA 0 0 0 0 0 0 0 0 0 0 LED1_DUTY_CYC[1:0] 0 0 0 0 0 0 0 0 GP12_FN[3:0] GP11_FN[3:0] GP10_FN[3:0] GP9_FN[3:0] GP8_FN[3:0] GP7_FN[3:0] GP6_FN[3:0] GP5_FN[3:0] GP4_FN[3:0] GP3_FN[3:0] GP2_FN[3:0] LED2_DUR[1:0] 0 1 GP1_FN[3:0] 2 LED1_DUR[1:0] 0 0 0 0 0 0 0 0 3 Bin Default 0000_0011_0000_0000 1000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0UUU_UUUU_UUUU 0000_0000_UU00_UUUU 0000_0000_0000_0000 0000_0000_0000_0000 1100_0000_0010_0110 1100_0000_0010_0110 0000_0000_0000_0000 0000_0000_0000_0000 0000_0110_0000_0010 0000_0000_0000_0001 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 1010_0100_0000_0000 1010_0100_0000_0000 1010_0100_0000_0000 1010_0100_0000_0000 1010_0100_0000_0000 1010_0100_0000_0000 1010_0100_0000_0000 1010_0100_0000_0000 1010_0100_0000_0000 1010_0100_0000_0000 1010_0100_0000_0000 1010_0100_0000_0000 WM8321 Production Data PD, February 2012, Rev 4.0 140 w 4077 16503 4074 16500 4075 4073 16499 4076 4072 16498 16501 4071 16497 16502 4070 16496 4068 16488 406F 4067 16487 406E 4066 16486 16495 4065 16485 16494 4064 16484 406D 4063 16483 16493 4062 16482 406C 4061 16481 406B 4060 16480 16492 405F 16491 405E 16478 16479 4069 405D 16477 406A 405C 16476 16489 405B 16475 16490 4059 405A 16473 4058 16472 16474 Hex Addr Dec Addr 0 0 DC2_RATE[1:0] DC2_ERR_ACT[1:0] DC2 Control 1 DC2 Control 2 0 0 0 0 0 LDO6_HWC_SRC[1:0] 0 LDO6_ERR_ACT[1:0] 0 LDO5_ON_SLOT[2:0] LDO5_SLP_SLOT[2:0] LDO5 ON Control LDO6 Control 0 0 LDO5_HWC_SRC[1:0] LDO5 SLEEP Control 0 0 LDO4_SLP_SLOT[2:0] LDO4 SLEEP Control LDO5_ERR_ACT[1:0] 0 LDO4_ON_SLOT[2:0] LDO5 Control 0 0 LDO4_HWC_SRC[1:0] LDO4 ON Control 0 0 LDO3_SLP_SLOT[2:0] LDO3 SLEEP Control LDO4_ERR_ACT[1:0] 0 LDO4 Control 0 0 LDO3_HWC_SRC[1:0] LDO3_ON_SLOT[2:0] LDO3 ON Control 0 0 LDO2_SLP_SLOT[2:0] LDO2 SLEEP Control LDO3_ERR_ACT[1:0] 0 LDO3 Control 0 0 LDO2_HWC_SRC[1:0] LDO2_ON_SLOT[2:0] LDO2 ON Control 0 0 LDO2_ERR_ACT[1:0] 0 LDO1_ON_SLOT[2:0] LDO1_SLP_SLOT[2:0] LDO1 ON Control LDO2 Control 0 0 0 LDO1_HWC_SRC[1:0] LDO1 SLEEP Control 0 0 LDO1_ERR_ACT[1:0] 0 DC4_ON_SLOT[2:0] LDO1 Control 0 DC4_HWC_SRC[1:0] DC4_SLP_SLOT[2:0] 0 DC4 ON Config DC4_ERR_ACT[1:0] DC4 SLEEP Control DC4 Control 2 0 DC4 Control 1 DC4_PHASE 0 DC3 SLEEP Control DC4_SLV DC3_SLP_SLOT[2:0] 0 0 0 DC3_HWC_SRC[1:0] 0 0 DC3_PHASE DC3_ON_SLOT[2:0] DC3_ERR_ACT[1:0] 0 0 DC2_DVS_SRC[1:0] DC3 ON Config DC3 Control 2 0 DC3 Control 1 0 0 0 DC2_SLP_SLOT[2:0] 0 DC2 DVS Control 0 DC2_ON_SLOT[2:0] DC2 SLEEP Control 0 DC2_HWC_SRC[1:0] DC2_PHASE DC2 ON Config 0 0 0 11 DC1_DVS_SRC[1:0] 0 0 0 DC1_SLP_SLOT[2:0] 12 DC1 DVS Control 13 DC1 SLEEP Control 14 0 15 DC1_ON_SLOT[2:0] Name DC1 ON Config 0 0 0 0 0 0 LDO1_SLP_ MODE 0 0 0 LDO2_SLP_ MODE 0 0 0 LDO3_SLP_ MODE 0 0 0 LDO4_SLP_ MODE 0 0 0 LDO6_FLT 0 LDO5_SLP_ MODE LDO6_HWC_V LDO6_HWC_MODE[1:0] SEL 0 0 LDO5_ON_ MODE LDO5_FLT 0 LDO4_ON_ MODE LDO5_HWC_V LDO5_HWC_MODE[1:0] SEL 0 0 LDO4_FLT 0 LDO3_ON_ MODE LDO4_HWC_V LDO4_HWC_MODE[1:0] SEL 0 0 LDO3_FLT 0 LDO2_ON_ MODE LDO2_FLT 0 LDO1_ON_ MODE LDO1_FLT 0 DC4_OVP DC4_ON_MODE[1:0] LDO3_HWC_V LDO3_HWC_MODE[1:0] SEL 0 0 0 DC4_FLT DC4_SLP_MODE[1:0] DC4_HWC_MODE[1:0] 0 DC3_SLP_MODE[1:0] 0 DC3_FLT DC3_OVP LDO2_HWC_V LDO2_HWC_MODE[1:0] SEL 0 0 0 0 DC3_ON_MODE[1:0] 0 0 0 0 DC2_FLT 0 DC3_HWC_MODE[1:0] 0 0 DC2_SLP_MODE[1:0] LDO1_HWC_V LDO1_HWC_MODE[1:0] SEL 0 0 DC4_HWC_VS EL 0 0 0 DC3_HWC_VS EL 0 0 DC2_ON_MODE[1:0] DC2_HWC_MODE[1:0] 0 DC2_FREQ[1:0] 0 0 0 0 7 DC1_SLP_MODE[1:0] 8 0 9 DC1_ON_MODE[1:0] DC2_HWC_VS EL 0 0 0 10 0 LDO6_SWI 0 0 LDO5_SWI 0 0 LDO4_SWI 0 0 LDO3_SWI 0 0 LDO2_SWI 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LDO3_SLP_VSEL[4:0] LDO4_SLP_VSEL[4:0] LDO4_ON_VSEL[4:0] LDO5_ON_VSEL[4:0] LDO5_SLP_VSEL[4:0] 0 0 0 0 DC4_CAP[1:0] 0 0 0 0 0 0 LDO6_LP_M ODE LDO5_LP_M ODE LDO4_LP_M ODE LDO3_LP_M ODE LDO2_LP_M ODE LDO1_LP_M ODE DC4_ON_VSEL[1:0] LDO3_ON_VSEL[4:0] 0 0 DC3_CAP[1:0] DC3_ON_VSEL[1:0] LDO2_SLP_VSEL[4:0] 0 DC2_CAP[1:0] DC2_ON_VSEL[1:0] LDO2_ON_VSEL[4:0] 0 0 DC2_FAST_ DC2_HC_IN DRV D_ENA LDO1_SLP_VSEL[4:0] 0 1 DC1_ON_VSEL[1:0] LDO1_ON_VSEL[4:0] DC4_SLP_VSEL[6:0] 0 DC4_STNBY_LIM[1:0] DC4_ON_VSEL[6:2] 0 0 DC3_SLP_VSEL[6:0] DC4_SOFT_START[1:0] 0 0 2 DC3_STNBY_LIM[1:0] DC2_DVS_VSEL[6:0] DC3_ON_VSEL[6:2] 0 0 DC2_SLP_VSEL[6:0] DC2_ON_VSEL[6:2] 0 DC1_DVS_VSEL[6:0] DC3_SOFT_START[1:0] 0 3 DC1_SLP_VSEL[6:0] DC1_ON_VSEL[6:2] DC2_SOFT_START[1:0] 5 DC2_HC_THR[2:0] LDO1_SWI 0 0 0 0 0 6 Bin Default 0000_0010_0000_0000 0000_0001_0000_0000 0000_0000_0000_0000 0000_0010_0000_0000 0000_0001_0000_0000 0000_0000_0000_0000 0000_0010_0000_0000 0000_0001_0000_0000 0000_0000_0000_0000 0000_0010_0000_0000 0000_0001_0000_0000 0000_0000_0000_0000 0000_0010_0000_0000 0000_0001_0000_0000 0000_0000_0000_0000 0000_0010_0000_0000 0000_0011_0000_0000 0000_0001_0000_0000 0000_0011_0000_0000 0000_0000_0001_0100 0000_0011_0000_0000 0000_0001_0000_0000 0000_0011_0000_0000 0000_0000_0001_0100 0000_0000_0000_0000 0000_0011_0000_0000 0000_0001_0000_0000 0000_0011_0000_0000 1001_0000_0000_0000 0000_0000_0000_0000 0000_0011_0000_0000 0000_0001_0000_0000 Production Data WM8321 PD, February 2012, Rev 4.0 141 w 4085 4086 4087 4088 16517 16518 16519 16520 4090 4091 4092 4093 4094 4095 4096 4097 16528 16529 16530 16531 16532 16533 16534 16535 408F 4084 16516 408E 4083 16515 16527 4082 16514 16526 4081 16513 408D 4080 16512 16525 407F 16511 408C 407E 16510 408B 407D 16509 16524 407C 16508 16523 407B 16507 4089 407A 16506 408A 4079 16505 16522 4078 16504 16521 Hex Addr Dec Addr 0 0 Reserved 0 0 0 0 0 CLKOUT_EN A XTAL_INH 0 0 0 0 0 0 Reserved Power Good Source 1 Power Good Source 2 Clock Control 1 Clock Control 2 Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTAL_BKUP ENA XTAL_ENA CLKOUT_O D 0 0 0 0 0 0 0 0 0 0 0 0 Reserved 0 0 Reserved 0 0 0 EPE2 Control 0 EPE1_HWC_SRC[1:0] EPE2_HWC_SRC[1:0] EPE1_ON_SLOT[2:0] EPE2_ON_SLOT[2:0] EPE1 Control 0 0 LDO11_SLP_SLOT[2:0] LDO11 SLEEP Control 0 0 0 0 LDO11_FRC ENA LDO11_ON_SLOT[2:0] 0 0 LDO11 ON Control 0 0 LDO10_SLP_SLOT[2:0] LDO10 SLEEP Control 0 0 0 LDO10_ON_SLOT[2:0] LDO10 ON Control LDO10 Control 0 LDO9_SLP_SLOT[2:0] LDO9 SLEEP Control 0 LDO10_HWC_SRC[1:0] 0 LDO9_ON_SLOT[2:0] LDO10_ERR_ACT[1:0] 0 0 LDO9_HWC_SRC[1:0] LDO9 ON Control 0 0 LDO8_SLP_SLOT[2:0] LDO8 SLEEP Control LDO9_ERR_ACT[1:0] 0 LDO8_ON_SLOT[2:0] LDO8 ON Control LDO9 Control 0 0 LDO8_HWC_SRC[1:0] 0 0 LDO7_SLP_SLOT[2:0] LDO8_ERR_ACT[1:0] LDO7 SLEEP Control LDO8 Control 0 0 11 LDO7_HWC_SRC[1:0] 0 0 LDO7_ON_SLOT[2:0] LDO7_ERR_ACT[1:0] LDO7 ON Control LDO7 Control 0 12 LDO6_SLP_SLOT[2:0] 13 LDO6 SLEEP Control 14 0 15 LDO6_ON_SLOT[2:0] Name LDO6 ON Control 0 0 9 0 0 LDO6_SLP_ MODE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LDO9_OK 0 0 0 0 0 0 0 0 0 0 0 0 LDO8_OK 0 0 0 0 0 0 0 0 0 0 LDO6_OK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 LDO5_OK CLKOUT_SLPSLOT[2:0] LDO7_OK 0 0 0 0 EPE2_SLP_SLOT[2:0] 0 0 0 EPE1_SLP_SLOT[2:0] 0 LDO11_VSE L_SRC EPE2_HWC ENA 0 0 0 0 EPE1_HWC ENA CLKOUT_SLOT[2:0] LDO10_OK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LDO10_SLP _MODE 0 0 0 0 0 0 0 LDO9_SLP_ MODE 0 0 LDO9_ON_ MODE 0 0 0 0 0 0 0 0 0 5 LDO10_ON_ MODE 0 0 LDO9_SWI 0 0 LDO8_SWI 0 0 LDO7_SWI 0 0 6 LDO10_HWC_ LDO10_HWC_MODE[1:0] LDO10_FLT LDO10_SWI VSEL 0 0 LDO9_FLT 0 LDO8_ON_ MODE LDO8_SLP_ MODE LDO9_HWC_V LDO9_HWC_MODE[1:0] SEL 0 0 LDO8_FLT 0 LDO7_ON_ MODE LDO7_SLP_ MODE LDO8_HWC_V LDO8_HWC_MODE[1:0] SEL 0 0 LDO7_FLT 7 8 LDO6_ON_ MODE LDO7_HWC_V LDO7_HWC_MODE[1:0] SEL 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 LDO3_OK DC3_OK 0 0 0 0 0 0 0 0 0 0 0 0 0 LDO2_OK DC2_OK 0 0 0 0 0 LDO11_SLP_VSEL[3:0] LDO11_ON_VSEL[3:0] 0 LDO10_SLP_VSEL[4:0] LDO10_ON_VSEL[4:0] 0 LDO9_SLP_VSEL[4:0] LDO9_ON_VSEL[4:0] 0 LDO8_SLP_VSEL[4:0] LDO8_ON_VSEL[4:0] 0 LDO7_SLP_VSEL[4:0] LDO7_ON_VSEL[4:0] 0 LDO6_SLP_VSEL[4:0] LDO4_OK 0 2 LDO6_ON_VSEL[4:0] DC4_OK 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 LDO1_OK DC1_OK 0 0 0 0 0 0 0 0 0 0 0 Bin Default 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0001_0000_0000_0000 U000_0000_0000_0000 0000_0011_1111_1111 0000_0000_0000_0111 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0001_0000_0000 0000_0000_0000_0000 0000_0010_0000_0000 0000_0001_0000_0000 0000_0000_0000_0000 0000_0010_0000_0000 0000_0001_0000_0000 0000_0000_0000_0000 0000_0010_0000_0000 0000_0001_0000_0000 0000_0000_0000_0000 0000_0010_0000_0000 0000_0001_0000_0000 0000_0000_0000_0000 WM8321 Production Data PD, February 2012, Rev 4.0 142 w 780E 780F 7810 7811 30734 30735 30736 30737 7819 781A 781B 781C 781D 781E 781F 30745 30746 30747 30748 30749 30750 30751 7817 7818 30743 7816 30742 30744 7814 7815 30740 30741 7812 780D 30733 7813 780C 30732 30738 780B 30731 30739 780A 30730 7806 30726 7809 7805 30729 7804 30724 30725 7807 7802 7803 30722 30723 7808 7801 30721 30728 7800 30720 30727 Hex Addr Dec Addr 0 OTP_AUTO_ PROG Reserved Customer OTP ID 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP1_DIR 0 GP2_DIR GP3_DIR GP4_DIR GP5_DIR GP6_DIR GPIO2 OTP Control GPIO3 OTP Control GPIO4 OTP Control GPIO5 OTP Control GPIO6 OTP Control LDO11/EPE Control GPIO1 OTP Control LDO11_ON_SLOT[2:0] GP1_POL GP2_POL GP3_POL GP4_POL GP5_POL GP6_POL GP1_INT_M GP1_PWR_ ODE DOM GP2_INT_M GP2_PWR_ ODE DOM GP3_INT_M GP3_PWR_ ODE DOM GP4_INT_M GP4_PWR_ ODE DOM GP5_INT_M GP5_PWR_ ODE DOM GP6_INT_M GP6_PWR_ ODE DOM GP1_PULL[1:0] GP2_PULL[1:0] GP3_PULL[1:0] GP4_PULL[1:0] GP5_PULL[1:0] GP6_PULL[1:0] GP6_OD GP5_OD GP4_OD GP3_OD GP2_OD GP1_OD 0 0 0 0 0 0 0 0 GP6_ENA GP5_ENA GP4_ENA GP3_ENA GP2_ENA GP1_ENA DC3_ON_SLOT[2:0] DC1_ON_SLOT[2:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DC1_CAP[1:0] 0 0 0 0 0 0 0 0 GP6_FN[3:0] GP5_FN[3:0] GP4_FN[3:0] GP3_FN[3:0] GP2_FN[3:0] GP1_FN[3:0] EPE2_ON_SLOT[2:0] LDO9_ON_SLOT[2:0] LDO7_ON_SLOT[2:0] LDO5_ON_SLOT[2:0] LDO3_ON_SLOT[2:0] LDO1_ON_SLOT[2:0] DC2_CAP[1:0] OTP_CUST_ID[13:0] 0 0 0 0 0 0 0 0 DC3_CAP[1:0] 0 0 0 0 0 0 0 0 LDO11_ON_VSEL[3:0] LDO8_ON_VSEL[4:0] LDO10_ON_VSEL[4:0] LDO8_ON_SLOT[2:0] LDO10_ON_SLOT[2:0] LDO6_ON_VSEL[4:0] LDO6_ON_SLOT[2:0] LDO5/6 OTP Control LDO7/8 OTP Control LDO4_ON_VSEL[4:0] LDO9/10 OTP Control LDO2_ON_VSEL[4:0] LDO4_ON_SLOT[2:0] DC4_CAP[1:0] LDO2_ON_SLOT[2:0] DC3_PHAS DC2_PHAS DC1_PHAS E E E LDO3/4 OTP Control DC4_PHASE LDO1/2 OTP Control DC3 OTP Control DC4_ON_VSEL[6:2] 0 Factory OTP 6 0 0 0 0 0 DC4_ON_SLOT[2:0] 0 Factory OTP 5 0 0 0 DC2 OTP Control 0 Factory OTP 4 0 0 0 DC2_ON_VSEL[6:2] 0 Factory OTP 3 0 0 DC2_ON_SLOT[2:0] 0 Factory OTP 2 0 0 DC1 OTP Control 0 Factory OTP 1 0 DC3_ON_VSEL[6:2] DC1_ON_VSEL[6:2] 0 0 0 0 0 0 0 0 0 0 SYSOK_THR[2:0] 0 OTP_CUST _FINAL 0 0 0 0 0 0 0 0 0 0 0 0 0 LED2_SRC[1:0] 0 WDOG_EN A 0 DC4_SLV DC1_FREQ[1:0] 0 0 0 0 0 0 0 0 XTAL_INH CLKOUT_SLOT[2:0] XTAL_ENA LED1_SRC[1:0] 0 0 EPE1_ON_SLOT[2:0] LDO9_ON_VSEL[4:0] LDO7_ON_VSEL[4:0] LDO5_ON_VSEL[4:0] LDO3_ON_VSEL[4:0] LDO1_ON_VSEL[4:0] DC2_FREQ[1:0] 0 0 0 0 0 0 0 0 1010_0100_0000_1010 1010_0100_0000_0000 1010_0100_0000_1111 1010_0100_0000_0000 1010_0100_0000_0001 1010_0100_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0010_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0 UNIQUE_ID[15:0] 0 Unique ID 8 0 0000_0000_0000_0000 Factory OTP ID 0000_0000_0000_0000 UNIQUE_ID[31:16] Bin Default Unique ID 7 0 0000_0000_0000_0000 1 UNIQUE_ID[47:32] 2 UNIQUE_ID[63:48] 3 Unique ID 6 4 Unique ID 5 5 0000_0000_0000_0000 6 0000_0000_0000_0000 7 UNIQUE_ID[79:64] 8 UNIQUE_ID[95:80] 9 Unique ID 3 10 Unique ID 4 11 0000_0000_0000_0000 12 UNIQUE_ID[111:96] 13 Unique ID 2 14 0000_0000_0000_0000 15 UNIQUE_ID[127:112] Nam e Unique ID 1 Production Data WM8321 PD, February 2012, Rev 4.0 143 Hex Addr 7820 7821 7822 7823 7824 7825 7826 7827 Dec Addr 30752 30753 30754 30755 30756 30757 30758 30759 w 0 0 0 0 Reserved Reserved Reserved Reserved ICE CHECK DATA 0 0 0 0 0 0 0 Reserved 0 14 0 0 Reserved 15 Name Reserved 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 11 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 7 ICE_VALID_DATA[15:0] 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Bin Default 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0L0H_H0LL 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 WM8321 Production Data PD, February 2012, Rev 4.0 144 WM8321 Production Data 29 REGISTER BITS BY ADDRESS REGISTER BIT LABEL 15:0 CHIP_ID [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R0 (00h) Reset ID 0000_0000 Writing to this register causes a Software Reset. The _0000_000 register map contents may be reset, depending on SW_RESET_CFG. 0 Reading from this register will indicate Chip ID. Register 00h Reset ID REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO 15:8 PARENT_REV [7:0] 0000_0000 The revision number of the parent die 7:0 CHILD_REV [7:0] 0000_0000 The revision number of the child die (when present) ADDRESS R1 (01h) Revision Register 01h Revision REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16384 (4000h) Parent ID 15:0 PARENT_ID [15:0] 0110_0010 The ID of the parent die _0100_011 0 Register 4000h Parent ID REGISTER BIT LABEL DEFAULT 15:14 SYSLO_ERR_ ACT [1:0] 00 DESCRIPTION REFER TO ADDRESS R16385 (4001h) PVDD Control SYSLO Error Action Selects the action taken when SYSLO is asserted 00 = Interrupt 01 = WAKE transition 10 = Reserved 11 = OFF transition 11 SYSLO_STS 0 SYSLO Status 0 = Normal 1 = PVDD is below SYSLO threshold 6:4 SYSLO_THR [2:0] 010 SYSLO threshold (falling PVDD) This is the falling PVDD voltage at which SYSLO will be asserted 000 = 2.8V 001 = 2.9V … 111 = 3.5V 2:0 SYSOK_THR [2:0] 101 SYSOK threshold (rising PVDD) This is the rising PVDD voltage at which SYSOK will be asserted 000 = 2.8V 001 = 2.9V … 111 = 3.5V Note that the SYSOK hysteresis margin is added to these threshold levels. Register 4001h PVDD Control w PD, February 2012, Rev 4.0 145 WM8321 REGISTER Production Data BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16386 (4002h) Thermal Monitoring 3 THW_HYST 1 Thermal Warning hysteresis 0 = 8 degrees C 1 = 16 degrees C 1:0 THW_TEMP [1:0] 10 Thermal Warning temperature 00 = 90 degrees C 01 = 100 degrees C 10 = 110 degrees C 11 = 120 degrees C Register 4002h Thermal Monitoring REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16387 (4003h) Power State 15 CHIP_ON 0 Indicates whether the system is ON or OFF. 0 = OFF 1 = ON (or SLEEP) OFF can be commanded by writing CHIP_ON = 0. Note that writing CHIP_ON = 1 is not a valid ‘ON’ event, and will not trigger an ON transition. 14 CHIP_SLP 0 Indicates whether the system is in the SLEEP state. 0 = Not in SLEEP 1 = SLEEP WAKE can be commanded by writing CHIP_SLP = 0. SLEEP can be commanded by writing CHIP_SLP = 1. 12 REF_LP 0 Low Power Voltage Reference Control 0 = Normal 1 = Low Power Reference Mode select Note that Low Power Reference Mode is only supported when the Auxiliary ADC is disabled. 11:10 PWRSTATE_D LY [1:0] 10 Power State transition delay 00 = No delay 01 = No delay 10 = 1ms 11 = 10ms 9 SWRST_DLY 0 Software Reset Delay 0 = No delay 1 = Software Reset is delayed by PWRSTATE_DLY following the Software Reset command Register 4003h Power State REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16388 (4004h) Watchdog 15 WDOG_ENA 1 Watchdog Timer Enable 0 = Disabled 1 = Enabled (enables the watchdog; does not reset it) Protected by security key. 14 WDOG_DEBU G 0 Watchdog Pause 0 = Disabled 1 = Enabled (halts the Watchdog timer for system debugging) w PD, February 2012, Rev 4.0 146 WM8321 Production Data REGISTER BIT LABEL DEFAULT 13 WDOG_RST_S RC 1 DESCRIPTION REFER TO ADDRESS Protected by security key. Watchdog Reset Source 0 = Hardware only 1 = Software only Protected by security key. 12 WDOG_SLPE NA 0 Watchdog SLEEP Enable 0 = Disabled 1 = Controlled by WDOG_ENA Protected by security key. 11 WDOG_RESE T 0 Watchdog Software Reset 0 = Normal 1 = Watchdog Reset (resets the watchdog, if WDOG_RST_SRC = 1) 9:8 WDOG_SECA CT [1:0] 10 Secondary action of Watchdog timeout (taken after 2 timeout periods) 00 = No action 01 = Interrupt 10 = Device Reset 11 = WAKE transition Protected by security key. 5:4 WDOG_PRIMA CT [1:0] 01 Primary action of Watchdog timeout 00 = No action 01 = Interrupt 10 = Device Reset 11 = WAKE transition Protected by security key. 2:0 WDOG_TO [2:0] 111 Watchdog timeout period 000 = 0.256s 001 = 0.512s 010 = 1.024s 011 = 2.048s 100 = 4.096s 101 = 8.192s 110 = 16.384s 111 = 32.768s Protected by security key. Register 4004h Watchdog REGISTER BIT LABEL DEFAULT 9:8 ON_PIN_SECA CT [1:0] 01 DESCRIPTION REFER TO ADDRESS R16389 (4005h) ON Pin Control Secondary action of ON pin (taken after 1 timeout period) 00 = Interrupt 01 = ON request 10 = OFF request 11 = Reserved Protected by security key. 5:4 ON_PIN_PRIM ACT [1:0] 00 Primary action of ON pin 00 = Ignore 01 = ON request 10 = OFF request 11 = Reserved w PD, February 2012, Rev 4.0 147 WM8321 REGISTER Production Data BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS Note that an Interrupt is always raised. Protected by security key. 3 ON_PIN_STS 0 Current status of ON pin 0 = Asserted (logic 0) 1 = Not asserted (logic 1) 1:0 ON_PIN_TO [1:0] 00 ON pin timeout period 00 = 1s 01 = 2s 10 = 4s 11 = 8s Protected by security key. Register 4005h ON Pin Control REGISTER BIT LABEL DEFAULT 15 RECONFIG_A T_ON 1 DESCRIPTION REFER TO ADDRESS R16390 (4006h) Reset Control Selects if the bootstrap configuration data should be reloaded when an ON transition is scheduled 0 = Disabled 1 = Enabled Protected by security key. 10 SW_RESET_C FG 1 Software Reset Configuration. Selects whether the register map is reset to default values when Software Reset occurs. 0 = All registers except VPMIC domain and RTC are reset by Software Reset 1 = Register Map is not affected by Software Reset Protected by security key. 6 AUXRST_SLP ENA 1 Sets the output status of Auxiliary Reset (GPIO) function in SLEEP 0 = Auxiliary Reset not asserted 1 = Auxiliary Reset asserted Protected by security key. 5 RST_SLP_MS K 1 Masks the RESET pin input in SLEEP mode 0 = External RESET active in SLEEP 1 = External RESET masked in SLEEP Protected by security key. 4 RST_SLPENA 1 Sets the output status of RESET pin in SLEEP 0 = RESET high (not asserted) 1 = RESET low (asserted) Protected by security key. 1:0 RST_DUR [1:0] 11 Delay period for releasing RESET after ON or WAKE sequence 00 = 3ms 01 = 11ms 10 = 51ms 11 = 101ms Protected by security key. Register 4006h Reset Control w PD, February 2012, Rev 4.0 148 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16391 (4007h) Control Interface 2 AUTOINC 1 Enable Auto-Increment function 0 = Disabled 1 = Enabled Register 4007h Control Interface REGISTER BIT LABEL 15:0 SECURITY [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R16392 (4008h) Security Key 0000_0000 Security Key _0000_000 A value of 9716h must be written to this register to 0 access the user-keyed registers. Register 4008h Security Key REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16393 (4009h) Software Scratch 15:0 SW_SCRATCH 0000_0000 Software Scratch Register for use by the host [15:0] _0000_000 processor. 0 Note that this register’s contents are retained in the BACKUP power state. Register 4009h Software Scratch REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16394 (400Ah) OTP Control 15 OTP_PROG 0 Selects the PROGRAM device state. 0 = No action 1 = Select PROGRAM mode Note that, after PROGRAM mode has been selected, the chip will remain in PROGRAM mode until a Device Reset. Protected by security key. 13 OTP_MEM 1 Selects ICE or OTP memory for Program commands. 0 = ICE 1 = OTP Protected by security key. 11 OTP_FINAL 0 Selects the FINALISE command, preventing further OTP programming. 0 = No action 1 = Finalise Command Protected by security key. 10 OTP_VERIFY 0 Selects the VERIFY command for the selected OTP memory page(s). 0 = No action 1 = Verify Command Protected by security key. 9 OTP_WRITE 0 Selects WRITE command for the selected OTP memory page(s). 0 = No action 1 = Write Command Protected by security key. w PD, February 2012, Rev 4.0 149 WM8321 REGISTER Production Data BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 8 OTP_READ 0 Selects READ command for the selected memory page(s). 0 = No action 1 = Read Command Protected by security key. 7:6 OTP_READ_L VL [1:0] 00 Selects the Margin Level for READ or VERIFY OTP commands. 00 = Normal 01 = Reserved 10 = Margin 1 11 = Margin 2 Protected by security key. 5 OTP_BULK 0 Selects the number of memory pages for ICE / OTP commands. 0 = Single Page 1 = All Pages 1:0 OTP_PAGE [1:0] 00 Selects the single memory page for ICE / OTP commands (when OTP_BULK=0). If OTP is selected (OTP_MEM = 1): 00 = Page 0 01 = Page 1 10 = Page 2 11 = Page 3 If ICE is selected (OTP_MEM = 0): 00 = Page 2 01 = Page 3 10 = Page 4 11 = Reserved Register 400Ah OTP Control REGISTER BIT LABEL 11 GP12_LVL DEFAULT DESCRIPTION REFER TO ADDRESS R16396 (400Ch) GPIO Level 0 GPIO12 level. When GP12_FN = 0h and GP12_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP12_POL is 0, the register contains the opposite logic level to the external pin. 10 GP11_LVL 0 GPIO11 level. When GP11_FN = 0h and GP11_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP11_POL is 0, the register contains the opposite logic level to the external pin. 9 GP10_LVL 0 GPIO10 level. When GP10_FN = 0h and GP10_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP10_POL is 0, the register contains the opposite logic level to the external pin. w PD, February 2012, Rev 4.0 150 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 8 GP9_LVL 0 GPIO9 level. When GP9_FN = 0h and GP9_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP9_POL is 0, the register contains the opposite logic level to the external pin. 7 GP8_LVL 0 GPIO8 level. When GP8_FN = 0h and GP8_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP8_POL is 0, the register contains the opposite logic level to the external pin. 6 GP7_LVL 0 GPIO7 level. When GP7_FN = 0h and GP7_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP7_POL is 0, the register contains the opposite logic level to the external pin. 5 GP6_LVL 0 GPIO6 level. When GP6_FN = 0h and GP6_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP6_POL is 0, the register contains the opposite logic level to the external pin. 4 GP5_LVL 0 GPIO5 level. When GP5_FN = 0h and GP5_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP5_POL is 0, the register contains the opposite logic level to the external pin. 3 GP4_LVL 0 GPIO4 level. When GP4_FN = 0h and GP4_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP4_POL is 0, the register contains the opposite logic level to the external pin. 2 GP3_LVL 0 GPIO3 level. When GP3_FN = 0h and GP3_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP3_POL is 0, the register contains the opposite logic level to the external pin. 1 GP2_LVL 0 GPIO2 level. When GP2_FN = 0h and GP2_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP2_POL is 0, the register contains the opposite logic level to the external pin. 0 GP1_LVL 0 GPIO1 level. When GP1_FN = 0h and GP1_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP1_POL is 0, the register contains the opposite logic level to the external pin. Register 400Ch GPIO Level w PD, February 2012, Rev 4.0 151 WM8321 REGISTER Production Data BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16397 (400Dh) System Status 15 THW_STS 0 Thermal Warning status 0 = Normal 1 = Overtemperature Warning (warning temperature is set by THW_TEMP) 7 XTAL_OK 0 Crystal Oscillator Status 0 = Disabled or in start-up phase 1 = Enabled and verified 4:0 MAIN_STATE [4:0] 0_0000 Main State Machine condition 0_0000 = OFF 0_0001 = ON_CHK 0_0010 = OTP_DN 0_0011 = READ_OTP 0_0100 = READ_ICE 0_0101 = ICE_DN 0_0110 = BGDELAY 0_0111 = HYST 0_1000 = S_PRG_RD_OTP 0_1001 = S_PRG_OTP_DN 0_1010 = PWRDN1 0_1011 = PROGRAM 0_1100 = PROG_DN 0_1101 = PROG_OTP 0_1110 = VFY_OTP 0_1111 = VFY_DN 1_0000 = SD_RD_OTP 1_0001 = UNUSED 1_0010 = ICE_FAIL 1_0011 = SHUTDOWN 1_0100 = STARTFAIL 1_0101 = STARTUP 1_0110 = PREACTIVE 1_0111 = XTAL_CHK 1_1000 = PWRDN2 1_1001 = SHUT_DLY 1_1010 = RESET 1_1011 = RESET_DLY 1_1100 = SLEEP 1_1101 = SLEEP_DLY 1_1110 = CHK_RST 1_1111 = ACTIVE (ON) Register 400Dh System Status w PD, February 2012, Rev 4.0 152 WM8321 Production Data REGISTER BIT LABEL 15 ON_TRANS DEFAULT DESCRIPTION REFER TO ADDRESS R16398 (400Eh) ON Source 0 Most recent ON/WAKE event type 0 = WAKE transition 1 = ON transition Reset by state machine. 11 ON_GPIO 0 Most recent ON/WAKE event type 0 = Not caused by GPIO input 1 = Caused by GPIO input Reset by state machine. 10 ON_SYSLO 0 Most recent WAKE event type 0 = Not caused by PVDD 1 = Caused by SYSLO threshold. Note that the SYSLO threshold cannot trigger an ON event. Reset by state machine. 7 ON_WDOG_T O 0 Most recent WAKE event type 0 = Not caused by Watchdog timer 1 = Caused by Watchdog timer Reset by state machine. 6 ON_SW_REQ 0 Most recent WAKE event type 0 = Not caused by software WAKE 1 = Caused by software WAKE command (CHIP_SLP = 0) Reset by state machine. 5 ON_RTC_ALM 0 Most recent ON/WAKE event type 0 = Not caused by RTC Alarm 1 = Caused by RTC Alarm Reset by state machine. 4 ON_ON_PIN 0 Most recent ON/WAKE event type 0 = Not caused by the ON pin 1 = Caused by the ON pin Reset by state machine. 3 RESET_CNV_ UV 0 Most recent ON event type 0 = Not caused by undervoltage 1 = Caused by a Device Reset due to a Converter (LDO or DC-DC) undervoltage condition Reset by state machine. 2 RESET_SW 0 Most recent ON event type 0 = Not caused by Software Reset 1 = Caused by Software Reset Reset by state machine. 1 RESET_HW 0 Most recent ON event type 0 = Not caused by Hardware Reset 1 = Caused by Hardware Reset Reset by state machine. 0 RESET_WDO G 0 Most recent ON event type 0 = Not caused by the Watchdog 1 = Caused by a Device Reset triggered by the Watchdog timer Reset by state machine. Register 400Eh ON Source w PD, February 2012, Rev 4.0 153 WM8321 REGISTER Production Data BIT LABEL DEFAULT 13 OFF_INTLDO_ ERR 0 DESCRIPTION REFER TO ADDRESS R16399 (400Fh) OFF Source Most recent OFF event type 0 = Not caused by LDO13 Error condition 1 = Caused by LDO13 Error condition Reset by state machine. 12 OFF_PWR_SE Q 0 Most recent OFF event type 0 = Not caused by Power Sequence Failure 1 = Caused by a Power Sequence Failure Reset by state machine. 11 OFF_GPIO 0 Most recent OFF event type 0 = Not caused by GPIO input 1 = Caused by GPIO input Reset by state machine. 10 OFF_PVDD 0 Most recent OFF event type 0 = Not caused by PVDD 1 = Caused by the SYSLO or SHUTDOWN threshold Reset by state machine. 9 OFF_THERR 0 Most recent OFF event type 0 = Not caused by temperature 1 = Caused by over-temperature Reset by state machine. 6 OFF_SW_REQ 0 Most recent OFF event type 0 = Not caused by software OFF 1 = Caused by software OFF command (CHIP_ON = 0) Reset by state machine. 4 OFF_ON_PIN 0 Most recent OFF event type 0 = Not caused by the ON pin 1 = Caused by the ON pin Reset by state machine. Register 400Fh OFF Source REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16400 (4010h) System Interrupts 15 PS_INT 0 Power State primary interrupt 0 = No interrupt 1 = Interrupt is asserted 14 TEMP_INT 0 Thermal primary interrupt 0 = No interrupt 1 = Interrupt is asserted 13 GP_INT 0 GPIO primary interrupt 0 = No interrupt 1 = Interrupt is asserted 12 ON_PIN_INT 0 ON Pin primary interrupt 0 = No interrupt 1 = Interrupt is asserted 11 WDOG_INT 0 Watchdog primary interrupt 0 = No interrupt 1 = Interrupt is asserted 8 AUXADC_INT 0 AUXADC primary interrupt 0 = No interrupt 1 = Interrupt is asserted 7 PPM_INT w 0 Power Path Management primary interrupt PD, February 2012, Rev 4.0 154 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 0 = No interrupt 1 = Interrupt is asserted 5 RTC_INT 0 Real Time Clock and Crystal Oscillator primary interrupt 0 = No interrupt 1 = Interrupt is asserted 4 OTP_INT 0 OTP Memory primary interrupt 0 = No interrupt 1 = Interrupt is asserted 1 HC_INT 0 High Current primary interrupt 0 = No interrupt 1 = Interrupt is asserted 0 UV_INT 0 Undervoltage primary interrupt 0 = No interrupt 1 = Interrupt is asserted Register 4010h System Interrupts REGISTER BIT LABEL DEFAULT 15 PPM_SYSLO_ EINT 0 ON_PIN_CINT 0 DESCRIPTION REFER TO ADDRESS R16401 (4011h) Interrupt Status 1 Power Path SYSLO interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 12 ON pin interrupt. (Rising and Falling Edge triggered) Note: Cleared when a ‘1’ is written. 11 WDOG_TO_EI NT 0 AUXADC_DAT A_EINT 0 AUXADC_DCO MP4_EINT 0 AUXADC_DCO MP3_EINT 0 AUXADC_DCO MP2_EINT 0 AUXADC_DCO MP1_EINT 0 RTC_PER_EIN T 0 RTC_ALM_EIN T 0 Watchdog timeout interrupt. (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 8 AUXADC Data Ready interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 7 AUXADC Digital Comparator 4 interrupt (Trigger is controlled by DCMP4_GT) Note: Cleared when a ‘1’ is written. 6 AUXADC Digital Comparator 3 interrupt (Trigger is controlled by DCMP3_GT) Note: Cleared when a ‘1’ is written. 5 AUXADC Digital Comparator 2 interrupt (Trigger is controlled by DCMP2_GT) Note: Cleared when a ‘1’ is written. 4 AUXADC Digital Comparator 1 interrupt (Trigger is controlled by DCMP1_GT) Note: Cleared when a ‘1’ is written. 3 RTC Periodic interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 2 RTC Alarm interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. w PD, February 2012, Rev 4.0 155 WM8321 REGISTER Production Data BIT LABEL DEFAULT 1 TEMP_THW_C INT 0 DESCRIPTION REFER TO ADDRESS Thermal Warning interrupt (Rising and Falling Edge triggered) Note: Cleared when a ‘1’ is written. Register 4011h Interrupt Status 1 REGISTER BIT LABEL DEFAULT 5 OTP_CMD_EN D_EINT 0 OTP_ERR_EIN T 0 PS_POR_EINT 0 DESCRIPTION REFER TO ADDRESS R16402 (4012h) Interrupt Status 2 OTP / ICE Command End interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 4 OTP / ICE Command Fail interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 2 Power On Reset interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 1 PS_SLEEP_O FF_EINT 0 SLEEP or OFF interrupt (Power state transition to SLEEP or OFF states) (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 0 PS_ON_WAKE _EINT 0 ON or WAKE interrupt (Power state transition to ON state) (Rising Edge triggered) Note: Cleared when a ‘1’ is written. Register 4012h Interrupt Status 2 REGISTER BIT LABEL DEFAULT 9 UV_LDO10_EI NT 0 DESCRIPTION REFER TO ADDRESS R16403 (4013h) Interrupt Status 3 LDO10 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 8 UV_LDO9_EIN T 0 UV_LDO8_EIN T 0 UV_LDO7_EIN T 0 UV_LDO6_EIN T 0 UV_LDO5_EIN T 0 UV_LDO4_EIN T 0 LDO9 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 7 LDO8 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 6 LDO7 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 5 LDO6 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 4 LDO5 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 3 LDO4 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. w PD, February 2012, Rev 4.0 156 WM8321 Production Data REGISTER BIT LABEL DEFAULT 2 UV_LDO3_EIN T 0 UV_LDO2_EIN T 0 UV_LDO1_EIN T 0 DESCRIPTION REFER TO ADDRESS LDO3 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 1 LDO2 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 0 LDO1 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. Register 4013h Interrupt Status 3 REGISTER BIT LABEL DEFAULT 9 HC_DC2_EINT 0 DESCRIPTION REFER TO ADDRESS R16404 (4014h) Interrupt Status 4 DC-DC2 High current interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 8 HC_DC1_EINT 0 DC-DC1 High current interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 7 XTAL_START_ EINT 0 XTAL_TAMPE R_EINT 0 UV_DC4_EINT 0 Crystal Oscillator Start Failure interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 6 Crystal Oscillator Tamper interrupt (Rising and Falling Edge triggered) Note: Cleared when a ‘1’ is written. 3 DC-DC4 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 2 UV_DC3_EINT 0 DC-DC3 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 1 UV_DC2_EINT 0 DC-DC2 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 0 UV_DC1_EINT 0 DC-DC1 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. Register 4014h Interrupt Status 4 REGISTER BIT LABEL 11 GP12_EINT DEFAULT DESCRIPTION REFER TO ADDRESS R16405 (4015h) Interrupt Status 5 0 GPIO12 interrupt. (Trigger is controlled by GP12_INT_MODE) Note: Cleared when a ‘1’ is written. 10 GP11_EINT 0 GPIO11 interrupt. (Trigger is controlled by GP11_INT_MODE) Note: Cleared when a ‘1’ is written. 9 GP10_EINT 0 GPIO10 interrupt. (Trigger is controlled by GP10_INT_MODE) Note: Cleared when a ‘1’ is written. w PD, February 2012, Rev 4.0 157 WM8321 REGISTER Production Data BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 8 GP9_EINT 0 GPIO9 interrupt. (Trigger is controlled by GP9_INT_MODE) Note: Cleared when a ‘1’ is written. 7 GP8_EINT 0 GPIO8 interrupt. (Trigger is controlled by GP8_INT_MODE) Note: Cleared when a ‘1’ is written. 6 GP7_EINT 0 GPIO7 interrupt. (Trigger is controlled by GP7_INT_MODE) Note: Cleared when a ‘1’ is written. 5 GP6_EINT 0 GPIO6 interrupt. (Trigger is controlled by GP6_INT_MODE) Note: Cleared when a ‘1’ is written. 4 GP5_EINT 0 GPIO5 interrupt. (Trigger is controlled by GP5_INT_MODE) Note: Cleared when a ‘1’ is written. 3 GP4_EINT 0 GPIO4 interrupt. (Trigger is controlled by GP4_INT_MODE) Note: Cleared when a ‘1’ is written. 2 GP3_EINT 0 GPIO3 interrupt. (Trigger is controlled by GP3_INT_MODE) Note: Cleared when a ‘1’ is written. 1 GP2_EINT 0 GPIO2 interrupt. (Trigger is controlled by GP2_INT_MODE) Note: Cleared when a ‘1’ is written. 0 GP1_EINT 0 GPIO1 interrupt. (Trigger is controlled by GP1_INT_MODE) Note: Cleared when a ‘1’ is written. Register 4015h Interrupt Status 5 REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16407 (4017h) IRQ Config 1 IRQ_OD 1 IRQ pin configuration 0 = CMOS 1 = Open Drain (integrated pull-up) 0 IM_IRQ 0 IRQ pin output mask 0 = Normal 1 = IRQ output is masked Register 4017h IRQ Config REGISTER BIT LABEL 15 IM_PS_INT DEFAULT DESCRIPTION REFER TO ADDRESS R16408 (4018h) System Interrupts Mask 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 14 IM_TEMP_INT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) w PD, February 2012, Rev 4.0 158 WM8321 Production Data REGISTER BIT LABEL 13 IM_GP_INT DEFAULT DESCRIPTION REFER TO ADDRESS 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 12 IM_ON_PIN_IN T 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 11 IM_WDOG_INT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 8 IM_AUXADC_I NT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 7 IM_PPM_INT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 5 IM_RTC_INT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 4 IM_OTP_INT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 1 IM_HC_INT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 0 IM_UV_INT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Register 4018h System Interrupts Mask REGISTER BIT LABEL DEFAULT 15 IM_PPM_SYSL O_EINT 1 DESCRIPTION REFER TO ADDRESS R16409 (4019h) Interrupt Status 1 Mask Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 12 IM_ON_PIN_CI NT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 11 IM_WDOG_TO _EINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) w PD, February 2012, Rev 4.0 159 WM8321 REGISTER Production Data BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 8 IM_AUXADC_ DATA_EINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 7 IM_AUXADC_ DCOMP4_EIN T 1 IM_AUXADC_ DCOMP3_EIN T 1 IM_AUXADC_ DCOMP2_EIN T 1 IM_AUXADC_ DCOMP1_EIN T 1 IM_RTC_PER_ EINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 6 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 5 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 4 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 3 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 2 IM_RTC_ALM_ EINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 1 IM_TEMP_TH W_CINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Register 4019h Interrupt Status 1 Mask REGISTER BIT LABEL DEFAULT 5 IM_OTP_CMD _END_EINT 1 DESCRIPTION REFER TO ADDRESS R16410 (401Ah) Interrupt Status 2 Mask Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 4 IM_OTP_ERR_ EINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 2 IM_PS_POR_E INT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 1 IM_PS_SLEEP _OFF_EINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. w PD, February 2012, Rev 4.0 160 WM8321 Production Data REGISTER BIT LABEL DEFAULT 0 IM_PS_ON_W AKE_EINT 1 DESCRIPTION REFER TO ADDRESS Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Register 401Ah Interrupt Status 2 Mask REGISTER BIT LABEL DEFAULT 9 IM_UV_LDO10 _EINT 1 DESCRIPTION REFER TO ADDRESS R16411 (401Bh) Interrupt Status 3 Mask Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 8 IM_UV_LDO9_ EINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 7 IM_UV_LDO8_ EINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 6 IM_UV_LDO7_ EINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 5 IM_UV_LDO6_ EINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 4 IM_UV_LDO5_ EINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 3 IM_UV_LDO4_ EINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 2 IM_UV_LDO3_ EINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 1 IM_UV_LDO2_ EINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 0 IM_UV_LDO1_ EINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Register 401Bh Interrupt Status 3 Mask w PD, February 2012, Rev 4.0 161 WM8321 REGISTER Production Data BIT LABEL DEFAULT 9 IM_HC_DC2_E INT 1 DESCRIPTION REFER TO ADDRESS R16412 (401Ch) Interrupt Status 4 Mask Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 8 IM_HC_DC1_E INT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 7 IM_XTAL_STA RT_EINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 3 IM_UV_DC4_E INT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 2 IM_UV_DC3_E INT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 1 IM_UV_DC2_E INT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 0 IM_UV_DC1_E INT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Register 401Ch Interrupt Status 4 Mask REGISTER BIT LABEL DEFAULT 11 IM_GP12_EIN T 1 DESCRIPTION REFER TO ADDRESS R16413 (401Dh) Interrupt Status 5 Mask Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 10 IM_GP11_EIN T 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 9 IM_GP10_EIN T 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 8 IM_GP9_EINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) w PD, February 2012, Rev 4.0 162 WM8321 Production Data REGISTER BIT LABEL DEFAULT 7 IM_GP8_EINT 1 DESCRIPTION REFER TO ADDRESS Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 6 IM_GP7_EINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 5 IM_GP6_EINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 4 IM_GP5_EINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 3 IM_GP4_EINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 2 IM_GP3_EINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 1 IM_GP2_EINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 0 IM_GP1_EINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Register 401Dh Interrupt Status 5 Mask REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16416 (4020h) RTC Write Counter 15:0 RTC_WR_CNT 0000_0000 RTC Write Counter. [15:0] _0000_000 This random number is updated on every write to the 0 RTC_TIME registers. Register 4020h RTC Write Counter REGISTER BIT LABEL 15:0 RTC_TIME [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R16417 (4021h) RTC Time 1 0000_0000 RTC Seconds counter (MSW) _0000_000 RTC_TIME increments by 1 every second. This is the 0 16 MSBs. Register 4021h RTC Time 1 w PD, February 2012, Rev 4.0 163 WM8321 REGISTER Production Data BIT LABEL 15:0 RTC_TIME [15:0] DEFAULT DESCRIPTION REFER TO ADDRESS R16418 (4022h) RTC Time 2 0000_0000 RTC Seconds counter (LSW) _0000_000 RTC_TIME increments by 1 every second. This is the 0 16 LSBs. Register 4022h RTC Time 2 REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16419 (4023h) RTC Alarm 1 15:0 RTC_ALM [15:0] 0000_0000 RTC Alarm time (MSW) _0000_000 16 MSBs of RTC_ALM 0 Register 4023h RTC Alarm 1 REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16420 (4024h) RTC Alarm 2 15:0 RTC_ALM [15:0] 0000_0000 RTC Alarm time (LSW) _0000_000 16 LSBs of RTC_ALM 0 Register 4024h RTC Alarm 2 REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16421 (4025h) RTC Control 15 RTC_VALID 0 RTC Valid status 0 = RTC_TIME has not been set since Power On Reset 1 = RTC_TIME has been written to since Power On Reset 14 RTC_SYNC_B USY 0 RTC Busy status 0 = Normal 1 = Busy The RTC registers should not be written to when RTC_SYNC_BUSY = 1. 10 RTC_ALM_EN A 0 RTC_PINT_FR EQ [2:0] 000 RTC Alarm Enable 0 = Disabled 1 = Enabled 6:4 RTC Periodic Interrupt timeout period 000 = Disabled 001 = 2s 010 = 4s 011 = 8s 100 = 16s 101 = 32s 110 = 64s 111 = 128s Register 4025h RTC Control w PD, February 2012, Rev 4.0 164 WM8321 Production Data REGISTER BIT LABEL 9:0 RTC_TRIM [9:0] DEFAULT DESCRIPTION REFER TO ADDRESS R16422 (4026h) RTC Trim 00_0000_0 RTC frequency trim. Value is a 10bit fixed point <4,6> 2's complement number. MSB Scaling = -8Hz. 000 The register indicates the error (in Hz) with respect to the ideal 32768Hz) of the input crystal frequency. Protected by security key. Register 4026h RTC Trim REGISTER BIT LABEL DEFAULT 15:12 AUX_DATA_S RC [3:0] 0000 DESCRIPTION REFER TO ADDRESS R16429 (402Dh) AuxADC Data AUXADC Data Source 1 = GPIO10 2 = GPIO11 3 = GPIO12 5 = Chip Temperature 7 = PVDD voltage All other values are Reserved 11:0 AUX_DATA [11:0] 0000_0000 AUXADC Measurement Data _0000 Voltage (mV) = AUX_DATA x 1.465 ChipTemp (°C) = (498 - AUX_DATA) / 1.09 Register 402Dh AuxADC Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16430 (402Eh) AuxADC Control 15 AUX_ENA 0 AUXADC Enable 0 = Disabled 1 = Enabled Note - this bit is reset to 0 when the OFF power state is entered. 14 AUX_CVT_EN A 0 AUXADC Conversion Enable 0 = Disabled 1 = Enabled In automatic mode, conversions are enabled by setting this bit. In manual mode (AUX_RATE = 0), setting this bit will initiate a conversion; the bit is reset automatically after each conversion. 12 AUX_SLPENA 0 AUXADC SLEEP Enable 0 = Disabled 1 = Controlled by AUX_ENA 5:0 AUX_RATE [5:0] 00_0000 AUXADC Conversion Rate 0 = Manual 1 = 2 samples/s 2 = 4 samples/s 3 = 6 samples/s … 31 = 62 samples/s 32 = Reserved 33 = 16 samples/s 34 = 32 samples/s 35 = 48 samples/s … 63 = 496 samples/s Register 402Eh AuxADC Control w PD, February 2012, Rev 4.0 165 WM8321 REGISTER Production Data BIT LABEL DEFAULT 6 AUX_PVDD_S EL 0 AUX_CHIP_TE MP_SEL 0 AUX_GPIO12_ SEL 0 AUX_GPIO11_ SEL 0 AUX_GPIO10_ SEL 0 DESCRIPTION REFER TO ADDRESS R16431 (402Fh) AuxADC Source AUXADC PVDD input select 0 = Disable PVDD measurement 1 = Enable PVDD measurement 4 AUXADC Chip Temp input select 0 = Disable Chip Temp measurement 1 = Enable Chip Temp measurement 2 AUXADC GPIO12 input select 0 = Disable GPIO12 measurement 1 = Enable GPIO12 measurement 1 AUXADC GPIO11 input select 0 = Disable GPIO11 measurement 1 = Enable GPIO11 measurement 0 AUXADC GPIO10 input select 0 = Disable GPIO10 measurement 1 = Enable GPIO10 measurement Register 402Fh AuxADC Source REGISTER BIT LABEL DEFAULT 11 DCOMP4_STS 0 DESCRIPTION REFER TO ADDRESS R16432 (4030h) Comparator Control Digital Comparator 4 status 0 = Comparator 4 threshold not detected 1 = Comparator 4 threshold detected (Trigger is controlled by DCMP4_GT) 10 DCOMP3_STS 0 Digital Comparator 3 status 0 = Comparator 3 threshold not detected 1 = Comparator 3 threshold detected (Trigger is controlled by DCMP3_GT) 9 DCOMP2_STS 0 Digital Comparator 2 status 0 = Comparator 2 threshold not detected 1 = Comparator 2 threshold detected (Trigger is controlled by DCMP2_GT) 8 DCOMP1_STS 0 Digital Comparator 1 status 0 = Comparator 1 threshold not detected 1 = Comparator 1 threshold detected (Trigger is controlled by DCMP1_GT) 3 DCMP4_ENA 0 Digital Comparator 4 Enable 0 = Disabled 1 = Enabled 2 DCMP3_ENA 0 Digital Comparator 3 Enable 0 = Disabled 1 = Enabled 1 DCMP2_ENA 0 Digital Comparator 2 Enable 0 = Disabled 1 = Enabled 0 DCMP1_ENA 0 Digital Comparator 1 Enable 0 = Disabled 1 = Enabled Register 4030h Comparator Control w PD, February 2012, Rev 4.0 166 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16433 (4031h) Comparator 1 15:13 DCMP1_SRC [2:0] 000 Digital Comparator 1 source select 0 = Reserved 1 = GPIO10 2 = GPIO11 3 = GPIO12 4 = Reserved 5 = Chip Temperature 6 = Reserved 7 = PVDD voltage 12 DCMP1_GT 0 Digital Comparator 1 interrupt control 0 = interrupt when less than threshold 1 = interrupt when greater than or equal to threshold 11:0 DCMP1_THR [11:0] 0000_0000 Digital Comparator 1 threshold _0000 (12-bit unsigned binary number; coding is the same as AUX_DATA) Register 4031h Comparator 1 REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16434 (4032h) Comparator 2 15:13 12 DCMP2_SRC [2:0] DCMP2_GT 000 0 Digital Comparator 2 source select 0 = Reserved 1 = GPIO10 2 = GPIO11 3 = GPIO12 4 = Reserved 5 = Chip Temperature 6 = Reserved 7 = PVDD voltage Digital Comparator 2 interrupt control 0 = interrupt when less than threshold 1 = interrupt when greater than or equal to threshold 11:0 DCMP2_THR [11:0] 0000_0000 Digital Comparator 2 threshold _0000 (12-bit unsigned binary number; coding is the same as AUX_DATA) Register 4032h Comparator 2 REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16435 (4033h) Comparator 3 15:13 12 DCMP3_SRC [2:0] DCMP3_GT 000 0 Digital Comparator 3 source select 0 = Reserved 1 = GPIO10 2 = GPIO11 3 = GPIO12 4 = Reserved 5 = Chip Temperature 6 = Reserved 7 = PVDD voltage Digital Comparator 3 interrupt control 0 = interrupt when less than threshold 1 = interrupt when greater than or equal to threshold w PD, February 2012, Rev 4.0 167 WM8321 REGISTER Production Data BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 11:0 DCMP3_THR [11:0] 0000_0000 Digital Comparator 3 threshold _0000 (12-bit unsigned binary number; coding is the same as AUX_DATA) Register 4033h Comparator 3 REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16436 (4034h) Comparator 4 15:13 12 DCMP4_SRC [2:0] DCMP4_GT 000 Digital Comparator 4 source select 0 = Backup Battery voltage 1 = GPIO10 2 = GPIO11 3 = GPIO12 4 = Reserved 5 = Chip Temperature 6 = Reserved 7 = PVDD voltage 0 Digital Comparator 4 interrupt control 0 = interrupt when less than threshold 1 = interrupt when greater than or equal to threshold 11:0 DCMP4_THR [11:0] 0000_0000 Digital Comparator 4 threshold _0000 (12-bit unsigned binary number; coding is the same as AUX_DATA) Register 4034h Comparator 4 REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16440 (4038h) GPIO1 Control 15 GP1_DIR 1 GPIO1 pin direction 0 = Output 1 = Input 14:13 GP1_PULL [1:0] 01 GPIO1 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved 12 GP1_INT_MOD E 0 GPIO1 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP1_POL=1) or falling edge triggered (if GP1_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges 11 GP1_PWR_DO M 0 GP1_POL 1 GPIO1 Power Domain select 0 = DBVDD 1 = PMICVDD (LDO12) 10 GPIO1 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) 9 GP1_OD 0 GPIO1 Output pin configuration 0 = CMOS 1 = Open Drain 7 GP1_ENA 0 GPIO1 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation w PD, February 2012, Rev 4.0 168 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 3:0 GP1_FN [3:0] 0000 GPIO1 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Reserved 7 = Reserved 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 4038h GPIO1 Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16441 (4039h) GPIO2 Control 15 GP2_DIR 1 GPIO2 pin direction 0 = Output 1 = Input 14:13 GP2_PULL [1:0] 01 GPIO2 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved 12 GP2_INT_MOD E 0 GPIO2 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP2_POL=1) or falling edge triggered (if GP2_POL=0) 1 = GPIO interrupt is triggered on rising and falling w PD, February 2012, Rev 4.0 169 WM8321 REGISTER Production Data BIT LABEL DEFAULT 11 GP2_PWR_DO M 0 GP2_POL 1 DESCRIPTION REFER TO ADDRESS edges GPIO2 Power Domain select 0 = DBVDD 1 = PMICVDD (LDO12) 10 GPIO2 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) 9 GP2_OD 0 GPIO2 Output pin configuration 0 = CMOS 1 = Open Drain 7 GP2_ENA 0 GPIO2 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation 3:0 GP2_FN [3:0] 0000 GPIO2 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Reserved 7 = Reserved 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 4039h GPIO2 Control w PD, February 2012, Rev 4.0 170 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16442 (403Ah) GPIO3 Control 15 GP3_DIR 1 GPIO3 pin direction 0 = Output 1 = Input 14:13 GP3_PULL [1:0] 01 GPIO3 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved 12 GP3_INT_MOD E 0 GPIO3 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP3_POL=1) or falling edge triggered (if GP3_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges 11 GP3_PWR_DO M 0 GP3_POL 1 GPIO3 Power Domain select 0 = DBVDD 1 = PMICVDD (LDO12) 10 GPIO3 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) 9 GP3_OD 0 GPIO3 Output pin configuration 0 = CMOS 1 = Open Drain 7 GP3_ENA 0 GPIO3 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation 3:0 GP3_FN [3:0] 0000 GPIO3 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Reserved 7 = Reserved w PD, February 2012, Rev 4.0 171 WM8321 REGISTER Production Data BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 403Ah GPIO3 Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16443 (403Bh) GPIO4 Control 15 GP4_DIR 1 GPIO4 pin direction 0 = Output 1 = Input 14:13 GP4_PULL [1:0] 01 GPIO4 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved 12 GP4_INT_MOD E 0 GPIO4 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP4_POL=1) or falling edge triggered (if GP4_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges 11 GP4_PWR_DO M 0 GP4_POL 1 GPIO4 Power Domain select 0 = DBVDD 1 = PVDD 10 GPIO4 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) 9 GP4_OD 0 GPIO4 Output pin configuration 0 = CMOS 1 = Open Drain 7 GP4_ENA 0 GPIO4 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation 3:0 GP4_FN [3:0] 0000 GPIO4 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input w PD, February 2012, Rev 4.0 172 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Reserved 7 = Reserved 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 403Bh GPIO4 Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16444 (403Ch) GPIO5 Control 15 GP5_DIR 1 GPIO5 pin direction 0 = Output 1 = Input 14:13 GP5_PULL [1:0] 01 GPIO5 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved 12 GP5_INT_MOD E 0 GPIO5 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP5_POL=1) or falling edge triggered (if GP5_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges 11 GP5_PWR_DO M 0 GP5_POL 1 GPIO5 Power Domain select 0 = DBVDD 1 = PVDD 10 GPIO5 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) 9 GP5_OD 0 GPIO5 Output pin configuration 0 = CMOS 1 = Open Drain 7 GP5_ENA 0 GPIO5 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation w PD, February 2012, Rev 4.0 173 WM8321 REGISTER Production Data BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 3:0 GP5_FN [3:0] 0000 GPIO5 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Reserved 7 = Reserved 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 403Ch GPIO5 Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16445 (403Dh) GPIO6 Control 15 GP6_DIR 1 GPIO6 pin direction 0 = Output 1 = Input 14:13 GP6_PULL [1:0] 01 GPIO6 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved 12 GP6_INT_MOD E 0 GPIO6 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP6_POL=1) or falling edge triggered (if GP6_POL=0) 1 = GPIO interrupt is triggered on rising and falling w PD, February 2012, Rev 4.0 174 WM8321 Production Data REGISTER BIT LABEL DEFAULT 11 GP6_PWR_DO M 0 GP6_POL 1 DESCRIPTION REFER TO ADDRESS edges GPIO6 Power Domain select 0 = DBVDD 1 = PVDD 10 GPIO6 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) 9 GP6_OD 0 GPIO6 Output pin configuration 0 = CMOS 1 = Open Drain 7 GP6_ENA 0 GPIO6 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation 3:0 GP6_FN [3:0] 0000 GPIO6 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Reserved 7 = Reserved 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 403Dh GPIO6 Control w PD, February 2012, Rev 4.0 175 WM8321 REGISTER Production Data BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16446 (403Eh) GPIO7 Control 15 GP7_DIR 1 GPIO7 pin direction 0 = Output 1 = Input 14:13 GP7_PULL [1:0] 01 GPIO7 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved 12 GP7_INT_MOD E 0 GPIO7 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP7_POL=1) or falling edge triggered (if GP7_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges 11 GP7_PWR_DO M 0 GP7_POL 1 GPIO7 Power Domain select 0 = DBVDD 1 = PMICVDD (LDO12) 10 GPIO7 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) 9 GP7_OD 0 GPIO7 Output pin configuration 0 = CMOS 1 = Open Drain 7 GP7_ENA 0 GPIO7 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation 3:0 GP7_FN [3:0] 0000 GPIO7 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Reserved 7 = Reserved w PD, February 2012, Rev 4.0 176 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 403Eh GPIO7 Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16447 (403Fh) GPIO8 Control 15 GP8_DIR 1 GPIO8 pin direction 0 = Output 1 = Input 14:13 GP8_PULL [1:0] 01 GPIO8 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved 12 GP8_INT_MOD E 0 GPIO8 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP8_POL=1) or falling edge triggered (if GP8_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges 11 GP8_PWR_DO M 0 GP8_POL 1 GPIO8 Power Domain select 0 = DBVDD 1 = PMICVDD (LDO12) 10 GPIO8 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) 9 GP8_OD 0 GPIO8 Output pin configuration 0 = CMOS 1 = Open Drain 7 GP8_ENA 0 GPIO8 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation 3:0 GP8_FN [3:0] 0000 GPIO8 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input w PD, February 2012, Rev 4.0 177 WM8321 REGISTER Production Data BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Reserved 7 = Reserved 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 403Fh GPIO8 Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16448 (4040h) GPIO9 Control 15 GP9_DIR 1 GPIO9 pin direction 0 = Output 1 = Input 14:13 GP9_PULL [1:0] 01 GPIO9 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved 12 GP9_INT_MOD E 0 GPIO9 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP9_POL=1) or falling edge triggered (if GP9_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges 11 GP9_PWR_DO M 0 GP9_POL 1 GPIO9 Power Domain select 0 = DBVDD 1 = PMICVDD (LDO12) 10 GPIO9 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) 9 GP9_OD 0 GPIO9 Output pin configuration 0 = CMOS 1 = Open Drain 7 GP9_ENA 0 GPIO9 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation w PD, February 2012, Rev 4.0 178 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 3:0 GP9_FN [3:0] 0000 GPIO9 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Reserved 7 = Reserved 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 4040h GPIO9 Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16449 (4041h) GPIO10 Control 15 GP10_DIR 1 GPIO10 pin direction 0 = Output 1 = Input 14:13 GP10_PULL [1:0] 01 GPIO10 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved 12 GP10_INT_MO DE 0 GPIO10 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP10_POL=1) or falling edge triggered (if GP10_POL=0) 1 = GPIO interrupt is triggered on rising and falling w PD, February 2012, Rev 4.0 179 WM8321 REGISTER Production Data BIT LABEL DEFAULT 11 GP10_PWR_D OM 0 GP10_POL 1 DESCRIPTION REFER TO ADDRESS edges GPIO10 Power Domain select 0 = DBVDD 1 = PVDD 10 GPIO10 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) 9 GP10_OD 0 GPIO10 Output pin configuration 0 = CMOS 1 = Open Drain 7 GP10_ENA 0 GPIO10 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation 3:0 GP10_FN [3:0] 0000 GPIO10 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Reserved 7 = Reserved 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 4041h GPIO10 Control w PD, February 2012, Rev 4.0 180 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16450 (4042h) GPIO11 Control 15 GP11_DIR 1 GPIO11 pin direction 0 = Output 1 = Input 14:13 GP11_PULL [1:0] 01 GPIO11 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved 12 GP11_INT_MO DE 0 GPIO11 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP11_POL=1) or falling edge triggered (if GP11_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges 11 GP11_PWR_D OM 0 GP11_POL 1 GPIO11 Power Domain select 0 = DBVDD 1 = PVDD 10 GPIO11 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) 9 GP11_OD 0 GPIO11 Output pin configuration 0 = CMOS 1 = Open Drain 7 GP11_ENA 0 GPIO11 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation 3:0 GP11_FN [3:0] 0000 GPIO11 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Reserved 7 = Reserved w PD, February 2012, Rev 4.0 181 WM8321 REGISTER Production Data BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 4042h GPIO11 Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16451 (4043h) GPIO12 Control 15 GP12_DIR 1 GPIO12 pin direction 0 = Output 1 = Input 14:13 GP12_PULL [1:0] 01 GPIO12 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved 12 GP12_INT_MO DE 0 GPIO12 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP12_POL=1) or falling edge triggered (if GP12_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges 11 GP12_PWR_D OM 0 GP12_POL 1 GPIO12 Power Domain select 0 = DBVDD 1 = PVDD 10 GPIO12 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) 9 GP12_OD 0 GPIO12 Output pin configuration 0 = CMOS 1 = Open Drain 7 GP12_ENA 0 GPIO12 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation 3:0 GP12_FN [3:0] 0000 GPIO12 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input w PD, February 2012, Rev 4.0 182 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Reserved 7 = Reserved 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 4043h GPIO12 Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16460 (404Ch) Status LED 1 15:14 LED1_SRC [1:0] 11 LED1 Source (Selects the LED1 function.) 00 = Off 01 = Power State Status 10 = Reserved 11 = Manual Mode Note - LED1 also indicates completion of OTP Auto Program 9:8 LED1_MODE [1:0] 00 LED1 Mode (Controls LED1 in Manual Mode only.) 00 = Off 01 = Constant 10 = Continuous Pulsed 11 = Pulsed Sequence 5:4 LED1_SEQ_LE N [1:0] 10 LED1 Pulse Sequence Length (when LED1_MODE = Pulsed Sequence) 00 = 1 pulse 01 = 2 pulses 10 = 4 pulses 11 = 7 pulses 3:2 LED1_DUR [1:0] 01 LED1 On time (when LED1_MODE = Continuous Pulsed or Pulsed Sequence) 00 = 1 second 01 = 250ms 10 = 125ms w PD, February 2012, Rev 4.0 183 WM8321 REGISTER Production Data BIT LABEL DEFAULT 1:0 LED1_DUTY_C YC [1:0] 10 DESCRIPTION REFER TO ADDRESS 11 = 62.5ms LED1 Duty Cycle (On:Off ratio) (when LED1_MODE = Continuous Pulsed or Pulsed Sequence) 00 = 1:1 (50% on) 01 = 1:2 (33.3% on) 10 = 1:3 (25% on) 11 = 1:7 (12.5% on) Register 404Ch Status LED 1 REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16461 (404Dh) Status LED 2 15:14 LED2_SRC [1:0] 11 LED2 Source (Selects the LED2 function.) 00 = Off 01 = Power State Status 10 = Reserved 11 = Manual Mode Note - LED2 also indicates an OTP Auto Program Error condition 9:8 LED2_MODE [1:0] 00 LED2 Mode (Controls LED2 in Manual Mode only.) 00 = Off 01 = Constant 10 = Continuous Pulsed 11 = Pulsed Sequence 5:4 LED2_SEQ_LE N [1:0] 10 LED2 Pulse Sequence Length (when LED2_MODE = Pulsed Sequence) 00 = 1 pulse 01 = 2 pulses 10 = 4 pulses 11 = 7 pulses 3:2 LED2_DUR [1:0] 01 LED2 On time (when LED2_MODE = Continuous Pulsed or Pulsed Sequence) 00 = 1 second 01 = 250ms 10 = 125ms 11 = 62.5ms 1:0 LED2_DUTY_C YC [1:0] 10 LED2 Duty Cycle (On:Off ratio) (when LED2_MODE = Continuous Pulsed or Pulsed Sequence) 00 = 1:1 (50% on) 01 = 1:2 (33.3% on) 10 = 1:3 (25% on) 11 = 1:7 (12.5% on) Register 404Dh Status LED 2 w PD, February 2012, Rev 4.0 184 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16464 (4050h) DCDC Enable 7 EPE2_ENA 0 EPE2 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in EPE2_STS) 6 EPE1_ENA 0 EPE1 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in EPE1_STS) 3 DC4_ENA 0 DC-DC4 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in DC4_STS) 2 DC3_ENA 0 DC-DC3 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in DC3_STS) 1 DC2_ENA 0 DC-DC2 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in DC2_STS) 0 DC1_ENA 0 DC_DC1 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in DC1_STS) Register 4050h DCDC Enable REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16465 (4051h) LDO Enable 10 LDO11_ENA 0 LDO11 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in LDO11_STS) 9 LDO10_ENA 0 LDO10 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in LDO10_STS) 8 LDO9_ENA 0 LDO9 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in LDO9_STS) 7 LDO8_ENA 0 LDO8 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in LDO8_STS) 6 LDO7_ENA 0 LDO7 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in LDO7_STS) 5 LDO6_ENA 0 LDO6 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in LDO6_STS) w PD, February 2012, Rev 4.0 185 WM8321 REGISTER Production Data BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 4 LDO5_ENA 0 LDO5 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in LDO5_STS) 3 LDO4_ENA 0 LDO4 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in LDO4_STS) 2 LDO3_ENA 0 LDO3 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in LDO3_STS) 1 LDO2_ENA 0 LDO2 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in LDO2_STS) 0 LDO1_ENA 0 LDO1 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in LDO1_STS) Register 4051h LDO Enable REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16466 (4052h) DCDC Status 7 EPE2_STS 0 EPE2 Status 0 = Disabled 1 = Enabled 6 EPE1_STS 0 EPE1 Status 0 = Disabled 1 = Enabled 3 DC4_STS 0 DC-DC4 Status 0 = Disabled 1 = Enabled 2 DC3_STS 0 DC-DC3 Status 0 = Disabled 1 = Enabled 1 DC2_STS 0 DC-DC2 Status 0 = Disabled 1 = Enabled 0 DC1_STS 0 DC-DC1 Status 0 = Disabled 1 = Enabled Register 4052h DCDC Status w PD, February 2012, Rev 4.0 186 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO DESCRIPTION REFER TO ADDRESS R16467 (4053h) LDO Status 10 LDO11_STS 0 LDO11 Status 0 = Disabled 1 = Enabled 9 LDO10_STS 0 LDO10 Status 0 = Disabled 1 = Enabled 8 LDO9_STS 0 LDO9 Status 0 = Disabled 1 = Enabled 7 LDO8_STS 0 LDO8 Status 0 = Disabled 1 = Enabled 6 LDO7_STS 0 LDO7 Status 0 = Disabled 1 = Enabled 5 LDO6_STS 0 LDO6 Status 0 = Disabled 1 = Enabled 4 LDO5_STS 0 LDO5 Status 0 = Disabled 1 = Enabled 3 LDO4_STS 0 LDO4 Status 0 = Disabled 1 = Enabled 2 LDO3_STS 0 LDO3 Status 0 = Disabled 1 = Enabled 1 LDO2_STS 0 LDO2 Status 0 = Disabled 1 = Enabled 0 LDO1_STS 0 LDO1 Status 0 = Disabled 1 = Enabled Register 4053h LDO Status REGISTER BIT LABEL DEFAULT 13 DC2_OV_STS 0 ADDRESS R16468 (4054h) DCDC UV Status DC-DC2 Overvoltage Status 0 = Normal 1 = Overvoltage 12 DC1_OV_STS 0 DC-DC1 Overvoltage Status 0 = Normal 1 = Overvoltage 9 DC2_HC_STS 0 DC-DC2 High Current Status 0 = Normal 1 = High Current 8 DC1_HC_STS 0 DC-DC1 High Current Status 0 = Normal 1 = High Current 3 DC4_UV_STS 0 DC-DC4 Undervoltage Status 0 = Normal w PD, February 2012, Rev 4.0 187 WM8321 REGISTER Production Data BIT LABEL DEFAULT 2 DC3_UV_STS 0 DESCRIPTION REFER TO ADDRESS 1 = Undervoltage DC-DC3 Undervoltage Status 0 = Normal 1 = Undervoltage 1 DC2_UV_STS 0 DC-DC2 Undervoltage Status 0 = Normal 1 = Undervoltage 0 DC1_UV_STS 0 DC-DC1 Undervoltage Status 0 = Normal 1 = Undervoltage Register 4054h DCDC UV Status REGISTER BIT LABEL DEFAULT 15 INTLDO_UV_S TS 0 DESCRIPTION REFER TO ADDRESS R16469 (4055h) LDO UV Status LDO13 (Internal LDO) Undervoltage Status 0 = Normal 1 = Undervoltage 9 LDO10_UV_ST S 0 LDO9_UV_ST S 0 LDO8_UV_ST S 0 LDO7_UV_ST S 0 LDO6_UV_ST S 0 LDO5_UV_ST S 0 LDO4_UV_ST S 0 LDO3_UV_ST S 0 LDO2_UV_ST S 0 LDO1_UV_ST S 0 LDO10 Undervoltage Status 0 = Normal 1 = Undervoltage 8 LDO9 Undervoltage Status 0 = Normal 1 = Undervoltage 7 LDO8 Undervoltage Status 0 = Normal 1 = Undervoltage 6 LDO7 Undervoltage Status 0 = Normal 1 = Undervoltage 5 LDO6 Undervoltage Status 0 = Normal 1 = Undervoltage 4 LDO5 Undervoltage Status 0 = Normal 1 = Undervoltage 3 LDO4 Undervoltage Status 0 = Normal 1 = Undervoltage 2 LDO3 Undervoltage Status 0 = Normal 1 = Undervoltage 1 LDO2 Undervoltage Status 0 = Normal 1 = Undervoltage 0 LDO1 Undervoltage Status 0 = Normal 1 = Undervoltage Register 4055h LDO UV Status w PD, February 2012, Rev 4.0 188 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16470 (4056h) DC1 Control 1 15:14 DC1_RATE [1:0] 10 DC-DC1 Voltage Ramp rate 00 = 1 step every 32us 01 = 1 step every 16us 10 = 1 step every 8us 11 = Immediate voltage change 12 DC1_PHASE 0 DC-DC1 Clock Phase Control 0 = Normal 1 = Inverted 9:8 DC1_FREQ [1:0] 00 DC-DC1 Switching Frequency 00 = Reserved 01 = 2.0MHz (2.2uH output inductor) 10 = 4.0MHz (1uH output inductor) 11 = 4.0MHz (0.5uH output inductor) This field can only be written to by loading configuration settings from OTP/ICE. In all other cases, this field is Read Only. 7 5:4 1:0 DC1_FLT DC1_SOFT_ST ART [1:0] DC1_CAP [1:0] 0 DC-DC1 Output float 00 0 = DC-DC1 output discharged when disabled 1 = DC-DC1 output floating when disabled DC-DC1 Soft-Start Control (Duration in each of the 8 startup current limiting steps.) 00 00 = 32us steps 01 = 64us steps 10 = 128us steps 11 = 256us steps DC-DC1 Output Capacitor 00 = 4.7uF to 20uF 01 = Reserved 10 = 22uF to 47uF 11 = Reserved This field can only be written to by loading configuration settings from OTP/ICE. In all other cases, this field is Read Only. Register 4056h DC1 Control 1 REGISTER BIT LABEL DEFAULT DESCRIPTION 15:14 DC1_ERR_AC T [1:0] 00 DC1_HWC_SR C [1:0] 00 DC-DC1 Hardware Control Source DC1_HWC_VS EL 0 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 DC-DC1 Hardware Control Voltage select DC1_HWC_M ODE [1:0] 11 0 = Set by DC1_ON_VSEL 1 = Set by DC1_SLP_VSEL DC-DC1 Hardware Control Operating Mode REFER TO ADDRESS R16471 (4057h) DC1 Control 2 12:11 10 9:8 w DC-DC1 Error Action (Undervoltage) 00 = Ignore 01 = Shut down converter 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. 00 = Forced Continuous Conduction Mode 01 = Disabled 10 = LDO Mode PD, February 2012, Rev 4.0 189 WM8321 REGISTER Production Data BIT LABEL DEFAULT 6:4 DC1_HC_THR [2:0] 000 DC1_HC_IND_ ENA 0 DESCRIPTION REFER TO ADDRESS 0 11 = Hysteretic Mode DC-DC1 High Current threshold 000 = 125mA 001 = 250mA 010 = 375mA 011 = 500mA 100 = 625mA 101 = 750mA 110 = 875mA 111 = 1000mA DC-DC1 High Current detect enable 0 = Disabled 1 = Enabled Register 4057h DC1 Control 2 REGISTER BIT LABEL DEFAULT 15:13 DC1_ON_SLO T [2:0] 000 DESCRIPTION REFER TO ADDRESS R16472 (4058h) DC1 ON Config DC-DC1 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 9:8 DC1_ON_MOD E [1:0] 01 DC-DC1 ON Operating Mode 00 = Forced Continuous Conduction Mode 01 = Auto Mode (Continuous / Discontinuous Conduction with Pulse-Skipping) 10 = LDO Mode 11 = Hysteretic Mode 6:2 DC1_ON_VSE L [6:2] 0_0000 DC-DC1 ON Voltage select DC1_ON_VSEL [6:0] selects the DC-DC1 output voltage from 0.6V to 1.8V in 12.5mV steps. DC1_ON_VSEL [6:2] also exist in ICE/OTP memory, controlling the voltage in 50mV steps. DC1_ON_VSEL [6:0] is coded as follows: 00h to 08h = 0.6V 09h = 0.6125V … 48h = 1.4V (see note) … 67h = 1.7875V 68h to 7Fh = 1.8V Note - Maximum output voltage selection in 4MHz switching mode is 48h (1.4V). 1:0 DC1_ON_VSE L [1:0] 00 DC-DC1 ON Voltage select DC1_ON_VSEL [6:0] selects the DC-DC1 output voltage from 0.6V to 1.8V in 12.5mV steps. See DC1_ON_VSEL [6:2] for definition. Register 4058h DC1 ON Config w PD, February 2012, Rev 4.0 190 WM8321 Production Data REGISTER BIT LABEL DEFAULT 15:13 DC1_SLP_SLO T [2:0] 000 DESCRIPTION REFER TO ADDRESS R16473 (4059h) DC1 SLEEP Control DC-DC1 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If DC-DC1 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the converter enters its SLEEP condition. 9:8 DC1_SLP_MO DE [1:0] 11 DC-DC1 SLEEP Operating Mode 00 = Forced Continuous Conduction Mode 01 = Auto Mode (Continuous / Discontinuous Conduction with Pulse-Skipping) 10 = LDO Mode 11 = Hysteretic Mode 6:0 DC1_SLP_VSE L [6:0] 000_0000 DC-DC1 SLEEP Voltage select 0.6V to 1.8V in 12.5mV steps 00h to 08h = 0.6V 09h = 0.6125V … 48h = 1.4V (see note) … 67h = 1.7875V 68h to 7Fh = 1.8V Note - Maximum output voltage selection in 4MHz switching mode is 48h (1.4V). Register 4059h DC1 SLEEP Control REGISTER BIT LABEL DEFAULT 12:11 DC1_DVS_SR C [1:0] 00 DESCRIPTION REFER TO ADDRESS R16474 (405Ah) DC1 DVS Control DC-DC1 DVS Control Source 00 = Disabled 01 = Enabled 10 = Controlled by Hardware DVS1 11 = Controlled by Hardware DVS2 6:0 DC1_DVS_VS EL [6:0] 000_0000 DC-DC1 DVS Voltage select 0.6V to 1.8V in 12.5mV steps 00h to 08h = 0.6V 09h = 0.6125V … 48h = 1.4V (see note) … 67h = 1.7875V w PD, February 2012, Rev 4.0 191 WM8321 REGISTER Production Data BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 68h to 7Fh = 1.8V Note - Maximum output voltage selection in 4MHz switching mode is 48h (1.4V). Register 405Ah DC1 DVS Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16475 (405Bh) DC2 Control 1 15:14 DC2_RATE [1:0] 10 DC-DC2 Voltage Ramp rate 00 = 1 step every 32us 01 = 1 step every 16us 10 = 1 step every 8us 11 = Immediate voltage change 12 DC2_PHASE 1 DC-DC2 Clock Phase Control 0 = Normal 1 = Inverted 9:8 DC2_FREQ [1:0] 00 DC-DC2 Switching Frequency 00 = Reserved 01 = 2.0MHz (2.2uH output inductor) 10 = 4.0MHz (1uH output inductor) 11 = 4.0MHz (0.5uH output inductor) This field can only be written to by loading configuration settings from OTP/ICE. In all other cases, this field is Read Only. 7 DC2_FLT 0 DC-DC2 Output float 0 = DC-DC2 output discharged when disabled 1 = DC-DC2 output floating when disabled 5:4 DC2_SOFT_ST ART [1:0] 00 DC-DC2 Soft-Start Control (Duration in each of the 8 startup current limiting steps.) 00 = 32us steps 01 = 64us steps 10 = 128us steps 11 = 256us steps 1:0 DC2_CAP [1:0] 00 DC-DC2 Output Capacitor 00 = 4.7uF to 20uF 01 = Reserved 10 = 22uF to 47uF 11 = Reserved This field can only be written to by loading configuration settings from OTP/ICE. In all other cases, this field is Read Only. Register 405Bh DC2 Control 1 REGISTER BIT LABEL DEFAULT 15:14 DC2_ERR_AC T [1:0] 00 DESCRIPTION REFER TO ADDRESS R16476 (405Ch) DC2 Control 2 DC-DC2 Error Action (Undervoltage) 00 = Ignore 01 = Shut down converter 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. w PD, February 2012, Rev 4.0 192 WM8321 Production Data REGISTER BIT LABEL DEFAULT 12:11 DC2_HWC_SR C [1:0] 00 DESCRIPTION REFER TO ADDRESS DC-DC2 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 10 DC2_HWC_VS EL 0 DC2_HWC_M ODE [1:0] 11 DC-DC2 Hardware Control Voltage select 0 = Set by DC2_ON_VSEL 1 = Set by DC2_SLP_VSEL 9:8 DC-DC2 Hardware Control Operating Mode 00 = Forced Continuous Conduction Mode 01 = Disabled 10 = LDO Mode 11 = Hysteretic Mode 6:4 DC2_HC_THR [2:0] 000 DC-DC2 High Current threshold 000 = 125mA 001 = 250mA 010 = 375mA 011 = 500mA 100 = 625mA 101 = 750mA 110 = 875mA 111 = 1000mA 0 DC2_HC_IND_ ENA 0 DC-DC2 High Current detect enable 0 = Disabled 1 = Enabled Register 405Ch DC2 Control 2 REGISTER BIT LABEL DEFAULT 15:13 DC2_ON_SLO T [2:0] 000 DESCRIPTION REFER TO ADDRESS R16477 (405Dh) DC2 ON Config DC-DC2 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 9:8 DC2_ON_MOD E [1:0] 01 DC-DC2 ON Operating Mode 00 = Forced Continuous Conduction Mode 01 = Auto Mode (Continuous / Discontinuous Conduction with Pulse-Skipping) 10 = LDO Mode 11 = Hysteretic Mode 6:2 DC2_ON_VSE L [6:2] 0_0000 DC-DC2 ON Voltage select DC2_ON_VSEL [6:0] selects the DC-DC2 output voltage from 0.6V to 1.8V in 12.5mV steps. DC2_ON_VSEL [6:2] also exist in ICE/OTP memory, controlling the voltage in 50mV steps. DC2_ON_VSEL [6:0] is coded as follows: 00h to 08h = 0.6V w PD, February 2012, Rev 4.0 193 WM8321 REGISTER Production Data BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 09h = 0.6125V … 48h = 1.4V (see note) … 67h = 1.7875V 68h to 7Fh = 1.8V Note - Maximum output voltage selection in 4MHz switching mode is 48h (1.4V). 1:0 DC2_ON_VSE L [1:0] 00 DC-DC2 ON Voltage select DC2_ON_VSEL [6:0] selects the DC-DC2 output voltage from 0.6V to 1.8V in 12.5mV steps. See DC2_ON_VSEL [6:2] for definition. Register 405Dh DC2 ON Config REGISTER BIT LABEL DEFAULT 15:13 DC2_SLP_SLO T [2:0] 000 DESCRIPTION REFER TO ADDRESS R16478 (405Eh) DC2 SLEEP Control DC-DC2 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If DC-DC2 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the converter enters its SLEEP condition. 9:8 DC2_SLP_MO DE [1:0] 11 DC-DC2 SLEEP Operating Mode 00 = Forced Continuous Conduction Mode 01 = Auto Mode (Continuous / Discontinuous Conduction with Pulse-Skipping) 10 = LDO Mode 11 = Hysteretic Mode 6:0 DC2_SLP_VSE L [6:0] 000_0000 DC-DC2 SLEEP Voltage select 0.6V to 1.8V in 12.5mV steps 00h to 08h = 0.6V 09h = 0.6125V … 48h = 1.4V (see note) … 67h = 1.7875V 68h to 7Fh = 1.8V Note - Maximum output voltage selection in 4MHz switching mode is 48h (1.4V). Register 405Eh DC2 SLEEP Control w PD, February 2012, Rev 4.0 194 WM8321 Production Data REGISTER BIT LABEL DEFAULT 12:11 DC2_DVS_SR C [1:0] 00 DESCRIPTION REFER TO ADDRESS R16479 (405Fh) DC2 DVS Control DC-DC2 DVS Control Source 00 = Disabled 01 = Enabled 10 = Controlled by Hardware DVS1 11 = Controlled by Hardware DVS2 6:0 DC2_DVS_VS EL [6:0] 000_0000 DC-DC2 DVS Voltage select 0.6V to 1.8V in 12.5mV steps 00h to 08h = 0.6V 09h = 0.6125V … 48h = 1.4V (see note) … 67h = 1.7875V 68h to 7Fh = 1.8V Note - Maximum output voltage selection in 4MHz switching mode is 48h (1.4V). Register 405Fh DC2 DVS Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16480 (4060h) DC3 Control 1 12 DC3_PHASE 0 DC-DC3 Clock Phase Control 0 = Normal 1 = Inverted 7 DC3_FLT 0 DC-DC3 Output float 0 = DC-DC3 output discharged when disabled 1 = DC-DC3 output floating when disabled 5:4 DC3_SOFT_ST ART [1:0] 01 DC-DC3 Soft-Start Control (Duration in each of the 3 intermediate startup current limiting steps.) 00 = Immediate start-up 01 = 512us steps 10 = 4.096ms steps 11 = 32.768ms steps 3:2 DC3_STNBY_L IM [1:0] 01 DC-DC3 Current Limit Sets the maximum DC output current in Hysteretic Mode. 00 = 50mA 01 = 100mA 10 = 200mA 11 = 400mA Protected by security key. 1:0 DC3_CAP [1:0] 00 DC-DC3 Output Capacitor 00 = 10uF to 20uF 01 = 10uF to 20uF 10 = 22uF to 45uF 11 = 47uF to 100uF This field can only be written to by loading configuration settings from OTP/ICE. In all other cases, this field is Read Only. Register 4060h DC3 Control 1 w PD, February 2012, Rev 4.0 195 WM8321 REGISTER Production Data BIT LABEL DEFAULT DESCRIPTION 15:14 DC3_ERR_AC T [1:0] 00 DC3_HWC_SR C [1:0] 00 DC-DC3 Hardware Control Source DC3_HWC_VS EL 0 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 DC-DC3 Hardware Control Voltage select DC3_HWC_M ODE [1:0] 11 DC-DC3 Hardware Control Operating Mode DC3_OVP 0 00 = Forced Continuous Conduction Mode 01 = Disabled 10 = LDO Mode 11 = Hysteretic Mode DC-DC3 Overvoltage Protection REFER TO ADDRESS R16481 (4061h) DC3 Control 2 12:11 10 DC-DC3 Error Action (Undervoltage) 00 = Ignore 01 = Shut down converter 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. 0 = Set by DC3_ON_VSEL 1 = Set by DC3_SLP_VSEL 9:8 7 0 = Disabled 1 = Enabled Register 4061h DC3 Control 2 REGISTER BIT LABEL DEFAULT 15:13 DC3_ON_SLO T [2:0] 000 DESCRIPTION REFER TO ADDRESS R16482 (4062h) DC3 ON Config DC-DC3 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 9:8 DC3_ON_MOD E [1:0] 01 DC-DC3 ON Operating Mode 00 = Forced Continuous Conduction Mode 01 = Auto Mode (Continuous / Discontinuous Conduction with Pulse-Skipping) 10 = LDO Mode 11 = Hysteretic Mode 6:2 DC3_ON_VSE L [6:2] 0_0000 DC-DC3 ON Voltage select DC3_ON_VSEL [6:0] selects the DC-DC3 output voltage from 0.85V to 3.4V in 25mV steps. DC3_ON_VSEL [6:2] also exist in ICE/OTP memory, controlling the voltage in 100mV steps. DC3_ON_VSEL [6:0] is coded as follows: 00h = 0.85V 01h = 0.875V … 65h = 3.375V w PD, February 2012, Rev 4.0 196 WM8321 Production Data REGISTER BIT LABEL DEFAULT 1:0 DC3_ON_VSE L [1:0] 00 DESCRIPTION REFER TO ADDRESS 66h to 7Fh = 3.4V DC-DC3 ON Voltage select DC3_ON_VSEL [6:0] selects the DC-DC3 output voltage from 0.85V to 3.4V in 25mV steps. See DC3_ON_VSEL [6:2] for definition. Register 4062h DC3 ON Config REGISTER BIT LABEL DEFAULT 15:13 DC3_SLP_SLO T [2:0] 000 DESCRIPTION REFER TO ADDRESS R16483 (4063h) DC3 SLEEP Control DC-DC3 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If DC-DC3 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the converter enters its SLEEP condition. 9:8 DC3_SLP_MO DE [1:0] 11 DC-DC3 SLEEP Operating Mode 00 = Forced Continuous Conduction Mode 01 = Auto Mode (Continuous / Discontinuous Conduction with Pulse-Skipping) 10 = LDO Mode 11 = Hysteretic Mode 6:0 DC3_SLP_VSE L [6:0] 000_0000 DC-DC3 SLEEP Voltage select 0.85V to 3.4V in 25mV steps 00h = 0.85V 01h = 0.875V … 65h = 3.375V 66h to 7Fh = 3.4V Register 4063h DC3 SLEEP Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16484 (4064h) DC4 Control 1 13 DC4_SLV 0 DC-DC4 Slave Mode select 0 = Disabled 1 = Enabled DC4_SLV = 1, then DC-DC4 is a slave to DC-DC3, and both converters are controlled by the DC-DC3 registers. This field can only be written to by loading configuration settings from OTP/ICE. In all other cases, this field is Read Only. w PD, February 2012, Rev 4.0 197 WM8321 REGISTER Production Data BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 12 DC4_PHASE 0 DC-DC4 Clock Phase Control 0 = Normal 1 = Inverted 7 DC4_FLT 0 DC-DC4 Output float 0 = DC-DC4 output discharged when disabled 1 = DC-DC4 output floating when disabled 5:4 DC4_SOFT_ST ART [1:0] 01 DC-DC4 Soft-Start Control (Duration in each of the 3 intermediate startup current limiting steps.) 00 = Immediate start-up 01 = 512us steps 10 = 4.096ms steps 11 = 32.768ms steps 3:2 DC4_STNBY_L IM [1:0] 01 DC-DC4 Current Limit Sets the maximum DC output current in Hysteretic Mode. 00 = 50mA 01 = 100mA 10 = 200mA 11 = 400mA Protected by security key. 1:0 DC4_CAP [1:0] 00 DC-DC4 Output Capacitor 00 = 10uF to 20uF 01 = 10uF to 20uF 10 = 22uF to 45uF 11 = 47uF to 100uF This field can only be written to by loading configuration settings from OTP/ICE. In all other cases, this field is Read Only. Register 4064h DC4 Control 1 REGISTER BIT LABEL DEFAULT 15:14 DC4_ERR_AC T [1:0] 00 DESCRIPTION REFER TO ADDRESS R16485 (4065h) DC4 Control 2 DC-DC4 Error Action (Undervoltage) 00 = Ignore 01 = Shut down converter 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. 12:11 DC4_HWC_SR C [1:0] 00 DC-DC4 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 10 DC4_HWC_VS EL 0 DC4_HWC_M ODE [1:0] 11 DC-DC4 Hardware Control Voltage select 0 = Set by DC4_ON_VSEL 1 = Set by DC4_SLP_VSEL 9:8 DC-DC4 Hardware Control Operating Mode 00 = Forced Continuous Conduction Mode 01 = Disabled 10 = LDO Mode 11 = Hysteretic Mode w PD, February 2012, Rev 4.0 198 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 7 DC4_OVP 0 DC-DC4 Overvoltage Protection 0 = Disabled 1 = Enabled Register 4065h DC4 Control 2 REGISTER BIT LABEL DEFAULT 15:13 DC4_ON_SLO T [2:0] 000 DESCRIPTION REFER TO ADDRESS R16486 (4066h) DC4 ON Config DC-DC4 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 9:8 DC4_ON_MOD E [1:0] 01 DC-DC4 ON Operating Mode 00 = Forced Continuous Conduction Mode 01 = Auto Mode (Continuous / Discontinuous Conduction with Pulse-Skipping) 10 = LDO Mode 11 = Hysteretic Mode 6:2 DC4_ON_VSE L [6:2] 0_0000 DC-DC4 ON Voltage select DC4_ON_VSEL [6:0] selects the DC-DC4 output voltage from 0.85V to 3.4V in 25mV steps. DC4_ON_VSEL [6:2] also exist in ICE/OTP memory, controlling the voltage in 100mV steps. DC4_ON_VSEL [6:0] is coded as follows: 00h = 0.85V 01h = 0.875V … 65h = 3.375V 66h to 7Fh = 3.4V 1:0 DC4_ON_VSE L [1:0] 00 DC-DC4 ON Voltage select DC4_ON_VSEL [6:0] selects the DC-DC4 output voltage from 0.85V to 3.4V in 25mV steps. See DC4_ON_VSEL [6:2] for definition. Register 4066h DC4 ON Config REGISTER BIT LABEL DEFAULT 15:13 DC4_SLP_SLO T [2:0] 000 DESCRIPTION REFER TO ADDRESS R16487 (4067h) DC4 SLEEP Control DC-DC4 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 w PD, February 2012, Rev 4.0 199 WM8321 REGISTER Production Data BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 111 = SLEEP voltage / operating mode transition in Timeslot 1 If DC-DC4 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the converter enters its SLEEP condition. 9:8 DC4_SLP_MO DE [1:0] 11 DC-DC4 SLEEP Operating Mode 00 = Forced Continuous Conduction Mode 01 = Continuous / Discontinuous Conduction with Pulse-Skipping 10 = LDO Mode 11 = Hysteretic Mode 6:0 DC4_SLP_VSE L [6:0] 000_0000 DC-DC4 SLEEP Voltage select 0.85V to 3.4V in 25mV steps 00h = 0.85V 01h = 0.875V … 65h = 3.375V 66h to 7Fh = 3.4V Register 4067h DC4 SLEEP Control REGISTER BIT LABEL DEFAULT 15:14 LDO1_ERR_A CT [1:0] 00 DESCRIPTION REFER TO ADDRESS R16488 (4068h) LDO1 Control LDO1 Error Action (Undervoltage) 00 = Ignore 01 = Shut down regulator 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. 12:11 LDO1_HWC_S RC [1:0] 00 LDO1 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 10 LDO1_HWC_V SEL 0 LDO1_HWC_M ODE [1:0] 10 LDO1 Hardware Control Voltage select 0 = Set by LDO1_ON_VSEL 1 = Set by LDO1_SLP_VSEL 9:8 LDO1 Hardware Control Operating Mode 00 = Low Power mode 01 = Turn converter off 10 = Low Power mode 11 = Set by LDO1_ON_MODE 7 LDO1_FLT 0 LDO1 Output float 0 = LDO1 output discharged when disabled 1 = LDO1 output floating when disabled 6 LDO1_SWI 0 LDO1 Switch Mode 0 = LDO mode 1 = Switch mode 0 LDO1_LP_MO DE 0 LDO1 Low Power Mode Select 0 = 50mA (reduced quiescent current) 1 = 20mA (minimum quiescent current) Selects which Low Power mode is used in ON, SLEEP, w PD, February 2012, Rev 4.0 200 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS or under HWC modes. Register 4068h LDO1 Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16489 (4069h) LDO1 ON Control 15:13 LDO1_ON_SL OT [2:0] 000 LDO1 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 8 LDO1_ON_MO DE 0 LDO1_ON_VS EL [4:0] 0_0000 LDO1 ON Operating Mode 0 = Normal mode 1 = Low Power mode 4:0 LDO1 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V … 0Eh = 1.60V 0Fh = 1.70V … 1Eh = 3.20V 1Fh = 3.30V Register 4069h LDO1 ON Control REGISTER BIT LABEL DEFAULT 15:13 LDO1_SLP_SL OT [2:0] 000 DESCRIPTION REFER TO ADDRESS R16490 (406Ah) LDO1 SLEEP Control LDO1 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO1 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. 8 LDO1_SLP_M ODE 1 LDO1 SLEEP Operating Mode 0 = Normal mode 1 = Low Power mode w PD, February 2012, Rev 4.0 201 WM8321 REGISTER Production Data BIT LABEL DEFAULT 4:0 LDO1_SLP_VS EL [4:0] 0_0000 DESCRIPTION REFER TO ADDRESS LDO1 SLEEP Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V … 0Eh = 1.60V 0Fh = 1.70V … 1Eh = 3.20V 1Fh = 3.30V Register 406Ah LDO1 SLEEP Control REGISTER BIT LABEL DEFAULT 15:14 LDO2_ERR_A CT [1:0] 00 DESCRIPTION REFER TO ADDRESS R16491 (406Bh) LDO2 Control LDO2 Error Action (Undervoltage) 00 = Ignore 01 = Shut down regulator 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. 12:11 LDO2_HWC_S RC [1:0] 00 LDO2 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 10 LDO2_HWC_V SEL 0 LDO2 Hardware Control Voltage select 0 = Set by LDO2_ON_VSEL 1 = Set by LDO2_SLP_VSEL 9:8 LDO2_HWC_M ODE [1:0] 10 LDO2 Hardware Control Operating Mode 00 = Low Power mode 01 = Turn converter off 10 = Low Power mode 11 = Set by LDO2_ON_MODE 7 LDO2_FLT 0 LDO2 Output float 0 = LDO2 output discharged when disabled 1 = LDO2 output floating when disabled 6 LDO2_SWI 0 LDO2 Switch Mode 0 = LDO mode 1 = Switch mode 0 LDO2_LP_MO DE 0 LDO2 Low Power Mode Select 0 = 50mA (reduced quiescent current) 1 = 20mA (minimum quiescent current) Selects which Low Power mode is used in ON, SLEEP, or under HWC modes. Register 406Bh LDO2 Control w PD, February 2012, Rev 4.0 202 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16492 (406Ch) LDO2 ON Control 15:13 LDO2_ON_SL OT [2:0] 000 LDO2 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 8 LDO2_ON_MO DE 0 LDO2_ON_VS EL [4:0] 0_0000 LDO2 ON Operating Mode 0 = Normal mode 1 = Low Power mode 4:0 LDO2 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V … 0Eh = 1.60V 0Fh = 1.70V … 1Eh = 3.20V 1Fh = 3.30V Register 406Ch LDO2 ON Control REGISTER BIT LABEL DEFAULT 15:13 LDO2_SLP_SL OT [2:0] 000 DESCRIPTION REFER TO ADDRESS R16493 (406Dh) LDO2 SLEEP Control LDO2 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO2 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. 8 LDO2_SLP_M ODE 1 LDO2 SLEEP Operating Mode 0 = Normal mode 1 = Low Power mode w PD, February 2012, Rev 4.0 203 WM8321 REGISTER Production Data BIT LABEL DEFAULT 4:0 LDO2_SLP_VS EL [4:0] 0_0000 DESCRIPTION REFER TO ADDRESS LDO2 SLEEP Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V … 0Eh = 1.60V 0Fh = 1.70V … 1Eh = 3.20V 1Fh = 3.30V Register 406Dh LDO2 SLEEP Control REGISTER BIT LABEL DEFAULT 15:14 LDO3_ERR_A CT [1:0] 00 DESCRIPTION REFER TO ADDRESS R16494 (406Eh) LDO3 Control LDO3 Error Action (Undervoltage) 00 = Ignore 01 = Shut down regulator 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. 12:11 LDO3_HWC_S RC [1:0] 00 LDO3 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 10 LDO3_HWC_V SEL 0 LDO3 Hardware Control Voltage select 0 = Set by LDO3_ON_VSEL 1 = Set by LDO3_SLP_VSEL 9:8 LDO3_HWC_M ODE [1:0] 10 LDO3 Hardware Control Operating Mode 00 = Low Power mode 01 = Turn converter off 10 = Low Power mode 11 = Set by LDO3_ON_MODE 7 LDO3_FLT 0 LDO3 Output float 0 = LDO3 output discharged when disabled 1 = LDO3 output floating when disabled 6 LDO3_SWI 0 LDO3 Switch Mode 0 = LDO mode 1 = Switch mode 0 LDO3_LP_MO DE 0 LDO3 Low Power Mode Select 0 = 50mA (reduced quiescent current) 1 = 20mA (minimum quiescent current) Selects which Low Power mode is used in ON, SLEEP, or under HWC modes. Register 406Eh LDO3 Control w PD, February 2012, Rev 4.0 204 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16495 (406Fh) LDO3 ON Control 15:13 LDO3_ON_SL OT [2:0] 000 LDO3 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 8 LDO3_ON_MO DE 0 LDO3_ON_VS EL [4:0] 0_0000 LDO3 ON Operating Mode 0 = Normal mode 1 = Low Power mode 4:0 LDO3 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V … 0Eh = 1.60V 0Fh = 1.70V … 1Eh = 3.20V 1Fh = 3.30V Register 406Fh LDO3 ON Control REGISTER BIT LABEL DEFAULT 15:13 LDO3_SLP_SL OT [2:0] 000 DESCRIPTION REFER TO ADDRESS R16496 (4070h) LDO3 SLEEP Control LDO3 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO3 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. 8 LDO3_SLP_M ODE 1 LDO3 SLEEP Operating Mode 0 = Normal mode 1 = Low Power mode w PD, February 2012, Rev 4.0 205 WM8321 REGISTER Production Data BIT LABEL DEFAULT 4:0 LDO3_SLP_VS EL [4:0] 0_0000 DESCRIPTION REFER TO ADDRESS LDO3 SLEEP Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V … 0Eh = 1.60V 0Fh = 1.70V … 1Eh = 3.20V 1Fh = 3.30V Register 4070h LDO3 SLEEP Control REGISTER BIT LABEL DEFAULT 15:14 LDO4_ERR_A CT [1:0] 00 DESCRIPTION REFER TO ADDRESS R16497 (4071h) LDO4 Control LDO4 Error Action (Undervoltage) 00 = Ignore 01 = Shut down regulator 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. 12:11 LDO4_HWC_S RC [1:0] 00 LDO4 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 10 LDO4_HWC_V SEL 0 LDO4 Hardware Control Voltage select 0 = Set by LDO4_ON_VSEL 1 = Set by LDO4_SLP_VSEL 9:8 LDO4_HWC_M ODE [1:0] 10 LDO4 Hardware Control Operating Mode 00 = Low Power mode 01 = Turn converter off 10 = Low Power mode 11 = Set by LDO4_ON_MODE 7 LDO4_FLT 0 LDO4 Output float 0 = LDO4 output discharged when disabled 1 = LDO4 output floating when disabled 6 LDO4_SWI 0 LDO4 Switch Mode 0 = LDO mode 1 = Switch mode 0 LDO4_LP_MO DE 0 LDO4 Low Power Mode Select 0 = 50mA (reduced quiescent current) 1 = 20mA (minimum quiescent current) Selects which Low Power mode is used in ON, SLEEP, or under HWC modes. Register 4071h LDO4 Control w PD, February 2012, Rev 4.0 206 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16498 (4072h) LDO4 ON Control 15:13 LDO4_ON_SL OT [2:0] 000 LDO4 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 8 LDO4_ON_MO DE 0 LDO4_ON_VS EL [4:0] 0_0000 LDO4 ON Operating Mode 0 = Normal mode 1 = Low Power mode 4:0 LDO4 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V … 0Eh = 1.60V 0Fh = 1.70V … 1Eh = 3.20V 1Fh = 3.30V Register 4072h LDO4 ON Control REGISTER BIT LABEL DEFAULT 15:13 LDO4_SLP_SL OT [2:0] 000 DESCRIPTION REFER TO ADDRESS R16499 (4073h) LDO4 SLEEP Control LDO4 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO4 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. 8 LDO4_SLP_M ODE 1 LDO4 SLEEP Operating Mode 0 = Normal mode 1 = Low Power mode w PD, February 2012, Rev 4.0 207 WM8321 REGISTER Production Data BIT LABEL DEFAULT 4:0 LDO4_SLP_VS EL [4:0] 0_0000 DESCRIPTION REFER TO ADDRESS LDO4 SLEEP Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V … 0Eh = 1.60V 0Fh = 1.70V … 1Eh = 3.20V 1Fh = 3.30V Register 4073h LDO4 SLEEP Control REGISTER BIT LABEL DEFAULT 15:14 LDO5_ERR_A CT [1:0] 00 DESCRIPTION REFER TO ADDRESS R16500 (4074h) LDO5 Control LDO5 Error Action (Undervoltage) 00 = Ignore 01 = Shut down regulator 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. 12:11 LDO5_HWC_S RC [1:0] 00 LDO5 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 10 LDO5_HWC_V SEL 0 LDO5 Hardware Control Voltage select 0 = Set by LDO5_ON_VSEL 1 = Set by LDO5_SLP_VSEL 9:8 LDO5_HWC_M ODE [1:0] 10 LDO5 Hardware Control Operating Mode 00 = Low Power mode 01 = Turn converter off 10 = Low Power mode 11 = Set by LDO5_ON_MODE 7 LDO5_FLT 0 LDO5 Output float 0 = LDO5 output discharged when disabled 1 = LDO5 output floating when disabled 6 LDO5_SWI 0 LDO5 Switch Mode 0 = LDO mode 1 = Switch mode 0 LDO5_LP_MO DE 0 LDO5 Low Power Mode Select 0 = 50mA (reduced quiescent current) 1 = 20mA (minimum quiescent current) Selects which Low Power mode is used in ON, SLEEP, or under HWC modes. Register 4074h LDO5 Control w PD, February 2012, Rev 4.0 208 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16501 (4075h) LDO5 ON Control 15:13 LDO5_ON_SL OT [2:0] 000 LDO5 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 8 LDO5_ON_MO DE 0 LDO5_ON_VS EL [4:0] 0_0000 LDO5 ON Operating Mode 0 = Normal mode 1 = Low Power mode 4:0 LDO5 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V … 0Eh = 1.60V 0Fh = 1.70V … 1Eh = 3.20V 1Fh = 3.30V Register 4075h LDO5 ON Control REGISTER BIT LABEL DEFAULT 15:13 LDO5_SLP_SL OT [2:0] 000 DESCRIPTION REFER TO ADDRESS R16502 (4076h) LDO5 SLEEP Control LDO5 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO5 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. 8 LDO5_SLP_M ODE 1 LDO5 SLEEP Operating Mode 0 = Normal mode 1 = Low Power mode w PD, February 2012, Rev 4.0 209 WM8321 REGISTER Production Data BIT LABEL DEFAULT 4:0 LDO5_SLP_VS EL [4:0] 0_0000 DESCRIPTION REFER TO ADDRESS LDO5 SLEEP Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V … 0Eh = 1.60V 0Fh = 1.70V … 1Eh = 3.20V 1Fh = 3.30V Register 4076h LDO5 SLEEP Control REGISTER BIT LABEL DEFAULT 15:14 LDO6_ERR_A CT [1:0] 00 DESCRIPTION REFER TO ADDRESS R16503 (4077h) LDO6 Control LDO6 Error Action (Undervoltage) 00 = Ignore 01 = Shut down regulator 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. 12:11 LDO6_HWC_S RC [1:0] 00 LDO6 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 10 LDO6_HWC_V SEL 0 LDO6 Hardware Control Voltage select 0 = Set by LDO6_ON_VSEL 1 = Set by LDO6_SLP_VSEL 9:8 LDO6_HWC_M ODE [1:0] 10 LDO6 Hardware Control Operating Mode 00 = Low Power mode 01 = Turn converter off 10 = Low Power mode 11 = Set by LDO6_ON_MODE 7 LDO6_FLT 0 LDO6 Output float 0 = LDO6 output discharged when disabled 1 = LDO6 output floating when disabled 6 LDO6_SWI 0 LDO6 Switch Mode 0 = LDO mode 1 = Switch mode 0 LDO6_LP_MO DE 0 LDO6 Low Power Mode Select 0 = 50mA (reduced quiescent current) 1 = 20mA (minimum quiescent current) Selects which Low Power mode is used in ON, SLEEP, or under HWC modes. Register 4077h LDO6 Control w PD, February 2012, Rev 4.0 210 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16504 (4078h) LDO6 ON Control 15:13 LDO6_ON_SL OT [2:0] 000 LDO6 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 8 LDO6_ON_MO DE 0 LDO6_ON_VS EL [4:0] 0_0000 LDO6 ON Operating Mode 0 = Normal mode 1 = Low Power mode 4:0 LDO6 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V … 0Eh = 1.60V 0Fh = 1.70V … 1Eh = 3.20V 1Fh = 3.30V Register 4078h LDO6 ON Control REGISTER BIT LABEL DEFAULT 15:13 LDO6_SLP_SL OT [2:0] 000 DESCRIPTION REFER TO ADDRESS R16505 (4079h) LDO6 SLEEP Control LDO6 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO6 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. 8 LDO6_SLP_M ODE 1 LDO6 SLEEP Operating Mode 0 = Normal mode 1 = Low Power mode w PD, February 2012, Rev 4.0 211 WM8321 REGISTER Production Data BIT LABEL DEFAULT 4:0 LDO6_SLP_VS EL [4:0] 0_0000 DESCRIPTION REFER TO ADDRESS LDO6 SLEEP Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V … 0Eh = 1.60V 0Fh = 1.70V … 1Eh = 3.20V 1Fh = 3.30V Register 4079h LDO6 SLEEP Control REGISTER BIT LABEL DEFAULT 15:14 LDO7_ERR_A CT [1:0] 00 DESCRIPTION REFER TO ADDRESS R16506 (407Ah) LDO7 Control LDO7 Error Action (Undervoltage) 00 = Ignore 01 = Shut down regulator 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. 12:11 LDO7_HWC_S RC [1:0] 00 LDO7 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 10 LDO7_HWC_V SEL 0 LDO7 Hardware Control Voltage select 0 = Set by LDO7_ON_VSEL 1 = Set by LDO7_SLP_VSEL 9:8 LDO7_HWC_M ODE [1:0] 10 LDO7 Hardware Control Operating Mode 00 = Low Power mode 01 = Turn converter off 10 = Low Power mode 11 = Set by LDO7_ON_MODE 7 LDO7_FLT 0 LDO7 Output float 0 = LDO7 output discharged when disabled 1 = LDO7 output floating when disabled 6 LDO7_SWI 0 LDO7 Switch Mode 0 = LDO mode 1 = Switch mode Register 407Ah LDO7 Control w PD, February 2012, Rev 4.0 212 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16507 (407Bh) LDO7 ON Control 15:13 LDO7_ON_SL OT [2:0] 000 LDO7 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 8 LDO7_ON_MO DE 0 LDO7_ON_VS EL [4:0] 0_0000 LDO7 ON Operating Mode 0 = Normal mode 1 = Low Power mode 4:0 LDO7 ON Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V … 0Ch = 1.60V 0Dh = 1.70V … 1Eh = 3.40V 1Fh = 3.50V Register 407Bh LDO7 ON Control REGISTER BIT LABEL DEFAULT 15:13 LDO7_SLP_SL OT [2:0] 000 DESCRIPTION REFER TO ADDRESS R16508 (407Ch) LDO7 SLEEP Control LDO7 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO7 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. 8 LDO7_SLP_M ODE 1 LDO7 SLEEP Operating Mode 0 = Normal mode 1 = Low Power mode w PD, February 2012, Rev 4.0 213 WM8321 REGISTER Production Data BIT LABEL DEFAULT 4:0 LDO7_SLP_VS EL [4:0] 0_0000 DESCRIPTION REFER TO ADDRESS LDO7 SLEEP Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V … 0Ch = 1.60V 0Dh = 1.70V … 1Eh = 3.40V 1Fh = 3.50V Register 407Ch LDO7 SLEEP Control REGISTER BIT LABEL DEFAULT 15:14 LDO8_ERR_A CT [1:0] 00 DESCRIPTION REFER TO ADDRESS R16509 (407Dh) LDO8 Control LDO8 Error Action (Undervoltage) 00 = Ignore 01 = Shut down regulator 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. 12:11 LDO8_HWC_S RC [1:0] 00 LDO8 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 10 LDO8_HWC_V SEL 0 LDO8 Hardware Control Voltage select 0 = Set by LDO8_ON_VSEL 1 = Set by LDO8_SLP_VSEL 9:8 LDO8_HWC_M ODE [1:0] 10 LDO8 Hardware Control Operating Mode 00 = Low Power mode 01 = Turn converter off 10 = Low Power mode 11 = Set by LDO8_ON_MODE 7 LDO8_FLT 0 LDO8 Output float 0 = LDO8 output discharged when disabled 1 = LDO8 output floating when disabled 6 LDO8_SWI 0 LDO8 Switch Mode 0 = LDO mode 1 = Switch mode Register 407Dh LDO8 Control w PD, February 2012, Rev 4.0 214 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16510 (407Eh) LDO8 ON Control 15:13 LDO8_ON_SL OT [2:0] 000 LDO8 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 8 LDO8_ON_MO DE 0 LDO8_ON_VS EL [4:0] 0_0000 LDO8 ON Operating Mode 0 = Normal mode 1 = Low Power mode 4:0 LDO8 ON Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V … 0Ch = 1.60V 0Dh = 1.70V … 1Eh = 3.40V 1Fh = 3.50V Register 407Eh LDO8 ON Control REGISTER BIT LABEL DEFAULT 15:13 LDO8_SLP_SL OT [2:0] 000 DESCRIPTION REFER TO ADDRESS R16511 (407Fh) LDO8 SLEEP Control LDO8 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO8 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. 8 LDO8_SLP_M ODE 1 LDO8 SLEEP Operating Mode 0 = Normal mode 1 = Low Power mode w PD, February 2012, Rev 4.0 215 WM8321 REGISTER Production Data BIT LABEL DEFAULT 4:0 LDO8_SLP_VS EL [4:0] 0_0000 DESCRIPTION REFER TO ADDRESS LDO8 SLEEP Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V … 0Ch = 1.60V 0Dh = 1.70V … 1Eh = 3.40V 1Fh = 3.50V Register 407Fh LDO8 SLEEP Control REGISTER BIT LABEL DEFAULT 15:14 LDO9_ERR_A CT [1:0] 00 DESCRIPTION REFER TO ADDRESS R16512 (4080h) LDO9 Control LDO9 Error Action (Undervoltage) 00 = Ignore 01 = Shut down regulator 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. 12:11 LDO9_HWC_S RC [1:0] 00 LDO9 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 10 LDO9_HWC_V SEL 0 LDO9 Hardware Control Voltage select 0 = Set by LDO9_ON_VSEL 1 = Set by LDO9_SLP_VSEL 9:8 LDO9_HWC_M ODE [1:0] 10 LDO9 Hardware Control Operating Mode 00 = Low Power mode 01 = Turn converter off 10 = Low Power mode 11 = Set by LDO9_ON_MODE 7 LDO9_FLT 0 LDO9 Output float 0 = LDO9 output discharged when disabled 1 = LDO9 output floating when disabled 6 LDO9_SWI 0 LDO9 Switch Mode 0 = LDO mode 1 = Switch mode Register 4080h LDO9 Control w PD, February 2012, Rev 4.0 216 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16513 (4081h) LDO9 ON Control 15:13 LDO9_ON_SL OT [2:0] 000 LDO9 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 8 LDO9_ON_MO DE 0 LDO9_ON_VS EL [4:0] 0_0000 LDO9 ON Operating Mode 0 = Normal mode 1 = Low Power mode 4:0 LDO9 ON Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V … 0Ch = 1.60V 0Dh = 1.70V … 1Eh = 3.40V 1Fh = 3.50V Register 4081h LDO9 ON Control REGISTER BIT LABEL DEFAULT 15:13 LDO9_SLP_SL OT [2:0] 000 DESCRIPTION REFER TO ADDRESS R16514 (4082h) LDO9 SLEEP Control LDO9 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO9 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. 8 LDO9_SLP_M ODE 1 LDO9 SLEEP Operating Mode 0 = Normal mode 1 = Low Power mode w PD, February 2012, Rev 4.0 217 WM8321 REGISTER Production Data BIT LABEL DEFAULT 4:0 LDO9_SLP_VS EL [4:0] 0_0000 DESCRIPTION REFER TO ADDRESS LDO9 SLEEP Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V … 0Ch = 1.60V 0Dh = 1.70V … 1Eh = 3.40V 1Fh = 3.50V Register 4082h LDO9 SLEEP Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16515 (4083h) LDO10 Control 15:14 LDO10_ERR_ ACT [1:0] 00 LDO10 Error Action (Undervoltage) 00 = Ignore 01 = Shut down regulator 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. 12:11 LDO10_HWC_ SRC [1:0] 00 LDO10 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 10 LDO10_HWC_ VSEL 0 LDO10 Hardware Control Voltage select 0 = Set by LDO10_ON_VSEL 1 = Set by LDO10_SLP_VSEL 9:8 LDO10_HWC_ MODE [1:0] 10 LDO10 Hardware Control Operating Mode 00 = Low Power mode 01 = Turn converter off 10 = Low Power mode 11 = Set by LDO10_ON_MODE 7 LDO10_FLT 0 LDO10 Output float 0 = LDO10 output discharged when disabled 1 = LDO10 output floating when disabled 6 LDO10_SWI 0 LDO10 Switch Mode 0 = LDO mode 1 = Switch mode Register 4083h LDO10 Control w PD, February 2012, Rev 4.0 218 WM8321 Production Data REGISTER BIT LABEL DEFAULT 15:13 LDO10_ON_SL OT [2:0] 000 DESCRIPTION REFER TO ADDRESS R16516 (4084h) LDO10 ON Control LDO10 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 8 LDO10_ON_M ODE 0 LDO10_ON_V SEL [4:0] 0_0000 LDO10 ON Operating Mode 0 = Normal mode 1 = Low Power mode 4:0 LDO10 ON Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V … 0Ch = 1.60V 0Dh = 1.70V … 1Eh = 3.40V 1Fh = 3.50V Register 4084h LDO10 ON Control REGISTER BIT LABEL DEFAULT 15:13 LDO10_SLP_S LOT [2:0] 000 DESCRIPTION REFER TO ADDRESS R16517 (4085h) LDO10 SLEEP Control LDO10 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO10 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. 8 LDO10_SLP_M ODE 1 LDO10 SLEEP Operating Mode 0 = Normal mode 1 = Low Power mode w PD, February 2012, Rev 4.0 219 WM8321 REGISTER Production Data BIT LABEL DEFAULT 4:0 LDO10_SLP_V SEL [4:0] 0_0000 DESCRIPTION REFER TO ADDRESS LDO10 SLEEP Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V … 0Ch = 1.60V 0Dh = 1.70V … 1Eh = 3.40V 1Fh = 3.50V Register 4085h LDO10 SLEEP Control REGISTER BIT LABEL DEFAULT 15:13 LDO11_ON_SL OT [2:0] 000 DESCRIPTION REFER TO ADDRESS R16519 (4087h) LDO11 ON Control LDO11 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 12 LDO11_FRCE NA 0 LDO11 Force Enable (allows LDO11 to be enabled at all times in the OFF, ON and SLEEP states) 0 = Disabled 1 = Enabled 7 LDO11_VSEL_ SRC 0 LDO11_ON_V SEL [3:0] 0000 LDO11 Voltage Select source 0 = Normal (LDO11 settings) 1 = Same as DC-DC Converter 1 3:0 LDO11 ON Voltage select 0.80V to 1.55V in 50mV steps 0h = 0.80V 1h = 0.85V 2h = 0.90V … Eh = 1.50V Fh = 1.55V Register 4087h LDO11 ON Control w PD, February 2012, Rev 4.0 220 WM8321 Production Data REGISTER BIT LABEL DEFAULT 15:13 LDO11_SLP_S LOT [2:0] 000 DESCRIPTION REFER TO ADDRESS R16520 (4088h) LDO11 SLEEP Control LDO11 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO11 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. 3:0 LDO11_SLP_V SEL [3:0] 0000 LDO11 SLEEP Voltage select 0.80V to 1.55V in 50mV steps 0h = 0.80V 1h = 0.85V 2h = 0.90V … Eh = 1.50V Fh = 1.55V Register 4088h LDO11 SLEEP Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16521 (4089h) EPE1 Control 15:13 EPE1_ON_SL OT [2:0] 000 EPE1 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 12:11 EPE1_HWC_S RC [1:0] 00 EPE1 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 8 EPE1_HWCEN A 0 EPE1 Hardware Control Enable 0 = EPE1 is controlled by EPE1_ENA (Hardware Control input(s) are ignored) 1 = EPE1 is controlled by HWC inputs (Hardware Control input(s) force EPE1 to be de-asserted) w PD, February 2012, Rev 4.0 221 WM8321 REGISTER Production Data BIT LABEL DEFAULT 7:5 EPE1_SLP_SL OT [2:0] 000 DESCRIPTION REFER TO ADDRESS EPE1 SLEEP Slot select 000 = No action 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = No action 111 = No action Register 4089h EPE1 Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16522 (408Ah) EPE2 Control 15:13 EPE2_ON_SL OT [2:0] 000 EPE2 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 12:11 EPE2_HWC_S RC [1:0] 00 EPE2 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 8 EPE2_HWCEN A 0 EPE2 Hardware Control Enable 0 = EPE2 is controlled by EPE2_ENA (Hardware Control input(s) are ignored) 1 = EPE2 is controlled by HWC inputs (Hardware Control input(s) force EPE2 to be de-asserted) 7:5 EPE2_SLP_SL OT [2:0] 000 EPE2 SLEEP Slot select 000 = No action 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = No action 111 = No action Register 408Ah EPE2 Control w PD, February 2012, Rev 4.0 222 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16526 (408Eh) Power Good Source 1 3 DC4_OK 0 DC-DC4 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled 2 DC3_OK 1 DC-DC3 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled 1 DC2_OK 1 DC-DC2 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled 0 DC1_OK 1 DC-DC1 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled Register 408Eh Power Good Source 1 REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16527 (408Fh) Power Good Source 2 9 LDO10_OK 1 LDO10 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled 8 LDO9_OK 1 LDO9 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled 7 LDO8_OK 1 LDO8 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled 6 LDO7_OK 1 LDO7 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled 5 LDO6_OK 1 LDO6 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled 4 LDO5_OK 1 LDO5 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled 3 LDO4_OK 1 LDO4 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled 2 LDO3_OK 1 LDO3 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled 1 LDO2_OK 1 LDO2 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled 0 LDO1_OK 1 LDO1 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled Register 408Fh Power Good Source 2 w PD, February 2012, Rev 4.0 223 WM8321 REGISTER Production Data BIT LABEL DEFAULT 15 CLKOUT_ENA 0 DESCRIPTION REFER TO ADDRESS R16528 (4090h) Clock Control 1 CLKOUT output enable 0 = Disabled 1 = Enabled Protected by security key. 13 CLKOUT_OD 0 CLKOUT pin configuration 0 = CMOS 1 = Open Drain 10:8 CLKOUT_SLO T [2:0] 000 CLKOUT output enable ON slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Do not enable 111 = Do not enable 6:4 CLKOUT_SLP SLOT [2:0] 000 CLKOUT output SLEEP slot select 000 = Controlled by CLKOUT_ENA 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = Controlled by CLKOUT_ENA 111 = Controlled by CLKOUT_ENA Register 4090h Clock Control 1 REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R16529 (4091h) Clock Control 2 15 XTAL_INH 0 Crystal Start-Up Inhibit 0 = Disabled 1 = Enabled When XTAL_INH=0, the internal RC oscillator will provide CLKOUT until the crystal oscillator is valid. When XTAL_INH=1, the ‘ON’ transition is inhibited until the crystal oscillator is valid. 13 XTAL_ENA 0 Crystal Oscillator Enable 0 = Disabled at all times 1 = Enabled in OFF, ON, SLEEP states (Note that the BACKUP behaviour is determined by XTAL_BKUPENA.) This field can only be written to by loading configuration settings from OTP/ICE. In all other cases, this field is Read Only. 12 XTAL_BKUPE NA 1 Selects the RTC and 32.768kHz oscillator in BACKUP state 0 = RTC unclocked in BACKUP 1 = RTC maintained in BACKUP (Note that XTAL_ENA must also be set if the RTC is to be maintained in BACKUP) Register 4091h Clock Control 2 w PD, February 2012, Rev 4.0 224 WM8321 Production Data REGISTER BIT LABEL 15:0 UNIQUE_ID [15:0] DEFAULT DESCRIPTION REFER TO DESCRIPTION REFER TO DESCRIPTION REFER TO DESCRIPTION REFER TO DESCRIPTION REFER TO DESCRIPTION REFER TO DESCRIPTION REFER TO ADDRESS R30720 (7800h) Unique ID 1 0000_0000 Unique ID, Word 7 _0000_000 0 Register 7800h Unique ID 1 REGISTER BIT LABEL 15:0 UNIQUE_ID [15:0] DEFAULT ADDRESS R30721 (7801h) Unique ID 2 0000_0000 Unique ID, Word 6 _0000_000 0 Register 7801h Unique ID 2 REGISTER BIT LABEL 15:0 UNIQUE_ID [15:0] DEFAULT ADDRESS R30722 (7802h) Unique ID 3 0000_0000 Unique ID, Word 5 _0000_000 0 Register 7802h Unique ID 3 REGISTER BIT LABEL 15:0 UNIQUE_ID [15:0] DEFAULT ADDRESS R30723 (7803h) Unique ID 4 0000_0000 Unique ID, Word 4 _0000_000 0 Register 7803h Unique ID 4 REGISTER BIT LABEL 15:0 UNIQUE_ID [15:0] DEFAULT ADDRESS R30724 (7804h) Unique ID 5 0000_0000 Unique ID, Word 3 _0000_000 0 Register 7804h Unique ID 5 REGISTER BIT LABEL 15:0 UNIQUE_ID [15:0] DEFAULT ADDRESS R30725 (7805h) Unique ID 6 0000_0000 Unique ID, Word 2 _0000_000 0 Register 7805h Unique ID 6 REGISTER BIT LABEL 15:0 UNIQUE_ID [15:0] DEFAULT ADDRESS R30726 (7806h) Unique ID 7 0000_0000 Unique ID, Word 1 _0000_000 0 Register 7806h Unique ID 7 w PD, February 2012, Rev 4.0 225 WM8321 REGISTER Production Data BIT LABEL 15:0 UNIQUE_ID [15:0] DEFAULT DESCRIPTION REFER TO DESCRIPTION REFER TO ADDRESS R30727 (7807h) Unique ID 8 0000_0000 Unique ID, Word 0 _0000_000 0 Register 7807h Unique ID 8 REGISTER BIT LABEL DEFAULT 15 OTP_AUTO_P ROG 0 ADDRESS R30736 (7810h) Customer OTP ID 14:1 0 If this bit is set when bootstrap data is loaded from ICE (in development mode), then the ICE contents will be programmed in the OTP. OTP_CUST_ID 00_0000_0 This field is checked when an ‘ON’ transition is [13:0] 000_0000 requested. A non-zero value is used to confirm valid data. OTP_CUST_FI NAL 0 If OTP_CUST_FINAL is set in the OTP and also set in the DCRW, then no further Writes are possible to the OTP. Register 7810h Customer OTP ID REGISTER BIT LABEL DEFAULT 15:13 DC2_ON_SLO T [2:0] 000 DESCRIPTION REFER TO ADDRESS R30737 (7811h) DC1 OTP Control DC-DC2 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 12:8 DC2_ON_VSE L [6:2] 0_0000 DC-DC2 ON Voltage select DC2_ON_VSEL [6:0] selects the DC-DC2 output voltage from 0.6V to 1.8V in 12.5mV steps. DC2_ON_VSEL [6:2] controls the voltage in 50mV steps. DC2_ON_VSEL [6:0] is coded as follows: 00h to 08h = 0.6V 09h = 0.6125V … 48h = 1.4V (see note) … 67h = 1.7875V 68h to 7Fh = 1.8V Note - Maximum output voltage selection in 4MHz switching mode is 48h (1.4V). 7:5 DC1_ON_SLO T [2:0] 000 DC-DC1 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 w PD, February 2012, Rev 4.0 226 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 4:0 DC1_ON_VSE L [6:2] 0_0000 DC-DC1 ON Voltage select DC1_ON_VSEL [6:0] selects the DC-DC1 output voltage from 0.6V to 1.8V in 12.5mV steps. DC1_ON_VSEL [6:2] controls the voltage in 50mV steps. DC1_ON_VSEL [6:0] is coded as follows: 00h to 08h = 0.6V 09h = 0.6125V … 48h = 1.4V (see note) … 67h = 1.7875V 68h to 7Fh = 1.8V Note - Maximum output voltage selection in 4MHz switching mode is 48h (1.4V). Register 7811h DC1 OTP Control REGISTER BIT LABEL DEFAULT 15:13 DC4_ON_SLO T [2:0] 000 DESCRIPTION REFER TO ADDRESS R30738 (7812h) DC2 OTP Control DC-DC4 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 12:8 DC4_ON_VSE L [6:2] 0_0000 DC-DC4 ON Voltage select DC4_ON_VSEL [6:0] selects the DC-DC3 output voltage from 0.85V to 3.4V in 25mV steps. DC4_ON_VSEL [6:2] controls the voltage in 100mV steps. DC4_ON_VSEL [6:0] is coded as follows: 00h = 0.85V 01h = 0.875V … 65h = 3.375V 66h to 7Fh = 3.4V 7:5 DC3_ON_SLO T [2:0] 000 DC-DC3 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 w PD, February 2012, Rev 4.0 227 WM8321 REGISTER Production Data BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 4:0 DC3_ON_VSE L [6:2] 0_0000 DC-DC3 ON Voltage select DC3_ON_VSEL [6:0] selects the DC-DC3 output voltage from 0.85V to 3.4V in 25mV steps. DC3_ON_VSEL [6:2] controls the voltage in 100mV steps. DC3_ON_VSEL [6:0] is coded as follows: 00h = 0.85V 01h = 0.875V … 65h = 3.375V 66h to 7Fh = 3.4V Register 7812h DC2 OTP Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R30739 (7813h) DC3 OTP Control 15 DC4_PHASE 0 DC-DC4 Clock Phase Control 0 = Normal 1 = Inverted 14 DC3_PHASE 0 DC-DC3 Clock Phase Control 0 = Normal 1 = Inverted 13 DC2_PHASE 1 DC-DC2 Clock Phase Control 0 = Normal 1 = Inverted 12 DC1_PHASE 0 DC-DC1 Clock Phase Control 0 = Normal 1 = Inverted 11:10 DC4_CAP [1:0] 00 DC-DC4 Output Capacitor 00 = 10uF to 20uF 01 = 10uF to 20uF 10 = 22uF to 45uF 11 = 47uF to 100uF This field can only be written to by loading configuration settings from OTP/ICE. In all other cases, this field is Read Only. 9:8 DC3_CAP [1:0] 00 DC-DC3 Output Capacitor 00 = 10uF to 20uF 01 = 10uF to 20uF 10 = 22uF to 45uF 11 = 47uF to 100uF This field can only be written to by loading configuration settings from OTP/ICE. In all other cases, this field is Read Only. 7:6 DC2_CAP [1:0] 00 DC-DC2 Output Capacitor 00 = 4.7uF to 20uF 01 = Reserved 10 = 22uF to 47uF 11 = Reserved This field can only be written to by loading configuration w PD, February 2012, Rev 4.0 228 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS settings from OTP/ICE. In all other cases, this field is Read Only. 5:4 DC1_CAP [1:0] 00 DC-DC1 Output Capacitor 00 = 4.7uF to 20uF 01 = Reserved 10 = 22uF to 47uF 11 = Reserved This field can only be written to by loading configuration settings from OTP/ICE. In all other cases, this field is Read Only. 3:2 DC2_FREQ [1:0] 00 DC-DC2 Switching Frequency 00 = Reserved 01 = 2.0MHz (2.2uH output inductor) 10 = 4.0MHz (1uH output inductor) 11 = 4.0MHz (0.5uH output inductor) This field can only be written to by loading configuration settings from OTP/ICE. In all other cases, this field is Read Only. 1:0 DC1_FREQ [1:0] 00 DC-DC1 Switching Frequency 00 = Reserved 01 = 2.0MHz (2.2uH output inductor) 10 = 4.0MHz (1uH output inductor) 11 = 4.0MHz (0.5uH output inductor) This field can only be written to by loading configuration settings from OTP/ICE. In all other cases, this field is Read Only. Register 7813h DC3 OTP Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R30740 (7814h) LDO1/2 OTP Control 15:13 LDO2_ON_SL OT [2:0] 000 LDO2 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 12:8 LDO2_ON_VS EL [4:0] 0_0000 LDO2 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V … 0Eh = 1.60V 0Fh = 1.70V … 1Eh = 3.20V 1Fh = 3.30V 7:5 LDO1_ON_SL OT [2:0] w 000 LDO1 ON Slot select 000 = Do not enable PD, February 2012, Rev 4.0 229 WM8321 REGISTER Production Data BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 4:0 LDO1_ON_VS EL [4:0] 0_0000 LDO1 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V … 0Eh = 1.60V 0Fh = 1.70V … 1Eh = 3.20V 1Fh = 3.30V Register 7814h LDO1/2 OTP Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R30741 (7815h) LDO3/4 OTP Control 15:13 LDO4_ON_SL OT [2:0] 000 LDO4 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 12:8 LDO4_ON_VS EL [4:0] 0_0000 LDO4 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V … 0Eh = 1.60V 0Fh = 1.70V … 1Eh = 3.20V 1Fh = 3.30V 7:5 LDO3_ON_SL OT [2:0] 000 LDO3 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 w PD, February 2012, Rev 4.0 230 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 4:0 LDO3_ON_VS EL [4:0] 0_0000 LDO3 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V … 0Eh = 1.60V 0Fh = 1.70V … 1Eh = 3.20V 1Fh = 3.30V Register 7815h LDO3/4 OTP Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R30742 (7816h) LDO5/6 OTP Control 15:13 LDO6_ON_SL OT [2:0] 000 LDO6 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 12:8 LDO6_ON_VS EL [4:0] 0_0000 LDO6 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V … 0Eh = 1.60V 0Fh = 1.70V … 1Eh = 3.20V 1Fh = 3.30V 7:5 LDO5_ON_SL OT [2:0] 000 LDO5 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 w PD, February 2012, Rev 4.0 231 WM8321 REGISTER Production Data BIT LABEL DEFAULT 4:0 LDO5_ON_VS EL [4:0] 0_0000 DESCRIPTION REFER TO ADDRESS LDO5 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V … 0Eh = 1.60V 0Fh = 1.70V … 1Eh = 3.20V 1Fh = 3.30V Register 7816h LDO5/6 OTP Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R30743 (7817h) LDO7/8 OTP Control 15:13 LDO8_ON_SL OT [2:0] 000 LDO8 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 12:8 LDO8_ON_VS EL [4:0] 0_0000 LDO8 ON Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V … 0Ch = 1.60V 0Dh = 1.70V … 1Eh = 3.40V 1Fh = 3.50V 7:5 LDO7_ON_SL OT [2:0] 000 LDO7 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 w PD, February 2012, Rev 4.0 232 WM8321 Production Data REGISTER BIT LABEL DEFAULT 4:0 LDO7_ON_VS EL [4:0] 0_0000 DESCRIPTION REFER TO ADDRESS LDO7 ON Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V … 0Ch = 1.60V 0Dh = 1.70V … 1Eh = 3.40V 1Fh = 3.50V Register 7817h LDO7/8 OTP Control REGISTER BIT LABEL DEFAULT 15:13 LDO10_ON_SL OT [2:0] 000 DESCRIPTION REFER TO ADDRESS R30744 (7818h) LDO9/10 OTP Control LDO10 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 12:8 LDO10_ON_V SEL [4:0] 0_0000 LDO10 ON Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V … 0Ch = 1.60V 0Dh = 1.70V … 1Eh = 3.40V 1Fh = 3.50V 7:5 LDO9_ON_SL OT [2:0] 000 LDO9 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 w PD, February 2012, Rev 4.0 233 WM8321 REGISTER Production Data BIT LABEL DEFAULT 4:0 LDO9_ON_VS EL [4:0] 0_0000 DESCRIPTION REFER TO ADDRESS LDO9 ON Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V … 0Ch = 1.60V 0Dh = 1.70V … 1Eh = 3.40V 1Fh = 3.50V Register 7818h LDO9/10 OTP Control REGISTER BIT LABEL DEFAULT 15:13 LDO11_ON_SL OT [2:0] 000 DESCRIPTION REFER TO ADDRESS R30745 (7819h) LDO11/EPE Control LDO11 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 11:8 LDO11_ON_V SEL [3:0] 0000 LDO11 ON Voltage select 0.80V to 1.55V in 50mV steps 0h = 0.80V 1h = 0.85V 2h = 0.90V … Eh = 1.50V Fh = 1.55V 7:5 EPE2_ON_SL OT [2:0] 000 EPE2 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 4:2 EPE1_ON_SL OT [2:0] 000 EPE1 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 w PD, February 2012, Rev 4.0 234 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 0 DC4_SLV 0 DC-DC4 Slave Mode select 0 = Disabled 1 = Enabled DC4_SLV = 1, then DC-DC4 is a slave to DC-DC3, and both converters are controlled by the DC-DC3 registers. This field can only be written to by loading configuration settings from OTP/ICE. In all other cases, this field is Read Only. Register 7819h LDO11/EPE Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R30746 (781Ah) GPIO1 OTP Control 15 GP1_DIR 1 GPIO1 pin direction 0 = Output 1 = Input 14:13 GP1_PULL [1:0] 01 GPIO1 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved 12 GP1_INT_MOD E 0 GPIO1 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP1_POL=1) or falling edge triggered (if GP1_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges 11 GP1_PWR_DO M 0 GP1_POL 1 GPIO1 Power Domain select 0 = DBVDD 1 = PMICVDD (LDO12) 10 GPIO1 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) 9 GP1_OD 0 GPIO1 Output pin configuration 0 = CMOS 1 = Open Drain 8 GP1_ENA 0 GPIO1 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation 7:4 GP1_FN [3:0] 0000 GPIO1 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input w PD, February 2012, Rev 4.0 235 WM8321 REGISTER Production Data BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Reserved 7 = Reserved 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset 2 XTAL_ENA 0 Crystal Oscillator Enable 0 = Disabled at all times 1 = Enabled in OFF, ON, SLEEP states (Note that the BACKUP behaviour is determined by XTAL_BKUPENA.) This field can only be written to by loading configuration settings from OTP/ICE. In all other cases, this field is Read Only. 1 XTAL_INH 0 Crystal Start-Up Inhibit 0 = Disabled 1 = Enabled When XTAL_INH=0, the internal RC oscillator will provide CLKOUT until the crystal oscillator is valid. When XTAL_INH=1, the ‘ON’ transition is inhibited until the crystal oscillator is valid. Register 781Ah GPIO1 OTP Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R30747 (781Bh) GPIO2 OTP Control 15 GP2_DIR 1 GPIO2 pin direction 0 = Output 1 = Input 14:13 GP2_PULL [1:0] 01 GPIO2 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved 12 GP2_INT_MOD E 0 GPIO2 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP2_POL=1) or falling edge triggered (if GP2_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges w PD, February 2012, Rev 4.0 236 WM8321 Production Data REGISTER BIT LABEL DEFAULT 11 GP2_PWR_DO M 0 GP2_POL 1 DESCRIPTION REFER TO ADDRESS GPIO2 Power Domain select 0 = DBVDD 1 = PMICVDD (LDO12) 10 GPIO2 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) 9 GP2_OD 0 GPIO2 Output pin configuration 0 = CMOS 1 = Open Drain 8 GP2_ENA 0 GPIO2 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation 7:4 GP2_FN [3:0] 0000 GPIO2 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Reserved 7 = Reserved 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset 3:1 CLKOUT_SLO T [2:0] 000 CLKOUT output enable ON slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 w PD, February 2012, Rev 4.0 237 WM8321 REGISTER Production Data BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Do not enable 111 = Do not enable 0 WDOG_ENA 1 Watchdog Timer Enable 0 = Disabled 1 = Enabled (enables the watchdog; does not reset it) Protected by security key. Register 781Bh GPIO2 OTP Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R30748 (781Ch) GPIO3 OTP Control 15 GP3_DIR 1 GPIO3 pin direction 0 = Output 1 = Input 14:13 GP3_PULL [1:0] 01 GPIO3 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved 12 GP3_INT_MOD E 0 GPIO3 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP3_POL=1) or falling edge triggered (if GP3_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges 11 GP3_PWR_DO M 0 GP3_POL 1 GPIO3 Power Domain select 0 = DBVDD 1 = PMICVDD (LDO12) 10 GPIO3 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) 9 GP3_OD 0 GPIO3 Output pin configuration 0 = CMOS 1 = Open Drain 8 GP3_ENA 0 GPIO3 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation 7:4 GP3_FN [3:0] 0000 GPIO3 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input w PD, February 2012, Rev 4.0 238 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Reserved 7 = Reserved 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 781Ch GPIO3 OTP Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R30749 (781Dh) GPIO4 OTP Control 15 GP4_DIR 1 GPIO4 pin direction 0 = Output 1 = Input 14:13 GP4_PULL [1:0] 01 GPIO4 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved 12 GP4_INT_MOD E 0 GPIO4 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP4_POL=1) or falling edge triggered (if GP4_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges 11 GP4_PWR_DO M 0 GP4_POL 1 GPIO4 Power Domain select 0 = DBVDD 1 = PVDD 10 GPIO4 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) 9 GP4_OD 0 GPIO4 Output pin configuration 0 = CMOS 1 = Open Drain 8 GP4_ENA 0 GPIO4 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation 7:4 GP4_FN [3:0] 0000 GPIO4 Pin Function Input functions: w PD, February 2012, Rev 4.0 239 WM8321 REGISTER Production Data BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Reserved 7 = Reserved 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset 3:2 LED1_SRC [1:0] 11 LED1 Source (Selects the LED1 function.) 00 = Off 01 = Power State Status 10 = Reserved 11 = Manual Mode Note - LED1 also indicates completion of OTP Auto Program 1:0 LED2_SRC [1:0] 11 LED2 Source (Selects the LED2 function.) 00 = Off 01 = Power State Status 10 = Reserved 11 = Manual Mode Note - LED2 also indicates an OTP Auto Program Error condition Register 781Dh GPIO4 OTP Control w PD, February 2012, Rev 4.0 240 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R30750 (781Eh) GPIO5 OTP Control 15 GP5_DIR 1 GPIO5 pin direction 0 = Output 1 = Input 14:13 GP5_PULL [1:0] 01 GPIO5 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved 12 GP5_INT_MOD E 0 GPIO5 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP5_POL=1) or falling edge triggered (if GP5_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges 11 GP5_PWR_DO M 0 GP5_POL 1 GPIO5 Power Domain select 0 = DBVDD 1 = PVDD 10 GPIO5 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) 9 GP5_OD 0 GPIO5 Output pin configuration 0 = CMOS 1 = Open Drain 8 GP5_ENA 0 GPIO5 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation 7:4 GP5_FN [3:0] 0000 GPIO5 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Reserved 7 = Reserved w PD, February 2012, Rev 4.0 241 WM8321 REGISTER Production Data BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 781Eh GPIO5 OTP Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R30751 (781Fh) GPIO6 OTP Control 15 GP6_DIR 1 GPIO6 pin direction 0 = Output 1 = Input 14:13 GP6_PULL [1:0] 01 GPIO6 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved 12 GP6_INT_MOD E 0 GPIO6 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP6_POL=1) or falling edge triggered (if GP6_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges 11 GP6_PWR_DO M 0 GP6_POL 1 GPIO6 Power Domain select 0 = DBVDD 1 = PVDD 10 GPIO6 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) 9 GP6_OD 0 GPIO6 Output pin configuration 0 = CMOS 1 = Open Drain 8 GP6_ENA 0 GPIO6 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation 7:4 GP6_FN [3:0] 0000 GPIO6 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input w PD, February 2012, Rev 4.0 242 WM8321 Production Data REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Reserved 7 = Reserved 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset 3:1 SYSOK_THR [2:0] 101 SYSOK threshold (rising PVDD) This is the rising PVDD voltage at which SYSOK will be asserted 000 = 2.8V 001 = 2.9V … 111 = 3.5V Note that the SYSOK hysteresis margin is added to these threshold levels. Register 781Fh GPIO6 OTP Control REGISTER BIT LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R30759 (7827h) ICE CHECK DATA 15:0 ICE_VALID_D ATA [15:0] 0000_0000 This field is checked in development mode when an _0000_000 ‘ON’ transition is requested. A value of A596h is required to confirm valid data. 0 Register 7827h ICE CHECK DATA w PD, February 2012, Rev 4.0 243 WM8321 Production Data 30 APPLICATIONS INFORMATION 30.1 TYPICAL CONNECTIONS Figure 28 WM8321 Typical Connections Diagram For detailed schematics, bill of materials and recommended external components refer to the WM8321 evaluation board users manual. w PD, February 2012, Rev 4.0 244 WM8321 Production Data 30.2 VOLTAGE AND CURRENT REFERENCE COMPONENTS A decoupling capacitor is required between VREFC and GND; a 100nF X5R capacitor is recommended (available in 0201 package size). A current reference resistor is required between IREFR and GND; a 100k (1%) resistor is recommended. 30.3 DC-DC BUCK CONVERTER EXTERNAL COMPONENTS The recommended connections to the DC-DC buck converters are illustrated in Figure 29. Figure 29 DC-DC Buck Converter External Components When selecting suitable capacitors, is it imperative that the effective capacitance is within the required limits at the applicable input/output voltage of the converter. It should be noted that some components’ capacitance changes significantly depending on the DC voltage applied. Ceramic X7R or X5R types are recommended. The choice of output capacitor varies depending on the required transient response. Larger values may be required for optimum performance under large load transient conditions. Smaller values may be sufficient for a steady load, or in applications without stringent requirements on output voltage accuracy during load transients. For layout and size reasons, users may choose to implement large values of output capacitance by connecting two or more capacitors in parallel. To ensure stable operation, the DCm_CAP register fields must be set according to the output capacitance, as described in Section 15.6. When selecting a suitable output inductor, the inductance value and the saturation current must be compatible with the operating conditions of the converter. The magnitude of the inductor current ripple is dependant on the inductor value and can be determined by the following equation: w PD, February 2012, Rev 4.0 245 WM8321 Production Data As a minimum requirement, the DC current rating should be equal to the maximum load current plus one half of the inductor current ripple: To be suitable for the application, the chosen inductor must have a saturation current that is higher than the peak inductor current given by the above equation. To maximise the converter efficiency, the inductor should also have a low DC Resistance (DCR), resulting in minimum conduction losses. Care should also be taken to ensure that the component’s inductance is valid at the applicable operating temperature. The WM8321 incorporates a current-limit protection feature for all DC-DC Converter outputs. In order to achieve the benefit of this feature, the output inductor saturation current limit must be greater than or equal to the P-channel Current Limit for the applicable converter (see Section 7). Wolfson recommends the following external components for use with DC-DC Converters 1 and 2. The output inductor must be consistent with the DCm_FREQ register settings. The supported configurations are listed in Table 84. Note that for output voltages greater than 1.4V, the 2MHz mode must be used. DCm_FREQ SWITCHING FREQUENCY OUTPUT INDUCTOR COMMENTS 00 n/a n/a n/a 01 2MHz 2.2H Best efficiency 10 4MHz 1.0H Good transient performance and efficiency 11 4MHz 0.5H Best transient performance Table 84 Output Inductor Selection - DC-DC1, DC-DC2 The output capacitor must be consistent with the DCm_CAP register settings. For best performance, the 47F component is recommended. For typical applications, the 22F is suitable. The alternative values may be used for size or cost reasons if preferred. COMPONENT VALUE PART NUMBER SIZE L 0.5H Coilcraft XPL2010-501ML_ 1.9 x 2 x 1mm 1.0H Coilcraft XFL3012-102ME_ 3 x 3 x 1.2mm 2.2H Coilcraft LPS3015-222ML_ 3 x 3 x 1.5mm 0805 COUT CIN 47F MuRata GRM21BR60G476MEA1 22F MuRata GRM21BR60J226ME39 0805 10F MuRata GRM188R60J106ME84 0603 4.7F MuRata GRM188R60J475ME84 0603 10F MuRata GRM188R60J106ME84 0603 Table 85 Recommended External Components - DC-DC1, DC-DC2 w PD, February 2012, Rev 4.0 246 WM8321 Production Data Wolfson recommends the following external components for use with DC-DC Converters 3 and 4. Note that the switching frequency of DC-DC3 and DC-DC4 is fixed at 2MHz and the output inductor must be 2.2H in all cases. The output capacitor must be consistent with the DCm_CAP register setting. For best performance, the 47F component is recommended. For typical applications, the 22F is suitable. The alternative values may be used for size or cost reasons if preferred. COMPONENT VALUE PART NUMBER SIZE L 2.2H Coilcraft LPS3015-222ML_ 3 x 3 x 1.5mm 0805 COUT CIN 47F MuRata GRM21BR60G476MEA1 22F MuRata GRM21BR60J226ME39 0805 10F MuRata GRM188R60J106ME84 0603 4.7F MuRata GRM188R60J475ME84 0603 Table 86 Recommended External Components - DC-DC3, DC-DC4 w PD, February 2012, Rev 4.0 247 WM8321 Production Data 30.3.1 DC-DC3 / DC-DC4 DUAL MODE When DC-DC3 and DC-DC4 are operating in dual mode, the external component configuration for each converter is the same as previously noted for single converters. The output load connection points (Vo) are simply connected together as shown in Figure 30. 2.7V – 5.5V DC3VDD DC3FB CIN L DC3LX VO COUT DC3GND WM8321 DC4VDD DC4_SLV = 1 DC4FB CIN L DC4LX VO COUT Load DC4GND Figure 30 DC-DC3 / DC-DC4 Dual Mode Converter Connections Wolfson recommends the following external components for use with DC-DC Converters 3 and 4 when operating in Dual Mode. The output capacitor must be consistent with the DCm_CAP register setting. For best performance, the 47F component is recommended. For typical applications, the 22F is suitable. The alternative values may be used for size or cost reasons if preferred. COMPONENT VALUE PART NUMBER SIZE L 2.2H Coilcraft LPS3015-222ML_ 3 x 3 x 1.5mm COUT 47F MuRata GRM21BR60G476MEA1 0805 22F MuRata GRM21BR60J226ME39 0805 10F MuRata GRM188R60J106ME84 0603 4.7F MuRata GRM188R60J475ME84 0603 CIN Table 87 Recommended External Components - DC-DC3 / DC-DC4 Dual Mode w PD, February 2012, Rev 4.0 248 WM8321 Production Data 30.4 LDO REGULATOR EXTERNAL COMPONENTS The recommended connections to the LDO Regulators are illustrated in Figure 31. Figure 31 LDO Regulators External Components When selecting suitable capacitors, is it imperative that the effective capacitance is within the required limits at the applicable input/output voltage of the converter. Ceramic X7R or X5R types are recommended. Wolfson recommends the following external components for use with LDO Regulators 1 to 6. COMPONENT VALUE PART NUMBER COUT 2.2μF Kemet C0402C225M9PAC SIZE 0402 CIN 1.0μF MuRata GRM155R61A105KE15 0402 Table 88 Recommended External Components - LDO1 to LDO6 Wolfson recommends the following external components for use with LDO Regulators 7 to 10. For these regulators, note that it is important that the output capacitance, COUT, does not exceed 4.7F. COMPONENT VALUE PART NUMBER SIZE COUT 1.0μF MuRata GRM155R61A105KE15 0402 CIN 1.0μF MuRata GRM155R61A105KE15 0402 Table 89 Recommended External Components - LDO7 to LDO10 Wolfson recommends the following external components for use with LDO Regulators 11 to 13. COMPONENT VALUE PART NUMBER SIZE COUT (LDO11) 0.1μF MuRata GRM033R60J104KE19 0201 COUT (LDO12) 0.1μF MuRata GRM033R60J104KE19 0201 COUT (LDO13) 2.2μF Kemet C0402C225M9PAC 0402 Table 90 Recommended External Components - LDO11 to LDO13 w PD, February 2012, Rev 4.0 249 WM8321 Production Data 30.5 PCB LAYOUT Poor PCB layout will degrade the performance and be a contributory factor in EMI, ground bounce and resistive voltage losses. Poor regulation and instability can result. Simple design rules can be implemented to negate these effects: External input and output capacitors should be placed as close to the device as possible using short wide traces between the external power components. For the DC-DC Converters, the input capacitor placement takes priority on the DC-DC converters. (For the LDO Regulators, the placement of the input and output capacitors have equal priority.) Route the DC-DC converter output voltage feedback as an independent connection to the top of the output capacitor to create a true sense of the output voltage, routing away from noisy signals such as the LX connection. Use a local ground island for each individual DC-DC converter connected at a single point onto a fully flooded ground plane. Current loop areas should be kept as small as possible with loop areas changing little during alternating switching cycles. The layout in Figure 32, for example, shows DC-DC1 layout with external components C8, L1 and C1. The input capacitor, C8, is close into the IC and shares a small ground island with the output capacitor C1. The inductor, L1, is situated in close proximity to C1 in order to keep loop area small and minimise the trace resistance. Note also the use of short wide traces with all power tracking on a single (top) layer. Figure 32 PCB Layout w PD, February 2012, Rev 4.0 250 WM8321 Production Data 31 PACKAGE DIAGRAM FL: 81 PIN QFN PLASTIC PACKAGE 8 X 8 X 0.85 mm BODY DM082.B D2 eee C B A A4 A3 B4 A2 B2 B3 3.675 F2 B5 2.675 3.175 F3 A5 B6 2.525 2.025 1.375 D2 B7 1.225 D3 A6 A7 B8 1.875 2.025 2.675 0.750 A8 B9 0 A9 B10 0.330 A10 B11 0.750 A11 3.175 1.500 2.565 1.955 3.675 1.080 3.675 3.175 3.065 DETAIL D A1 B1 C1 DETAIL A DETAIL B E1 F1 G1 EXPOSED GND PADDLE 1.375 H3 H2 0.725 K3 K2 M3 M2 0.575 N3 N2 1.225 R3 R2 H1 J1 0 L1 M1 P1 2.525 V4 3.175 W12 W11 3.675 Y12 Y11 Y10 3.675 3.175 3.025 2.525 2.375 U2 U1 V3 V2 2.375 2.025 1.725 1.375 1.075 0.260 0.075 E2 eee C B A E 0.990 1.225 R1 U3 3.025 0.575 N1 1.875 3.675 3.175 0.725 K1 0.075 B 2.675 D1 DETAIL C D A PIN 1 CORNER T1 1.805 1.875 V1 2.525 3.175 Y4 Y3 Y2 Y1 3.675 2.925 3.675 W1 3.175 W2 2.175 1.375 Y5 Y6 0.875 Y7 W3 W4 W5 0.725 1.225 1.075 Y8 1.875 1.725 Y9 W6 W7 0.075 0.225 W8 0.575 0.425 W9 1.525 C W10 aaa C TOP VIEW BOTTOM VIEW 68x 4x L L2 ddd M C A B ddd M C A B ddd M C A B b b DETAIL A ddd M C A B DETAIL C L1 Ø0.25±0.03 ddd M C A B ddd M C A B b ddd M C A B DETAIL B Symbols L2 aaa bbb ccc ddd eee REF MIN --0.02 0.64 0.12 0.22 5.55 5.55 0.22 0.37 bbb C (A3) A A2 8x A A1 A2 A3 b D D2 E E2 L L1 C A1 C SECTION C-C ccc C DETAIL D Dimensions (mm) NOM MAX --0.85 0.08 0.05 0.675 0.71 0.13 0.14 0.25 0.28 8 BSC 5.60 5.65 8 BSC 5.60 5.65 0.25 0.28 0.43 0.4 NOTE 0.53 0.5 0.47 Tolerances of Form and Position 0.10 0.20 0.05 0.08 0.10 JEDEC, MO-220 NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETRES 2. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-002. 3. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. w PD, February 2012, Rev 4.0 251 WM8321 Production Data 32 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer’s own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: [email protected] w PD, February 2012, Rev 4.0 252 WM8321 Production Data 33 REVISION HISTORY DATE REV DESCRIPTION OF CHANGES CHANGED BY October 2010 2.0 SDOUT1 description amended to Open Drain, with external pull-up required. PH December 2010 2.0 Default value of PWRSTATE_DLY corrected. PH Undervoltage margin specified for all DC-DC converters. Overvoltage margin specified for DC-DC converters 1,2. Chip Temperature (AUX_DATA) equation updated. 07/03/11 2.0 Added notes that SLEEP > OFF is not a controlled transition; converters and regulators are disabled immediately. PH RESET pin description updated to note integrated pull-up. IRQ description updated to note pull-up in Open Drain mode. System Reset and Device Reset descriptions updated, consistent with the Summary Table. Recommended external pull-up resistances added in Pin Description. Internal pull-up / pull-down resistances added in Electrical Characteristics. Noted Active High (non-inverted) polarity for GPIO “Power On/Off request” function is not fully supported in development mode. 25/03/11 3.0 Noted maximum limit on Software Resets. Also clarification of the maximum number of Watchdog / Undervoltage Device Resets. PH Correction to DBVDD test conditions (Section 7.7). RTC_PINT_FREQ definition updated. DC-DC output inductor saturation limit recommendations added. SYSOK_THR register description updated. Quiescent current characteristics updated for DC-DC 1-4. 15/09/11 4.0 Backup battery power updated; Charger control registers deleted. PH LDO11 output amended for LDO11_VSEL_SRC=1 and DC-DC1 disabled. OTP Register Map overview correction (GPn_TRI replaced with GPn_ENA). LDO11 maximum output current increased (only for PVDD ≥ 3.1V). 01/02/12 4.0 Electrical Characteristics updated. PH DC3_STNBY_LIM, DC4_STNBY_LIM descriptions updated. SYSOK_THR description updated. 14/02/12 4.0 w Product status updated to Production Data JMacD PD, February 2012, Rev 4.0 253