WM8533 w 24-bit 192kHz Stereo DAC with 2Vrms Ground Referenced Line Output DESCRIPTION FEATURES The WM8533 is a stereo DAC with integral charge pump and software control interface. This provides 2Vrms line driver outputs using a 3.3V power supply rail. The device features ground-referenced outputs and the use of a DC servo to eliminate the need for line driving coupling capacitors and effectively eliminate power on pops and clicks. The device is controlled and configured either via the I2C/SPI compliant serial control interface or a hardware control interface. The device supports all common audio sampling rates between 8kHz and 192kHz using all common MCLK / fs ratios. Master and slave modes are available and deemphasis is also supported. The WM8533 has a 1.8 to 3.3V tolerant digital interface, allowing logic up to 3.3V to be connected. The device is available in a 1.842 x 1.772mm 20-ball WCSP. High performance stereo DAC with ground referenced line driver Audio performance 106dB SNR (‘A-weighted’) -89dB THD @ -1dBFS Digital volume control ranging from -100dB to +12dB 120dB mute attenuation All common sample rates from 8kHz to 192kHz supported 2 I C/SPI compatible and hardware control modes 2 Data formats: LJ, RJ, I S, DSP De-emphasis supported Maximum 1mV DC offset on line outputs Pop/click suppressed power up/down sequencer AVDD and LINEVDD +3.3V ±10% allowing single supply DBVDD supply supports +1.8V or +3.3V digital I/O 1.842 x 1.772mm 20-ball WCSP APPLICATIONS Consumer digital audio applications requiring 2Vrms output Set Top Box Digital TV DVD Players Games Consoles A/V Receivers BLOCK DIAGRAM W CONTROL INTERFACE WM8533 LEFT DAC MCLK BCLK LRCLK DACDAT DIGITAL AUDIO INTERFACE DIGITAL FILTERS LINEOUTL LINEREF RIGHT DAC LINEOUTR CHARGE PUMP WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews Production Data, July 2012, Rev 4.0 Copyright 2012 Wolfson Microelectronics plc WM8533 Production Data TABLE OF CONTENTS DESCRIPTION ....................................................................................................... 1 FEATURES ............................................................................................................ 1 APPLICATIONS .................................................................................................... 1 BLOCK DIAGRAM ................................................................................................ 1 TABLE OF CONTENTS......................................................................................... 2 PIN CONFIGURATION .......................................................................................... 3 ORDERING INFORMATION .................................................................................. 3 PIN DESCRIPTION ................................................................................................ 4 ABSOLUTE MAXIMUM RATINGS ........................................................................ 5 RECOMMENDED OPERATING CONDITIONS ..................................................... 5 ELECTRICAL CHARACTERISTICS ..................................................................... 6 TERMINOLOGY ............................................................................................................... 7 TYPICAL PERFORMANCE ................................................................................... 7 TYPICAL POWER CONSUMPTION ................................................................................ 7 SIGNAL TIMING REQUIREMENTS ...................................................................... 8 SYSTEM CLOCK TIMING ................................................................................................ 8 AUDIO INTERFACE TIMING – MASTER MODE ............................................................ 9 AUDIO INTERFACE TIMING – SLAVE MODE .............................................................. 10 CONTROL INTERFACE TIMING – I2C MODE .............................................................. 11 CONTROL INTERFACE TIMING – SPI MODE ............................................................. 12 POWER ON RESET ...................................................................................................... 13 DEVICE DESCRIPTION ...................................................................................... 15 INTRODUCTION ............................................................................................................ 15 SOFTWARE CONTROL INTERFACE ........................................................................... 15 DIGITAL AUDIO INTERFACE ........................................................................................ 19 DIGITAL AUDIO INTERFACE CONTROL ..................................................................... 21 DIGITAL AUDIO DATA SAMPLING RATES .................................................................. 23 DAC FEATURES ............................................................................................................ 24 HARDWARE CONTROL INTERFACE .......................................................................... 28 REGISTER MAP .................................................................................................. 30 REGISTER BITS BY ADDRESS .................................................................................... 31 DIGITAL FILTER CHARACTERISTICS .............................................................. 35 TERMINOLOGY ............................................................................................................. 35 DAC FILTER RESPONSES ........................................................................................... 36 DIGITAL DE-EMPHASIS CHARACTERISTICS ............................................................. 37 RECOMMENDED EXTERNAL COMPONENTS ................................................. 38 RECOMMENDED ANALOGUE LOW PASS FILTER .................................................... 39 RELEVANT APPLICATION NOTES .............................................................................. 39 PACKAGE DIMENSIONS .................................................................................... 40 IMPORTANT NOTICE ......................................................................................... 41 ADDRESS ...................................................................................................................... 41 w PD, July 2012, Rev 4.0 2 WM8533 Production Data PIN CONFIGURATION 1 2 3 4 5 A AVDD LINEOUTR LINEOUTL CPVOUTN CPCB B AGND LINEREF VMID LINEGND CPCA SCLK/ AIFMODE1 SDA/ AIFMODE0 CIFMODE DACDAT LINEVDD CS/MUTE MCLK BCLK LRCLK DBVDD C D ORDERING INFORMATION DEVICE TEMPERATURE RANGE WM8533ECSN/R -40 to +85 C o PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE 20-ball W-CSP (Pb-free, tape and reel) MSL1 260 C o Note: Reel quantity = 5000 w PD, July 2012, Rev 4.0 3 WM8533 Production Data PIN DESCRIPTION PIN NO NAME TYPE A1 AVDD Supply Analogue supply DESCRIPTION A2 LINEOUTR Analogue Out Right line output A3 LINEOUTL Analogue Out Left line output A4 CPVOUTN Analogue Out Charge pump negative rail decoupling pin A5 CPCB Analogue Out Charge pump fly back capacitor pin B1 AGND Supply B2 LINEREF Analogue Input B3 VMID Analogue Out B4 LINEGND Supply B5 CPCA Analogue Out Analogue ground Ground feedback from output jack Analogue midrail decoupling pin Charge pump ground Charge pump fly back capacitor pin I2C SOFTWARE MODE 2 SPI SOFTWARE MODE HARDWARE MODE AIFMODE [1:0] 00 = 24-bit LJ 01 = 24-bit I2S 10 = 16-bit RJ 11 = 24-bit RJ C1 SCLK/ AIFMODE1 Digital I/O I C control interface clock input pin SPI control interface clock input pin C2 SDA/ AIFMODE0 Digital I/O I C interface data input pin SPI control interface data input pin C3 CIFMODE Digital In Tri-Level 0 = select I C control interface mode C4 DACDAT Digital In C5 LINEVDD Supply D1 CS ¯¯ / MUTE ¯¯¯¯¯ Digital In D2 MCLK Digital In Master clock D3 BCLK Digital I/O Digital audio interface bit clock D4 LRCLK Digital I/O Digital audio interface left/right clock D5 DBVDD Supply 2 2 1 = select SPI control interface mode Z = select hardware mode Digital audio interface data input Charge pump supply 2 I C address select: 0 = 0x34 1 = 0x36 SPI control interface chip select 0 = Mute enabled 1 = Mute disabled Digital interface supply (for digital audio and I2C interfaces) Note: Tri-level pins which require the ‘Z’ state to be selected should be left floating (open) w PD, July 2012, Rev 4.0 4 WM8533 Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. MIN MAX AVDD, LINEVDD, DBVDD CONDITION -0.3V +4.5V Voltage range digital inputs AGND -0.3V DBVDD +0.3V Voltage range analogue inputs AGND -0.3V AVDD +0.3V Temperature range, TA -40°C +85°C Storage temperature after soldering -65°C +150°C RECOMMENDED OPERATING CONDITIONS PARAMETER Analogue supply range Digital buffer supply range Ground MIN TYP MAX AVDD, LINEVDD SYMBOL TEST CONDITIONS 2.97 3.3 3.63 V DBVDD 1.62 3.63 V AGND, LINEGND 0 UNIT V Notes 1. Analogue grounds must always be within 0.3V of each other. 2. LINEVDD and AVDD must always be within 0.3V of each other. w PD, July 2012, Rev 4.0 5 WM8533 Production Data ELECTRICAL CHARACTERISTICS Test Conditions LINEVDD=AVDD=3.3V, DBVDD=1.8V, LINEGND=AGND=0V, TA=+25ºC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT 0dBFS 1.89 2.1 2.31 Vrms Analogue Output Output Level Load Impedance 1 Load Capacitance kΩ No external RC filter 300 pF With filter shown in Figure 36 1 µF DAC Performance Signal to Noise Ratio SNR RL = 10kΩ A-weighted 100 106 dB RL = 10kΩ Un-weighted 104 dB Dynamic Range DNR RL = 10kΩ A-weighted 106 Total Harmonic Distortion THD RL = 10kΩ -1dBFS -89 RL = 10kΩ 0dBFS -86 Power Supply Rejection Ratio (AVDD or LINEVDD) PSRR Channel Separation System Absolute Phase 100Hz 54 1kHz 54 20kHz 50 1kHz 95 20Hz to 20kHz 72 1kHz 0 Channel Level Matching dB -78 dB dB Degrees 0.1 Hardware Mute Attenuation 120 Digital Soft Mute Attenuation 100 DC Offset at LINEOUTL and LINEOUTR 0 LINEREF Rejection dB dB dB +/-1 mV 1kHz 55 dB 20kHz 37 dB Digital Logic Levels Input HIGH Level VIH Input LOW Level VIL Output HIGH Level VOH Output LOW Level VOL 0.7 DBVDD V 0.3 DBVDD IOH = 1mA 0.9 DBVDD V IOL = -1mA Input Capacitance 10 Input Leakage 0 w V 0.1 DBVDD V +/-0.9 A pF PD, July 2012, Rev 4.0 6 WM8533 Production Data TERMINOLOGY 1. 2. 3. 4. Signal-to-Noise Ratio (dB) – SNR is a measure of the difference in level between the maximum theoretical full scale output signal and the output with no input signal applied. Total Harmonic Distortion (dB) – THD is the level of the rms value of the sum of harmonic distortion products relative to the amplitude of the measured output signal. All performance measurements carried out with 20kHz low pass filter, and where noted an A-weighted filter. Failure to use such a filter will result in higher THD and lower SNR readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. Mute Attenuation – This is a measure of the difference in level between the full scale output signal and the output with mute applied. TYPICAL PERFORMANCE TYPICAL POWER CONSUMPTION Test Conditions LINEVDD=AVDD=3.3V, DBVDD=1.8V, LINEGND=AGND=0V, TA=+25°C, Slave Mode, quiescent (no signal) TEST CONDITIONS ILINEVDD IAVDD IDBVDD TOTAL (mA) (mW) (mA) (mW) (mA) (mW) (mA) (mW) No clocks applied SYS_ENA [1:0]=00 0.7 2.31 0.9 2.97 0.05 0.09 1.65 5.37 Standby SYS_ENA [1:0]=01 0.2 0.66 2.0 6.6 0.1 0.18 2.3 7.44 Playback SYS_ENA [1:0]=11 4.4 14.52 6.0 19.8 0.1 0.18 10.5 34.5 Off fs=48kHz, MCLK=256fs fs=96kHz, MCLK=256fs Standby SYS_ENA [1:0]=01 0.2 0.66 2.8 9.24 0.1 0.18 3.1 10.08 Playback SYS_ENA [1:0]=11 4.9 16.17 8.5 28.05 0.1 0.18 13.5 44.4 fs=192kHz, MCLK=128fs Standby SYS_ENA [1:0]=01 0.2 0.66 2.8 9.24 0.1 0.18 3.1 10.08 Playback SYS_ENA [1:0]=11 4.9 16.17 8.5 28.05 0.1 0.18 13.5 44.4 w PD, July 2012, Rev 4.0 7 WM8533 Production Data SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING Figure 1 System Clock Timing Requirements Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN MCLK cycle time tMCLKY 27 MCLK high time tMCLKH 11 MCLK low time tMCLKL 11 TYP MAX UNIT 500 ns Master Clock Timing Information MCLK duty cycle (tMCLKH/tMCLKL) w 40:60 ns ns 60:40 % PD, July 2012, Rev 4.0 8 WM8533 Production Data AUDIO INTERFACE TIMING – MASTER MODE Figure 2 Master Mode Digital Audio Data Timing Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT 16 ns Audio Data Input Timing Information LRCLK propagation delay from BCLK falling edge tDL 4 DACDAT setup time to BCLK rising edge tDST 22 ns DACDAT hold time from BCLK rising edge tDHT 25 ns Table 1 Master Mode Audio Interface Timing w PD, July 2012, Rev 4.0 9 WM8533 Production Data AUDIO INTERFACE TIMING – SLAVE MODE Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 27 ns BCLK pulse width high tBCH 11 ns BCLK pulse width low tBCL 11 ns LRCLK set-up time to BCLK rising edge tLRSU 7 ns LRCLK hold time from BCLK rising edge tLRH 5 ns DACDAT hold time from BCLK rising edge tDH 5 ns DACDAT set-up time to BCLK rising edge tDS 7 ns Table 2 Slave Mode Audio Interface Timing Note: BCLK period should always be greater than or equal to MCLK period. w PD, July 2012, Rev 4.0 10 WM8533 Production Data 2 CONTROL INTERFACE TIMING – I C MODE 2 I C mode is selected by driving the CIFMODE pin low. 2 Figure 4 Control Interface Timing – I C Control Mode Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT SCLK Low Pulse-Width t1 100 400 kHz ns SCLK High Pulse-Width t2 100 ns Hold Time (Start Condition) t3 600 ns Setup Time (Start Condition) t4 600 ns Data Setup Time t5 100 SDA, SCLK Rise Time (see Note) t6 SDA, SCLK Fall Time t7 Setup Time (Stop Condition) t8 Data Hold Time t9 Program Register Input Information SCLK Frequency Pulse width of spikes that will be suppressed ns 300 ns 300 ns 900 ns 8 ns 600 2 ns 2 Table 3 Control Interface Timing – I C Control Mode Note: When SCLK frequency ≤ 100kHz, the maximum rise time for SDA and SCLK is increased to 1000ns. w PD, July 2012, Rev 4.0 11 WM8533 Production Data CONTROL INTERFACE TIMING – SPI MODE SPI mode is selected by connecting the CIFMODE pin high. Figure 5 Control Interface Timing – SPI Control Mode Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information ¯¯ falling edge SCLK rising edge to CS tCSU 40 ns ¯¯ rising edge SCLK falling edge to CS tCHO 40 ns SCLK pulse cycle time tSCY 160 ns SCLK pulse width low tSCL 64 ns SCLK pulse width high tSCH 64 ns SDA to SCLK set-up time tDSU 20 ns SDA to SCLK hold time tDHO 40 tps 2 Pulse width of spikes that will be suppressed ns 8 ns Table 4 Control Interface Timing –SPI Control Mode w PD, July 2012, Rev 4.0 12 WM8533 Production Data POWER ON RESET Figure 6 Internal Power on Reset Circuit Schematic The WM8533 includes an internal Power-On-Reset circuit, as shown in Figure 6, which is used to reset the DAC digital logic into a default state after power up. The POR circuit is powered by AVDD and has as its inputs VMID and LINEVDD. It asserts POR low if VMID or LINEVDD are below a minimum threshold. Figure 7 Typical Power Timing Requirements Figure 7 shows a typical power-up sequence where LINEVDD comes up with AVDD. When AVDD goes above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee POR is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. After VMID rises to Vpord_hi and AVDD rises to Vpora_hi, POR is released high and all registers are in their default state and writes to the control interface may take place. On power down, POR is asserted low whenever LINEVDD or AVDD drop below the minimum threshold Vpora_low. w PD, July 2012, Rev 4.0 13 WM8533 Production Data Test Conditions LINEVDD = AVDD = 3.3V, DBVDD = 1.8V, AGND = LINEGND = 0V, TA = +25ºC PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Power Supply Input Timing Information VDD level to POR defined (LINEVDD/AVDD rising) Vpora Measured from LINEGND VDD level to POR rising edge (VMID rising) Vpord_hi Measured from LINEGND 0.63 0.8 1 V VDD level to POR rising edge (LINEVDD/AVDD rising) Vpora_hi Measured from LINEGND 1.44 1.8 2.18 V VDD level to POR falling edge (LINEVDD/AVDD falling) Vpora_lo Measured from LINEGND 0.96 1.46 1.97 V 158 mV Table 5 Power on Reset Note: All values are simulated results w PD, July 2012, Rev 4.0 14 WM8533 Production Data DEVICE DESCRIPTION INTRODUCTION The WM8533 provides high fidelity, 2Vrms ground referenced stereo line output from a single supply line with minimal external components. The integrated DC servo eliminates the requirement for external mute circuitry by minimising DC transients at the output during power up/down. The device is well-suited to both stereo and multi-channel systems. The device supports all common audio sampling rates between 8kHz and 192kHz using common MCLK / fs ratios. Master and slave modes are available. The WM8533 supports both hardware and software control modes. In hardware control mode, the digital audio interface format is switchable between 16 to 24bits LJ, RJ 2 and I S, and a mute control pin is also available. In software control modes, the digital audio interface is fully programmable, with two control interface addresses to allow multiple WM8533 devices to be configured independently. SOFTWARE CONTROL INTERFACE Software control mode is selected by logic 1 or 0 on the CIFMODE pin. The logic level is referenced to the DBVDD power domain. When software mode is selected, the associated multi-function control pins are defined as described in Table 6. PIN NAME PIN REF DESCRIPTION SDA C2 Serial Data Input SCLK C1 Serial Data Clock CS ¯¯ D1 I C Mode - Device Address SPI Mode - Chip Select CIFMODE C3 Control Interface Mode 2 0 = I C Mode 1 = SPI Mode Z = Hardware Mode 2 Table 6 Software Control Pin Configuration In software control mode, the WM8533 is controlled by writing to its control registers. Readback is 2 available for all registers, including device ID and power management status bits, in I C control mode 2 only. The control interface can operate as an I C or SPI control interface: register read-back is 2 provided on the bi-directional pin SDA in I C mode. Note that Readback is not available in SPI mode. The WM8533 software control interface is supplied by the DBVDD power domain. The available software control interface modes are summarised as follows: 2 I C mode uses pins SCLK and SDA. SPI mode uses pins CS ¯¯ , SCLK and SDA. 2 I C mode is selected by setting the CIFMODE pin to logic 0. SPI mode is selected by setting the CIFMODE pin to logic 1. w PD, July 2012, Rev 4.0 15 WM8533 Production Data 2 I C CONTROL MODE 2 In I C mode, the WM8533 is a slave device on the control interface; SCLK is a clock input, while SDA is a bi-directional data pin. To allow arbitration of multiple slaves (and/or multiple masters) on the same interface, the WM8533 transmits logic 1 by tri-stating the SDA pin, rather than pulling it high. An external pull-up resistor is required to pull the SDA line high so that the logic 1 can be recognised by the master. 2 In order to allow many devices to share a single I C control bus, every device on the bus has a unique 8-bit device ID (this is not the same as the 8-bit address of each register in the WM8533). ¯¯ pin as shown in Table 7. The LSB of the The device ID is determined by the logic level on the CS device ID is the R/W ¯¯ bit; this bit is set to logic 1 for “Read” and logic 0 for “Write”. ¯¯ CS DEVICE ID 0 0011 0100 (34h) 1 0011 0110 (36h) Table 7 Control Interface Device ID Selection 2 The WM8533 operates as an I C slave device only. The controller indicates the start of data transfer with a high to low transition on SDA while SCLK remains high. This indicates that a device ID, register address and data will follow. The WM8533 responds to the start condition and shift in the next eight bits on SDA (8-bit device ID, including Read/Write bit, MSB first). If the device ID received matches the device address of the WM8533, then the WM8533 responds by pulling SDA low on the next clock pulse (ACK). If the device ID is not recognised or the R/W ¯¯ bit is set incorrectly, the WM8533 returns to the idle condition and waits for a new start condition and valid address. If the device ID matches the device ID of the WM8533, the data transfer continues as described below. The controller indicates the end of data transfer with a low to high transition on SDA while SCLK remains high. After receiving a complete address and data sequence the WM8533 returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e. SDA changes while SCLK is high), the device returns to the idle condition. The WM8533 supports the following read and write operations: Single write Single read The sequence of signals associated with a single register write operation is illustrated in Figure 8. 2 Figure 8 Control Interface I C Register Write The sequence of signals associated with a single register read operation is illustrated in Figure 9. 2 Figure 9 Control Interface I C Register Read w PD, July 2012, Rev 4.0 16 WM8533 Production Data Figure 10 Single Register Write to Specified Address Figure 11 Single Register Read from Specified Address SPI CONTROL MODE The WM8533 can also be controlled by writing to registers through a SPI control interface. A control word consists of 24 bits. The first bit is the read/write bit (R/W ¯¯) which must always be 0, which is followed by 7 address bits (A6 to A0) that determine which control register is accessed. The remaining 16 bits (B15 to B0) are data bits, corresponding to the 16 bits in each control register. Volume update registers R06h and R07h are unavailable in SPI control mode. To use volume update 2 in software control mode, I C mode must be used. In SPI mode, every rising edge of SCLK clocks in one data bit from the SDA pin. A rising edge on CS ¯¯ latches in a complete control word consisting of the last 24 bits. The SPI mode write operation protocol is illustrated in Figure 12. Figure 12 SPI Control Interface – Write operation In Write operations (R/W ¯¯=0), all SDA bits are driven by the controlling device. w PD, July 2012, Rev 4.0 17 WM8533 Production Data REGISTER RESET Any write to register R0 (00h) will reset the WM8533. All register bits are reset to their default values. CHIP ID AND REVISION Reading from register R0 (00h) returns the Chip ID. Reading from register R1 returns the Chip revision number. REGISTER ADDRESS BIT LABEL DEFAULT R0 (00h) DEVICE_ID 15:0 CHIP_ID [15:0] 8523h R1 (01h) REVISION 2:0 CHIP_REV [2:0] 001 DESCRIPTION Chip ID Writing to this register resets all registers to their default state. Reading from this register will indicate the Chip ID 8523h. Chip Revision Indicates the Chip Revision number Table 8 Chip ID and Revision Number w PD, July 2012, Rev 4.0 18 WM8533 Production Data DIGITAL AUDIO INTERFACE The digital audio interface is used for inputting audio data to the WM8533. The digital audio interface uses three pins: DACDAT: DAC data input LRCLK: Left/Right data alignment clock BCLK: Bit clock, for synchronisation MASTER AND SLAVE MODE OPERATION The WM8533 digital audio interface can operate as a master or as a slave as shown in Figure 13 and Figure 14. Figure 13 Slave Mode Figure 14 Master Mode INTERFACE FORMATS The WM8533 supports five different audio data formats: Left justified Right justified I2S DSP Mode A DSP Mode B PCM operation is supported using the DSP mode. All of these modes are MSB first. They are described in the following sections. Refer to the “Signal Timing Requirements” section for timing information. Refer to Table 10 for interface control format register settings. AUDIO DATA FORMATS In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition. Figure 15 Right Justified Audio Interface (assuming n-bit word length) w PD, July 2012, Rev 4.0 19 WM8533 Production Data In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition. Figure 16 Left Justified Audio Interface (assuming n-bit word length) 2 In I S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next. 2 Figure 17 I S Justified Audio Interface (assuming n-bit word length) st nd In DSP mode, the left channel MSB is available on either the 1 (mode B) or 2 (mode A) rising edge of BCLK (selectable by AIF_LRCLK_INV) following a rising edge of LRCLK. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. In device master mode, the LRCLK output will resemble the frame pulse shown in Figure 18 and Figure 19. In device slave mode, Figure 20 and Figure 21, it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period before the rising edge of the next frame pulse. Figure 18 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Master) w PD, July 2012, Rev 4.0 20 WM8533 Production Data Figure 19 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Master) Figure 20 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Slave) Figure 21 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Slave) DIGITAL AUDIO INTERFACE CONTROL The control of the audio interface in software mode is achieved by register write. Dynamically changing the audio data format may cause erroneous operation and is not recommended. Digital audio data is transferred to the WM8533 via the digital audio interface. The DAC operates in master or slave mode. The DAC audio interface requires left/right frame clock (LRCLK) and bit clock (BCLK). These can be supplied externally (slave mode) or they can be generated internally (master mode). Selection of master and slave mode is achieved by setting AIF_MSTR bit in Register 3. The frequency of LRCLK in master mode is dependent upon the DAC master clock frequency and the AIF_SR [2:0] bits. The frequency of BCLK in master mode can be selected by AIF_BCLKDIV [2:0]. In slave mode, the MCLK to LRCLK ratio can be auto-detected or set manually using the AIF_SR [2:0] bits. w PD, July 2012, Rev 4.0 21 WM8533 Production Data REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3 (03h) AIF_CTRL1 7 AIF_MSTR 0 R4 (04h) AIF_CTRL2 5:3 AIF_BCLKD IV [2:0] 000 BCLK Divider Control (Master Mode) 000 = MCLK/4 001 = MCLK/8 010 = 32fs 011 = 64fs 100 = 128fs 101 to 111 = Reserved 2:0 AIF_SR [2:0] 000 MCLK:LRCLK Ratio 000 = Auto detect 001 = 128fs 010 = 192fs 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = 1152fs Master/Slave Select 0 = Slave 1 = Master Table 9 DAC Clocking Mode Control Interface timing is such that the input data and left/right clock are sampled on the rising edge of BCLK. By setting the appropriate BCLK and LRCLK polarity bits, the WM8533 DAC can sample data on the opposite clock edges. The control of audio interface formats and clock polarities is summarised in Table 10. REGISTER ADDRESS R3 (03h) AIF_CTRL1 BIT LABEL DEFAULT DESCRIPTION 6 AIF_LRCLK _INV 0 LRCLK Inversion Control 0 = Normal polarity 1 = Inverted polarity When AIF_FMT [1:0]=11 (DSP Mode): 0 = Mode A (2nd clock) 1 = Mode B (1st clock) 5 AIF_BCLK_ INV 0 BCLK Inversion Control Slave mode: 0 = use rising edge 1 = use falling edge Master mode: 0 = BCLK normal 1 = BCLK inverted 4:3 AIF_WL [1:0] 10 Audio Data Word Length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits 1:0 AIF_FMT [1:0] 10 Audio Data Interface Format 00 = Right justified 01 = Left justified 10 = I2S format 11 = DSP mode Table 10 Audio Interface Control w PD, July 2012, Rev 4.0 22 WM8533 Production Data DIGITAL AUDIO DATA SAMPLING RATES The external master clock is applied directly to the MCLK input pin. In a system where there are a number of possible sources for the reference clock, it is recommended that the clock source with the lowest jitter be used for the master clock to optimise the performance of the WM8533. In slave mode the WM8533 has a detection circuit that automatically determines the relationship between the master clock frequency (MCLK) and the sampling rate (LRCLK), to within ±32 system clock periods. The MCLK must be synchronised with the LRCLK, although the device is tolerant of phase variations or jitter on the MCLK. If the device is configured in slave mode using auto-detect or in hardware mode, and during sample rate change the ratio between MCLK and LRCLK varies more than once within 1026 LRCLK periods, then it is recommended that the device be taken into the standby state or the off state before the sample rate change and held in standby until the sample rate change is complete. This will ensure correct operation of the detection circuit on the return to the enabled state. For details on the standby state, please refer to the “Software Control Interface” (software mode, page 15) and “Power Up and Down Control In Hardware Mode” sections of the datasheet (hardware mode, on page 29). The DAC supports MCLK to LRCLK ratios of 128fs to 1152fs and sampling rates of 8kHz to 192kHz, provided the internal signal processing of the DAC is programmed to operate at the correct rate. Table 11 shows typical master clock frequencies and sampling rates supported by the WM8533 DAC. SAMPLE RATE (LRCLK) MASTER CLOCK (MCLK) FREQUENCY (MHz) 8kHz 128fs Unavailable 192fs Unavailable 256fs 2.048 384fs 3.072 512fs 4.096 768fs 6.144 1152fs 9.216 32kHz Unavailable Unavailable 8.192 12.288 16.384 24.576 36.864 44.1kHz Unavailable Unavailable 11.2896 16.9344 22.5792 33.8688 Unavailable 48kHz Unavailable Unavailable 12.288 18.432 24.576 36.864 Unavailable 88.2kHz 11.2896 16.9344 22.5792 33.8688 Unavailable Unavailable Unavailable 96kHz 12.288 18.432 24.576 36.864 Unavailable Unavailable Unavailable 176.4kHz 22.5792 33.8688 Unavailable Unavailable Unavailable Unavailable Unavailable 192kHz 24.576 36.864 Unavailable Unavailable Unavailable Unavailable Unavailable Table 11 MCLK Frequencies and Audio Sample Rates w PD, July 2012, Rev 4.0 23 WM8533 Production Data DAC FEATURES SYSTEM ENABLE The WM8533 includes a number of enable and disable mechanisms to allow the device to be powered on and off in a pop-free manner. The SYS_ENA [1:0] control bits enable the DAC and analogue paths. REGISTER ADDRESS R2 (02h) PSCTRL1 BIT LABEL DEFAULT 1:0 SYS_ENA [1:0] 00 DESCRIPTION System Power Control 00 = Off 01 = Power down 10 = Power up (Digital Soft Mute) 11 = Power up (un-muted) Table 12 System Enable Control Note: MCLK must be present at all times when using the SYS_ENA [1:0] bits. If MCLK is stopped at any point the device will power down to the ‘off’ state, but all register settings will remain. Restarting MCLK will start the device internal power sequence and the device will return to the power state set by the SYS_ENA [1:0] bits. The power up and power down sequences are summarised in Figure 22. There is no requirement to manually cycle the device through the sequence via register writes, as the device will always automatically step through each stage in the sequence. Power Up When SYS_ENA [1:0]=00, the internal clocks are stopped and all analogue and digital blocks are disabled for maximum power saving. The device starts up in this state in software mode. Setting SYS_ENA [1:0]=01 enables the internal charge pump and required control circuitry, but the signal path remains powered down. When SYS_ENA [1:0]=10 all blocks are powered up sequentially and full system configuration is achieved. Once this is complete, the device is ready to pass audio but is muted with a digital soft mute. Setting SYS_ENA [1:0]=11 releases the digital soft mute and audio playback begins. Power Down When SYS_ENA [1:0]=11 the device is powered up and passing audio. Changing SYS_ENA [1:0]=10 applies a digital soft mute to the output, with attenuation of 100dB on the input signal. Setting SYS_ENA [1:0]=01 sequentially powers down all circuit blocks but leaves the charge pump and required control circuitry enabled. This state is equivalent to the Hardware Mode mute state, and will give 120dB attenuation on the input signal. This can be considered the low-power standby state. Finally, setting SYS_ENA [1:0]=00 will disable all circuit blocks including the charge pump, and full system initialisation will be required to restart the device. Figure 22 SYS_ENA [1:0] Power Up and Down Sequences w PD, July 2012, Rev 4.0 24 WM8533 Production Data DIGITAL VOLUME CONTROL The WM8533 DAC includes digital volume control, allowing the digital gain to be adjusted between −100dB and +12dB in 0.25dB steps. Volume update bits allow the user to write both left and right channel volume changes before the volume is updated. 2 Note that digital volume control is only available in I C mode. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R6 (06h) DAC_GAINL 9 DACL_VU 0 R7 (07h) DAC_GAINR 9 DACR_VU 0 DAC Digital Volume Update 0 = Latch DAC volume setting into Register Map but do not update volume 1 = Latch DAC volume setting into Register Map and update left and right channels simultaneously R6 (06h) DAC_GAINL 8:0 DACL_VOL [8:0] 190h R7 (07h) DAC_GAINR 8:0 DACR_VOL [8:0] 190h DAC Digital Volume 000h = −100dB 001h = −99.75dB 002h = −99.5dB …0.25dB steps 190h = 0dB …0.25dB steps 1BEh = +11.75dB 1BFh to 1FFh = +12dB Table 13 DAC Digital Volume Control VOLUME CHANGE MODES Volume can be adjusted by step change (either using zero cross or not) or by soft ramp. The volume change mode is controlled by the DAC_VOL_DOWN_RAMP and DAC_VOL_UP_RAMP bits in R5: REGISTER ADDRESS R5 (05h) DAC_CTRL3 BIT LABEL DEFAULT DESCRIPTION 1 DAC_VOL _UP_RAM P 0 DAC Digital Volume Increase Control 0 = Apply volume increases instantly (step) 1 = Ramp volume increases 0 DAC_VOL _DOWN_ RAMP 1 DAC Digital Volume Decrease Control 0 = Apply volume decreases instantly (step) 1 = Ramp volume decreases Table 14 Volume Ramp Control w PD, July 2012, Rev 4.0 25 WM8533 Production Data The effect of the volume ramp is illustrated in Figure 23. Figure 23 Volume Ramp Functionality Ramp Volume Changes If ramp volume changes are selected, the ramp rate is dependent upon the sampling rate. The ramp rates for common audio sample rates are shown in Table 15. SAMPLE RATE FOR DAC (kHz) GAIN RAMP RATE 8 (ms/dB) 1 32 0.25 44.1 0.18 48 0.17 88.2 0.1 96 0.08 176.4 0.05 192 0.04 Table 15 Volume Ramp Rate For example, when using a sample rate of 48kHz, the time taken for a volume change from an initial setting of 0dB to -20dB is calculated as follows: Volume Change (dB) x Volume Ramp Rate (ms/dB) = 20 x 0.17 = 3.4ms Zero cross is not used when ramping. The volume level in the DAC is set by the user in 0.25dB increments, but during the volume ramp increments of 0.125dB are actually used. This step size is inaudible and means there is no requirement to wait until a zero crossing occurs. Another benefit of not using zero cross when ramping is that predictable ramp times are produced – there is no signal dependency on the ramp time. w PD, July 2012, Rev 4.0 26 WM8533 Production Data Step Volume Changes and Zero Cross The step volume control includes optional zero cross functionality. When zero cross is enabled, by setting DAC_ZC=1, volume changes are not applied until the signal crosses zero so no discontinuity is seen in the output signal. Zero cross helps to prevent pop and click noise when changing volume settings and is therefore recommended if using step volume changes. The zero cross function includes a timeout which forces volume changes if a zero cross event does not occur. The timeout period is 14400 samples, equivalent to 300ms at 48kHz sample rate. REGISTER ADDRESS R5 (05h) DAC_CTRL3 BIT LABEL DEFAULT 4 DAC_ZC 0 DESCRIPTION Zero Cross Enable 0 = Do not use zero cross 1 = Use zero cross Table 16 Zero Cross Control Table 17 gives a summary of the volume mode settings and their effect. DAC_VOL_ UP_RAMP DAC_VOL_ DOWN_RAMP DAC_ZC VOLUME CHANGE UP VOLUME CHANGE DOWN 0 0 0 Step, no zero cross Step, no zero cross 0 1 0 Step, no zero cross Ramp 1 0 0 Ramp Step, no zero cross 1 1 0 Ramp Ramp 0 0 1 Step, use zero cross Step, use zero cross 0 1 1 Step, use zero cross Ramp 1 0 1 Ramp Step, use zero cross 1 1 1 Ramp Ramp Table 17 Volume Change Summary MUTE A digital mute can be applied to left and right channels independently. REGISTER ADDRESS R5 (05h) DAC_CTRL3 BIT LABEL DEFAULT DESCRIPTION 3 DACR_MU TE 0 Right DAC Mute 0 = Normal operation 1 = Mute 2 DACL_MUT E 0 Left DAC Mute 0 = Normal operation 1 = Mute Table 18 DAC Mute Control The DAC mute function in software mode is controlled by the register settings DAC_VOL_UP_RAMP, DAC_VOL_DOWN_RAMP and DAC_ZC as described in Table 17. w PD, July 2012, Rev 4.0 27 WM8533 Production Data DIGITAL MONOMIX CONTROL The DAC can be set to output a range of mono and stereo options using DAC_OP_MUX [1:0]. REGISTER ADDRESS R4 (04h) AIF_CTRL2 BIT LABEL DEFAULT 7:6 DAC_OP_ MUX [1:0] 00 DESCRIPTION DAC Digital Monomix 00 = Stereo (Normal Operation) 01 = Mono (Left data to DACR) 10 = Mono (Right data to DACL) 11 = Digital Monomix, (L+R)/2 Table 19 Digital Monomix Control DE-EMPHASIS A digital de-emphasis filter may be applied to the DAC output when the sampling frequency is 44.1kHz. Operation at 48kHz and 32kHz is also possible, but with an increase in the error from the ideal response. Details of the de-emphasis filter characteristic for 32kHz, 44.1kHz and 48kHz can be seen in Figure 29 to Figure 34. REGISTER ADDRESS R3 (03h) AIF_CTRL1 BIT LABEL DEFAULT 8 DAC_DEE MP 0 DESCRIPTION DAC De-emphasis 0 = No de-emphasis 1 = Apply de-emphasis Table 20 De-emphasis Control HARDWARE CONTROL INTERFACE The WM8533 can be controlled in hardware mode or in software modes. In hardware mode, the device is configured according to logic levels applied to hardware pins. Hardware control mode is selected by leaving CIFMODE pin open-circuit (high-impedance). When hardware mode is selected, the associated multi-function control pins are defined as described in Table 21. PIN NAME DESCRIPTION AIFMODE0 / AIFMODE1 AIFMODE1 0 0 1 1 AIFMODE0 0 1 0 1 MUTE ¯¯¯¯¯ Mute Control 0 = Mute 1 = Normal operation CIFMODE Control Interface Mode 2 0 = I C Mode 1 = SPI Mode Z = Hardware Mode FORMAT 24-bit Left Justified 2 24-bit I S 16-bit Right Justified 24-bit Right Justified Table 21 Hardware Control Pin Configuration MUTE In hardware mode, the MUTE ¯¯¯¯¯ pin controls the DAC mute to both left and right channels. When the mute is asserted a softmute is applied to ramp the signal down, with the ramp rate related to the sample rate as defined in Table 15 on page 26. When the mute is de-asserted the DAC output returns to normal in one step. w PD, July 2012, Rev 4.0 28 WM8533 Production Data POWER UP AND DOWN CONTROL IN HARDWARE MODE In hardware mode the MCLK, BCLK and MUTE ¯¯¯¯¯ pins are monitored to control how the device powers up or down, and this is summarised in Figure 24 below. Figure 24 Hardware Power Sequence Diagram Off to Enable To power up the device to enabled, start MCLK and BCLK and set MUTE ¯¯¯¯¯ = 1. Off to Standby To power up the device to standby, start MCLK and BCLK and set MUTE ¯¯¯¯¯ = 0. Once the device is in standby mode, BCLK can be disabled and the device will remain in standby mode. Standby to Enable To transition from the standby state to the enabled state, set the MUTE ¯¯¯¯¯ pin to logic 1 and start BCLK. Enable to Standby To power down to a standby state leaving the charge pump running, either set the MUTE ¯¯¯¯¯ pin to logic 0 or stop BCLK. MCLK must continue to run in these situations. The device will automatically mute and power down quietly in either case. Note: It is recommended that the device is placed in standby mode before sample rate change if the sample rate changes more than once in 1026 LRCLK periods, as detailed in “Digital Audio Data Sampling Rates” on page 23. Enable to Off To power down the device completely, stop MCLK at any time. It is recommended that the device is placed into standby mode as described above before stopping MCLK to allow a quiet shutdown. For the timing of the off state to enabled state transition (power on to audio out timing), and the enabled state to standby state transition (the shutdown timing), please refer to WTN0302. w PD, July 2012, Rev 4.0 29 WM8533 REGISTER MAP Production Data The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8533 can be configured using the Control Interface. All unused bits should be set to '0' and access to unlisted registers should be avoided. REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R0 (0h) DEVICE_ID / SW RESET R1 (1h) REVISION 0 0 0 0 0 0 0 0 0 0 0 0 0 R2 (2h) PSCTRL1 0 0 0 0 0 0 0 0 0 0 0 0 0 R3 (3h) AIF_CTRL1 0 0 0 0 0 0 0 R4 (4h) AIF_CTRL2 0 0 0 0 0 0 0 0 R5 (5h) DAC_CTRL3 0 0 0 0 0 0 0 0 R6 (6h) DAC_GAINL 0 0 0 0 0 0 DACL_ VU DACL_VOL [8:0] 0190h R7 (7h) DAC_GAINR 0 0 0 0 0 0 DACR _VU DACR_VOL [8:0] 0190h CHIP_ID [15:0] 8523h DAC_ AIF_L AIF_B AIF_M DEEM RCLK_ CLK_I STR P INV NV DAC_OP_MUX [1:0] 0 0 AIF_WL [1:0] AIF_BCLKDIV [2:0] 0 CHIP_REV [2:0] 0001h 0 SYS_ENA [1:0] 0000h 0 AIF_FMT [1:0] 1812h AIF_SR [2:0] DAC_ DAC_ DACR DAC_ DACL_ VOL_ VOL_D _MUT ZC MUTE UP_R OWN_ E AMP RAMP 0000h 0001h Table 22 Register Map w PD, July 2012, Rev 4.0 30 WM8533 Production Data REGISTER BITS BY ADDRESS REGISTER ADDRESS BIT R0 (00h) DEVICE_ID/ SW RESET 15:0 LABEL DEFAULT DESCRIPTION REFER TO CHIP_ID [15:0] 1000_0101_0010_0011 Chip ID Writing to this register resets all registers to their default state. Reading from this register will indicate the Chip ID 8523h. Page 18 Register 00h DEVICE_ID / SW RESET REGISTER ADDRESS BIT LABEL DEFAULT R1 (01h) REVISION 2:0 CHIP_REV [2:0] 001 DESCRIPTION Chip Revision Indicates the Chip Revision number REFER TO Page 18 Register 01h REVISION REGISTER ADDRESS BIT LABEL DEFAULT R2 (02h) PSCTRL1 1:0 SYS_ENA [1:0] 00 DESCRIPTION System Power Control 00 = Off 01 = Power down 10 = Power up (muted) 11 = Power up (unmuted) REFER TO Page 24 Register 02h PSCTRL1 w PD, July 2012, Rev 4.0 31 WM8533 Production Data REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3 (03h) AIF_CTRL1 8 DAC_DEEMP 0 DAC De-emphasis Control 0 = No de-emphasis 1 = De-emphasis enabled Page 28 7 AIF_MSTR 0 Master/Slave Select 0 = Slave mode 1 = Master mode Page 21 6 AIF_LRCLK_INV 0 LRCLK Inversion Control 0 = Normal polarity 1 = Inverted polarity When AIF_FMT [1:0]=11 (DSP Mode): 0 = Mode A (2nd clock) 1 = Mode B (1st clock) Page 21 5 AIF_BCLK_INV 0 BCLK Inversion Control Slave mode: 0 = Use rising edge 1 = Use falling edge Master mode: 0 = BCLK normal 1 = BCLK inverted Page 21 4:3 AIF_WL [1:0] 10 Audio Data Word Length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits Page 21 2 Reserved 0 Reserved 2:0 AIF_FMT [1:0] 10 Audio Data Interface Format 00 = Right justified 01 = Left justified 2 10 = I S format 11 = DSP mode REFER TO Page 21 Register 03h AIF_CTRL1 w PD, July 2012, Rev 4.0 32 WM8533 Production Data REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R4 (04h) AIF_CTRL2 7:6 DAC_OP_MUX [1:0] 00 Digital Monomix Control 00 = Stereo (Normal operation) 01 = Mono (Left data to DACR) 10 = Mono (Right data to DACL) 11 = Digital Monomix, (L+R)/2 Page 28 5:3 AIF_BCLKDIV [2:0] 000 BCLK Divider Control (Master Mode) 000 = MCLK/4 001 = MCLK/8 010 = 32fs 011 = 64fs 100 = 128fs 101 to 111 = Reserved Page 21 2:0 AIF_SR [2:0] 000 MCLK:LRCLK Ratio 000 = Auto detect 001 = 128fs 010 = 192fs 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = 1152fs Page 21 Register 04h AIF_CTRL2 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R5 (05h) DAC_CTRL3 4 DAC_ZC 0 Zero Cross Enable 0 = Do not use zero cross 1 = Use zero cross Page 25 3 DACR_MUTE 0 Right DAC Mute 0 = Normal operation 1 = Mute Page 27 2 DACL_MUTE 0 Left DAC Mute 0 = Normal operation 1 = Mute Page 27 1 DAC_VOL_ UP_RAMP 0 DAC Digital Volume Increase Control 0 = Apply volume increases instantly (step) 1 = Ramp volume increases Page 25 0 DAC_VOL_ DOWN_RAMP 1 DAC Digital Volume Decrease Control 0 = Apply volume decreases instantly (step) 1 = Ramp volume decreases Page 25 Register 05h DAC_CTRL3 w PD, July 2012, Rev 4.0 33 WM8533 Production Data REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R6 (06h) DAC_GAINL 9 DACL_VU 0 Left DAC Digital Volume Update 0 = Latch Left DAC volume setting into register map but do not update volume 1 = Latch Left DAC volume setting into register map and update left and right channels simultaneously Page 25 8:0 DACL_VOL [8:0] 1_1001_0000 Left DAC Digital Volume Control 000h = -100dB 001h = -99.75dB 002h = -99.5dB …0.25dB steps 190h = 0dB …0.25dB steps 1BEh = +11.75dB 1BFh to 1FFh = +12dB Page 25 Register 06h DAC_GAINL REGISTER ADDRESS BIT LABEL DEFAULT R7 (07h) DAC_GAINR 9 DACR_VU 0 8:0 DACR_VOL [8:0] DESCRIPTION REFER TO Right DAC Digital Volume Update 0 = Latch Right DAC volume setting into register map but do not update volume 1 = Latch Right DAC volume setting into register map and update left and right channels simultaneously 1_1001_0000 Right DAC Digital Volume Control 000h = -100dB 001h = -99.75dB 002h = -99.5dB …0.25dB steps 190h = 0dB …0.25dB steps 1BEh = +11.75dB 1BFh to 1FFh = +12dB Page 25 Page 25 Register 07h DAC_GAINR w PD, July 2012, Rev 4.0 34 WM8533 Production Data DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS DAC Filter – 256fs to 1152fs Passband MIN TYP 0.1dB 0.1 Stopband -50 dB 14.5fs 0.1dB 0.247fs Passband Ripple 0.1 Stopband Stopband attenuation Group Delay dB 0.546fs f > 0.546fs Group Delay DAC Filter – 128fs and 192fs Passband UNIT 0.454fs Passband Ripple Stopband attenuation MAX dB 0.753fs f > 0.753fs -50 dB 6.5fs TERMINOLOGY 1. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band) 2. Pass-band Ripple – any variation of the frequency response in the pass-band region w PD, July 2012, Rev 4.0 35 WM8533 Production Data DAC FILTER RESPONSES 0.2 0 0.15 0.1 Response (dB) Response (dB) -20 -40 -60 0.05 0 -0.05 -0.1 -80 -0.15 -100 -0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Frequency (Fs) -120 0 0.5 1 1.5 2 2.5 3 Frequency (Fs) Figure 25 DAC Digital Filter Frequency Response Figure 26 DAC Digital Filter Ripple – 256fs to 1152fs Clock – 256fs to 1152fs Clock Modes Modes 0.2 0 0 Response (dB) Response (dB) -20 -40 -60 -0.2 -0.4 -0.6 -0.8 -80 -1 0 -100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Frequency (Fs) 1 Frequency (Fs) Figure 27 DAC Digital Filter Frequency Response – 128fs and 192fs Clock Modes w Figure 28 DAC Digital Filter Ripple – 128fs to 192fs Clock Modes PD, July 2012, Rev 4.0 36 WM8533 Production Data DIGITAL DE-EMPHASIS CHARACTERISTICS 0 1 0.5 -2 Response (dB) Response (dB) 0 -4 -6 -0.5 -1 -1.5 -2 -8 -2.5 -10 -3 0 2 4 6 8 10 Frequency (kHz) 12 14 16 0 2 4 6 8 10 Frequency (kHz) Figure 29 De-Emphasis Frequency Response (32kHz) Figure 30 De-Emphasis Error (32kHz) Figure 31 De-Emphasis Frequency Response (44.1kHz) Figure 32 De-Emphasis Error (44.1kHz) 0 12 14 16 1 0.8 -2 0.6 Response (dB) Response (dB) 0.4 -4 -6 0.2 0 -0.2 -0.4 -8 -0.6 -0.8 -10 -1 0 5 10 15 Frequency (kHz) 20 Figure 33 De-Emphasis Frequency Response (48kHz) w 0 5 10 15 Frequency (kHz) 20 Figure 34 De-Emphasis Error (48kHz) PD, July 2012, Rev 4.0 37 WM8533 Production Data RECOMMENDED EXTERNAL COMPONENTS Figure 35 Recommended External Components Notes: 1. Wolfson recommend using a single, common ground plane. Where this is not possible, care should be taken to optimise split ground configuration for audio performance. 2. Charge Pump fly-back capacitor C5 should be placed as close to WM8533 as possible, followed by Charge Pump decoupling capacitor C1, then LINEVDD and VMID decoupling capacitors. 3. Capacitor types should be chosen carefully. Capacitors with very low ESR are recommended for optimum performance. w PD, July 2012, Rev 4.0 38 WM8533 Production Data RECOMMENDED ANALOGUE LOW PASS FILTER Figure 36 Recommended Analogue Low Pass Filter (one channel shown) An external single-pole RC filter is recommended if the device is driving a wideband amplifier. Other filter architectures may provide equally good results. The filter shown in Figure 36 has a -3dB cut-off at 105.26kHz and a droop of 0.15dB at 20kHz. The typical output from the WM8533 is 2.1Vrms – when a 10kΩ load is placed at the output of this recommended filter the amplitude across this load is 1.99Vrms. RELEVANT APPLICATION NOTES The following application notes, available from www.wolfsonmicro.com, may provide additional guidance for use of the WM8533. DEVICE PERFORMANCE: WAN0129 – Decoupling and Layout Methodology for Wolfson DACs, ADCs and CODECs WAN0144 – Using Wolfson Audio DACs and CODECs with Noisy Supplies WTN0302 - WM8524 Recommended Power Sequence and Timing (for hardware mode) GENERAL: WAN0108 – Moisture Sensitivity Classification and Plastic IC Packaging WAN0109 – ESD Damage in Integrated Circuits: Causes and Prevention WAN0158 – Lead-Free Solder Profiles for Lead-Free Components WAN0161 – Electronic End-Product Design for ESD w PD, July 2012, Rev 4.0 39 WM8533 PACKAGE DIMENSIONS Production Data B: 20 BALL W-CSP PACKAGE 1.842 X 1.772 X 0.451mm BODY, 0.35 mm BALL PITCH DM107.A 6 A D A 2 3 4 5 A2 2 1 DETAIL 1 A A1 CORNER 4 B e 5 E E1 C D 2X DETAIL 2 ddd e M Z AB 2X aaa B aaa A B TOP VIEW D1 BOTTOM VIEW f1 SOLDER BALL f2 bbb Z h 1 Z ccc Z A1 DETAIL 1 DETAIL 2 Symbols A MIN 0.421 0.146 A1 A2 D D1 E E1 e f1 0.2085 f2 0.3485 h 0.175 0.266 1.817 1.747 Dimensions (mm) NOM MAX 0.451 0.481 0.172 0.198 0.292 0.279 1.842 1.867 1.400 BSC 1.772 1.797 1.050 BSC 0.350 BSC 0.221 0.361 aaa bbb ccc ddd 0.205 NOTE 5 0.235 0.025 0.060 0.030 0.015 NOTES: 1. PRIMARY DATUM -Z- AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 2. THIS DIMENSION INCLUDES STAND-OFF HEIGHT ‘A1’. 3. A1 CORNER IS IDENTIFIED BY INK/LASER MARK ON TOP PACKAGE. 4. BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY. 5. ‘e’ REPRESENTS THE BASIC SOLDER BALL GRID PITCH. 6. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 7. FOLLOWS JEDEC DESIGN GUIDE MO-211-C. w PD, July 2012, Rev 4.0 40 Production Data WM8533 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer’s own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: [email protected] w PD, July 2012, Rev 4.0 41