w WM8726 24-bit 192kHz Stereo DAC DESCRIPTION FEATURES The WM8726 is a high performance stereo DAC designed for audio applications such as DVD, home theatre systems, and digital TV. The WM8726 supports data input word lengths from 16 to 24-bits and sampling rates up to 192kHz. The WM8726 consists of a serial interface port, digital interpolation filters, multi-bit sigma delta modulators and stereo DAC. Stereo DAC Audio Performance 97 dB SNR (‘A’ weighted @ 48kHz) -89 dB THD DAC Sampling Frequency: 8kHz – 192kHz Pin Selectable Audio Data Interface Format I S, 16-bit Right Justified or DSP 3.0V - 5.5V Supply Operation 14-lead SOIC Package Pin Compatible with WM8725 2 The WM8726 has a hardware control interface for selection of audio data interface format, mute and de-emphasis. The 2 WM8726 supports I S, right Justified or DSP interfaces. The WM8726 is an ideal device to interface to AC-3, DTS, and MPEG audio decoders for surround sound applications, or for use in DVD players, including supporting the implementation of 2 channels at 192kHz for high-end DVD-Audio applications. APPLICATIONS The WM8726 is available in a 14-lead SOIC package. DVD Players Home Theatre Systems Digital TV Digital Set Top Boxes Automotive BLOCK DIAGRAM FORMAT MUTE DEEMPH W WM8726 CONTROL INTERFACE MUTE BCKIN LRCIN AUDIO INTERFACE SIGMA DELTA MODULATOR RIGHT DAC VOUTR SIGMA DELTA MODULATOR LEFT DAC VOUTL DIGITAL FILTERS DIN MUTE CAP MCLK WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews VDD GND Production Data, January 2012, Rev 4.8 Copyright 2012 Wolfson Microelectronics plc WM8726 Production Data TABLE OF CONTENTS DESCRIPTION ............................................................................................................ 1 FEATURES ................................................................................................................. 1 APPLICATIONS.......................................................................................................... 1 BLOCK DIAGRAM ..................................................................................................... 1 TABLE OF CONTENTS .............................................................................................. 2 PIN CONFIGURATION ............................................................................................... 3 ORDERING INFORMATION ....................................................................................... 3 PIN DESCRIPTION ..................................................................................................... 4 ABSOLUTE MAXIMUM RATINGS ............................................................................. 5 DC ELECTRICAL CHARACTERISTICS .................................................................... 6 ELECTRICAL CHARACTERISTICS .......................................................................... 6 TERMINOLOGY ....................................................................................................................7 MASTER CLOCK TIMING .......................................................................................... 8 DIGITAL AUDIO INTERFACE .................................................................................... 8 POWER ON RESET (POR) ........................................................................................ 9 DEVICE DESCRIPTION ........................................................................................... 11 GENERAL INTRODUCTION ...............................................................................................11 DAC CIRCUIT DESCRIPTION ............................................................................................11 CLOCKING SCHEMES .......................................................................................................12 DIGITAL AUDIO INTERFACE .............................................................................................12 AUDIO DATA SAMPLING RATES ......................................................................................14 HARDWARE CONTROL MODES .......................................................................................15 DIGITAL FILTER CHARACTERISTICS ................................................................... 17 DAC FILTER RESPONSES ................................................................................................17 DIGITAL DE-EMPHASIS CHARACTERISTICS ..................................................................18 APPLICATIONS INFORMATION ............................................................................. 19 RECOMMENDED EXTERNAL COMPONENTS .................................................................19 RECOMMENDED EXTERNAL COMPONENTS VALUES ..................................................19 RECOMMENDED ANALOGUE LOW PASS FILTER ..........................................................20 PCB LAYOUT RECOMMENDATIONS ................................................................................20 PACKAGE DIMENSIONS ......................................................................................... 21 IMPORTANT NOTICE .............................................................................................. 22 ADDRESS: ..........................................................................................................................22 REVISION HISTORY ................................................................................................ 23 w PD, Rev 4.8, January 2012 2 WM8726 Production Data PIN CONFIGURATION LRCIN 1 14 MCLK DIN 2 13 FORMAT BCKIN 3 12 DEEMPH NC 4 WM8726 11 CAP 5 10 MUTE VOUTR 6 9 VOUTL GND 7 8 VDD NC ORDERING INFORMATION DEVICE TEMPERATURE RANGE WM8726CGED -40 to +85 C WM8726CGED/R -40 to +85 C o o PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE 14-lead SOIC (Pb-free) MSL1 260 C 14-lead SOIC (Pb-free, tape and reel) MSL1 260 C o o Notes: 1. Reel quantity = 3,000 w PD, Rev 4.8, January 2012 3 WM8726 Production Data PIN DESCRIPTION PIN NAME 1 LRCIN 2 3 TYPE DESCRIPTION Digital input Sample rate clock input DIN Digital input Serial audio data input BCKIN Digital input Bit clock input 4 NC No connect No internal connection 5 CAP Analogue output Analogue internal reference 6 VOUTR Analogue output Right channel DAC output 7 GND Supply Negative supply 8 VDD Supply Positive supply 9 VOUTL Analogue output Left channel DAC output 10 MUTE Digital input Soft mute control, Internal pull down High Impedance = Automute High = Mute ON Low = Mute OFF 11 NC No connect 12 DEEMPH Digital input No internal connection De-emphasis select, Internal pull up High = de-emphasis ON Low = de-emphasis OFF 13 FORMAT Digital input Data input format select, Internal pull up Low = 16-bit right justified or DSP ‘late’ 2 High = 16-24-bit I S or DSP ‘early’ 14 MCLK Digital input Master clock input Note: 1. Digital input pins have Schmitt trigger input buffers. w PD, Rev 4.8, January 2012 4 WM8726 Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION Supply voltage Voltage range digital inputs MIN MAX -0.3V +7V GND -0.3V VDD +0.3V Master Clock Frequency 50MHz Operating temperature range , TA -40C +85C Storage temperature after soldering -65C +150C w PD, Rev 4.8, January 2012 5 WM8726 Production Data DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Supply range VDD Ground GND TEST CONDITIONS MIN TYP 3.0 MAX UNIT 5.5 V 0 V 27 mA Supply current VDD = 5V Supply current VDD = 3.3V 23 mA Power down current (note 4) VDD=3.3V 0.6 mA ELECTRICAL CHARACTERISTICS All MIN/MAX characteristics are guaranteed over the recommended operating conditions. Typical characteristics are based on measurements taken under the test conditions specified below. Test Conditions o VDD = 5V, GND = 0V, TA = +25 C, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital Logic Levels (TTL Levels) Input LOW level VIL Input HIGH level VIH 0.8 2.0 Output LOW VOL IOL = 2mA Output HIGH VOH IOH = 2mA RCAP VDD to CAP and CAP to GND V V GND + 0.3V VDD - 0.3V V V Analogue Reference Levels Reference voltage (CAP) Potential divider resistance VDD/2 V 33k 1.1 x VDD/5 Vrms DAC Output (Load = 10k 50pF) 0dBFs Full scale output voltage At DAC outputs DAC Performance (+25˚C ) SNR (Note 1,2,3) SNR (Note 1,2,3) SNR (Note 1,2,3) SNR (Note 1,2,3) SNR (Note 1,2,3) SNR (Note 1,2,3) THD (Note 3) Dynamic Range (Note 2) A-weighted, @ fs = 48kHz A-weighted @ fs = 96kHz A-weighted @ fs = 192kHz A-weighted, @ fs = 48kHz VDD = 3.3V A-weighted @ fs = 96kHz VDD = 3.3V Non ‘A’ weighted @ fs = 48kHz 1kHz, 0dBFs 90 1kHz, THD+N @ -60dBFs 90 DAC channel separation 97 dB 94 dB 94 dB 93 dB 93 dB 95 dB -89 dB 97 dB 93 dB 1.1 0.72 VRMS VRMS Analogue Output Levels Output level w Load = 10k, 0dBFS Load = 10k, 0dBFS, (VDD = 3.3V) PD, Rev 4.8, January 2012 6 WM8726 Production Data Test Conditions o VDD = 5V, GND = 0V, TA = +25 C, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN Gain mismatch channel-to-channel Minimum resistance load Maximum capacitance load To midrail or a.c. coupled To midrail or a.c. coupled (VDD = 3.3V) 5V or 3.3V Output d.c. level TYP MAX UNIT ±1 %FSR 1 k 1 k 100 pF VDD/2 V 2.4 V Power On Reset (POR) POR threshold Notes: 1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted over a 20Hz to 20kHz bandwidth. 2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 3. CAP pin decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance). 4. Power down occurs 1.5s after MCLK is stopped. TERMINOLOGY 1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). 2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). 3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. 4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band). 5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. w PD, Rev 4.8, January 2012 7 WM8726 Production Data MASTER CLOCK TIMING tMCLKL MCLK tMCLKH tMCLKY Figure 1 Master Clock Timing Requirements Test Conditions o VDD = 5V, GND = 0V, TA = +25 C, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT System Clock Timing Information MCLK Master clock pulse width high tMCLKH 8 ns MCLK Master clock pulse width low tMCLKL 8 ns MCLK Master clock cycle time tMCLKY 20 MCLK Duty cycle Time from MCLK stopping to power down. ns 40:60 60:40 1.5 12 s MAX UNIT DIGITAL AUDIO INTERFACE tBCH tBCL BCKIN tBCY LRCIN tDS tLRH tLRSU DIN tDH Figure 2 Digital Audio Data Timing Test Conditions o VDD = 5V, GND = 0V, TA = +25 C, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP Audio Data Input Timing Information BCKIN cycle time tBCY 40 ns BCKIN pulse width high tBCH 16 ns BCKIN pulse width low tBCL 16 ns LRCIN set-up time to BCKIN rising edge tLRSU 8 ns LRCIN hold time from BCKIN rising edge tLRH 8 ns DIN set-up time to BCKIN rising edge tDS 8 ns DIN hold time from BCKIN rising edge tDH 8 ns w PD, Rev 4.8, January 2012 8 WM8726 Production Data POWER ON RESET (POR) The WM8726 has an internal power-on-reset (POR) circuit which is used to reset the digital logic into a default state after power up. A block diagram of the reset circuit is shown in Figure 3 Figure 3 Block Diagram of Power-On-Reset The active low reset signal NPOR will be asserted low until VDD=2.4V, which means VMID rises to 1.2V. When this threshold has been reached, then the NPOR is released and the digital interface has been reset. This is illustrated in the diagram shown in Figure 4. Figure 4 Generation of Internal NPOR at Power-On-Reset w PD, Rev 4.8, January 2012 9 WM8726 Production Data Figure 5 illustrates the NPOR generation when the power is removed. Figure 5 Generation of NPOR at Power-Off-Reset w PD, Rev 4.8, January 2012 10 WM8726 Production Data DEVICE DESCRIPTION GENERAL INTRODUCTION The WM8726 is a high performance DAC designed for digital consumer audio applications. The range of features make it ideally suited for use in DVD players, AV receivers and other consumer audio equipment. The WM8726 is a complete 2-channel stereo audio digital-to-analogue converter, including digital interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit stereo DAC and output smoothing filters. It is fully compatible and an ideal partner for a range of industry standard microprocessors, controllers and DSPs. A novel multi bit sigma-delta DAC design is used, utilising a 128x oversampling rate, to optimise signal to noise performance and offer increased clock jitter tolerance. (In ‘high-rate’ operation, the oversampling ratio is 64x for system clocks of 128fs or 192fs) Control of internal functionality of the device is provided by hardware control (pin programmed). Operation using master clocks of 256fs, 384fs, 512fs or 768fs is provided, selection between clock rates being automatically controlled. Sample rates (fs) from less than 8kHz to 96kHz are allowed, provided the appropriate system clock is input. Support is also provided for up to 192kHz using a master clock of 128fs or 192fs. 2 The audio data interface supports 16-bit right justified or 16-24-bit I S (Philips left justified, one bit delayed) interface formats. A DSP interface is also supported, enhancing the interface options for the user. A single 3.0-5.5V supply may be used, the output amplitude scaling with absolute supply level. Low supply voltage operation and low current consumption combined with the low pin count small package make the WM8726 attractive for many consumer applications. The device is packaged in a small 14-pin SOIC. DAC CIRCUIT DESCRIPTION The WM8726 DAC is designed to allow playback of 24-bit PCM audio or similar data with high resolution and low noise and distortion. Sample rates up to 192kHz may be used, with much lower sample rates acceptable provided that the ratio of sample rate (LRCIN) to master clock (MCLK) is maintained at one of the required rates. The two DACs on the WM8726 are implemented using sigma-delta oversampled conversion techniques. These require that the PCM samples are digitally filtered and interpolated to generate a set of samples at a much higher rate than the up to 192kHz input rate. This sample stream is then digitally modulated to generate a digital pulse stream that is then converted to analogue signals in a switched capacitor DAC. The advantage of this technique is that the DAC is linearised using noise shaping techniques, allowing the 24-bit resolution to be met using non-critical analogue components. A further advantage is that the high sample rate at the DAC output means that smoothing filters on the output of the DAC need only have fairly crude characteristics in order to remove the characteristic steps, or images on the output of the DAC. To ensure that generation of tones characteristic to sigma-delta convertors is not a problem, dithering is used in the digital modulator along with a higher order modulator. The multi-bit switched capacitor technique used in the DAC reduces sensitivity to clock jitter, and dramatically reduces out of band noise compared to switched current or single bit techniques used in other implementations. The voltage on the CAP pin is used as the reference for the DACs. Therefore the amplitude of the signals at the DAC outputs will scale with the amplitude of the voltage at the CAP pin. An external reference could be used to drive into the CAP pin if desired, with a value typically of about midrail ideal for optimum performance. The outputs of the 2 DACs are buffered out of the device by buffer amplifiers. These amplifiers will source load currents of several mA and sink current up to 1.5mA allowing significant loads to be driven. The output source is active and the sink is Class A, i.e. fixed value, so greater loads might be driven if an external ‘pull-down’ resistor is connected at the output. w PD, Rev 4.8, January 2012 11 WM8726 Production Data Typically an external low pass filter circuit will be used to remove residual out of band noise characteristic of delta sigma converters. However, the advanced multi-bit DAC used in WM8726 produces far less out of band noise than single bit traditional sigma delta DACs, and so in many applications this filter may be removed, or replaced with a simple RC pole. CLOCKING SCHEMES In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system’s Master Clock. The external master clock can be applied directly through the MCLK input pin with no configuration necessary for sample rate selection. Note that on the WM8726, MCLK is used to derive clocks for the DAC path. The DAC path consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the DAC. The device can be powered down by stopping MCLK. In this state the power consumption is substantially reduced. DIGITAL AUDIO INTERFACE Audio data is applied to the internal DAC filters via the Digital Audio Interface. Three interface formats are supported: Right Justified mode I S mode DSP mode 2 All formats send the MSB first. The data format is selected with the FORMAT pin. When FORMAT is LOW, right justified data format is selected and word lengths up to 16-bits may be used. When 2 the FORMAT pin is HIGH, I S format is selected and word length of any value up to 24-bits may be used. (If a word length shorter than 24-bits is used, the unused bits will be padded with zeros). If LRCIN is 4 BCKINs or less duration, the DSP compatible format is selected. Early and Late clock formats are supported, selected by the state of the FORMAT pin. 2 ‘Packed’ mode (i.e. only 32 or 48 clocks per LRCIN period) operation is also supported in both I S (16-24 bits) and right justified formats, (16 bit). If a ‘packed’ format of 16-bit word length is applied (16 BCKINS per LRCIN half period), the device auto-detects this mode and switches to 16-bit data length. 2 I S MODE 2 The WM8726 supports word lengths of 16-24 bits in I S mode. 2 In I S mode, the digital audio interface receives data on the DIN input. Audio Data is time multiplexed with LRCIN indicating whether the left or right channel is present. LRCIN is also used as a timing reference to indicate the beginning or end of the data words. 2 In I S modes, the minimum number of BCKINs per LRCIN period is 2 times the selected word length. LRCIN must be high for a minimum of word length BCKINs and low for a minimum of word length BCKINs. Any mark to space ratio on LRCIN is acceptable provided the above requirements 2 are met. In I S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN transition. LRCIN is low during the left samples and high during the right samples. w PD, Rev 4.8, January 2012 12 WM8726 Production Data 1/fs LEFT CHANNEL RIGHT CHANNEL LRCIN BCKIN 1 BCKIN 1 BCKIN DIN 1 2 3 n-2 n-1 n 1 LSB MSB 2 3 n-2 n-1 n LSB MSB 2 Figure 6 I S Mode Timing Diagram RIGHT JUSTIFIED MODE The WM8726 supports word lengths of 16-bits in right justified mode. In right justified mode, the digital audio interface receives data on the DIN input. Audio Data is time multiplexed with LRCIN indicating whether the left or right channel is present. LRCIN is also used as a timing reference to indicate the beginning or end of the data words. In right justified mode, the minimum number of BCKINs per LRCIN period is 2 times the selected word length. LRCIN must be high for a minimum of word length BCKINs and low for a minimum of word length BCKINs. Any mark to space ratio on LRCIN is acceptable provided the above requirements are met. In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN transition. LRCIN is high during the left samples and low during the right samples. 1/fs LEFT CHANNEL RIGHT CHANNEL LRCIN BCKIN DIN 1 2 3 14 15 MSB 16 LSB 1 MSB 2 3 14 15 16 LSB Figure 7 Right Justified Mode Timing Diagram DSP MODE A DSP compatible, time division multiplexed format is also supported by the WM8726. This format is of the type where a ‘synch’ pulse is followed by two data words (left and right) of predetermined word length. (16-bits). The ‘synch’ pulse replaces the normal duration LRCIN, and DSP mode is auto-detected by the shorter than normal duration of the LRCIN. If LRCIN is of 4 BCKIN or less duration, the DSP compatible format is selected. Mode A and Mode B clock formats are supported, selected by the state of the FORMAT pin. w PD, Rev 4.8, January 2012 13 WM8726 Production Data 1 1 1/f max 4 BCKIN's LRCIN BCKIN LEFT CHANNEL DIN 1 2 RIGHT CHANNEL 1 MSB 1 1 2 1 NO VALID DATA 1 LSB Input Word Length (16 bits) Figure 8 DSP Mode A Timing 1/f Max 4 BCKIN's LRCIN BCKIN LEFT CHANNEL DIN 1 2 1 MSB RIGHT CHANNEL 1 1 2 1 NO VALID DATA 1 16 LSB Input Word Length (16 bits) Figure 9 DSP Mode B Timing AUDIO DATA SAMPLING RATES The master clock for WM8726 supports audio sampling rates from 128fs to 768fs, where fs is the audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The master clock is used to operate the digital filters and the noise shaping circuits. The WM8726 has a master clock detection circuit that automatically determines the relation between the master clock frequency and the sampling rate (to within +/- 8 master clocks). If there is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output. The master clock should be synchronised with LRCIN, although the WM8726 is tolerant of phase differences or jitter on this clock. SAMPLING RATE (LRCIN) 32kHz 44.1kHz 48kHz 96kHz 192kHz MASTER CLOCK FREQUENCY (MHZ) (MCLK) 128fs 192fs 256fs 384fs 512fs 768fs 4.096 5.6448 6.144 12.288 24.576 6.144 8.467 9.216 18.432 36.864 8.192 11.2896 12.288 24.576 Unavailable 12.288 16.9344 18.432 36.864 Unavailable 16.384 22.5792 24.576 Unavailable Unavailable 24.576 33.8688 36.864 Unavailable Unavailable Table 1 Master Clock Frequencies Versus Sampling Rate If operating in 192fs or 384fs modes, the following conditions must be met, otherwise the WM8726 may behave in an unspecified manner: w 1. After reset, ensure that LRCLK and BCLK are provided within 768 MCLK periods of MCLK starting up 2. If switching to 192fs or 384fs modes at any time during operation, reset the WM8726 by recycling the power or driving the CAP pin low PD, Rev 4.8, January 2012 14 WM8726 Production Data HARDWARE CONTROL MODES The WM8726 is hardware programmable providing the user with options to select input audio data format, de-emphasis and mute. MUTE AND AUTO MUTE OPERATION Pin 10 (MUTE) controls selection of MUTE directly, and can be used to enable and disable the automute function, or as an output of the automuted signal. MUTEB PIN DESCRIPTION 0 Normal Operation, MUTE off 1 Mute DAC channels Floating Enable IZD, MUTE becomes an output to indicate when IZD occurs. Table 2 Mute and Automute Control 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 0.001 0.002 0.003 0.004 0.005 0.006 Time(s) Figure 10 Application and Release of MUTE The MUTE pin is an input to select mute or not mute. MUTE is active high; taking the pin high causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking MUTE low again allows data into the filter. Refer to Figure 10. The Infinite Zero Detect (IZD) function detects a series of zero value audio samples of 1024 samples long being applied to both channels. After such an event, a latch is set whose output (AUTOMUTED) is connected through a 10kohm resistor to the MUTE pin. Thus if the MUTE pin is not being driven, the automute function will assert mute. If MUTE is tied low, AUTOMUTED is overridden and will not mute. If MUTE is driven from a bidirectional source, then both MUTE and automute functions are available. If MUTE is not driven, AUTOMUTED appears as a weak output (10k source impedance) so can be used to drive external mute circuits. AUTOMUTED will be removed as soon as any channel receives a non-zero input. w PD, Rev 4.8, January 2012 15 WM8726 Production Data A diagram showing how the various Mute modes interact is shown below in Figure 11. AUTOMUTED (Internal Signal) 10k MUTE PIN SOFTMUTE (Internal Signal) Figure 11 Selection Logic for MUTE Modes INPUT AUDIO FORMAT SELECTION FORMAT (pin 13) controls the data input format. FORMAT INPUT DATA MODE 0 16 bit right justified 1 16–24 bit I S 2 Table 3 Input Audio Format Selection Notes: 2 1. In 16-24 bit I S mode, any data from 16-24 bits or more is supported provided that LRCIN is high for a minimum of data width BCKINs and low for a minimum of data width BCKINs, unless Note 2. For data widths greater than 24 bits, the LSB’s will be truncated and the most significant 24 bits will be used by the internal processing. 2. If exactly 16 BCKIN cycles occur in both the low and high period of LRCIN the WM8726 will assume the data is 16-bit and accept the data accordingly. INPUT DSP FORMAT SELECTION FORMAT 50% LRCIN DUTY CYCLE LRCIN of 4 BCKIN or Less Duration 0 16 bit (MSB-first, right justified) DSP format – ‘late’ mode 1 I S format up to 24 bit (Philips serial data protocol) 2 DSP format – ‘early’ mode Table 4 DSP Interface Formats DE-EMPHASIS CONTROL DEM (pin 12) is an input control for selection of de-emphasis filtering to be applied. DEEMPH DE-EMPHASIS 0 Off 1 On Table 5 De-emphasis Control DAC OUTPUT PHASE In the DAC to analogue output, the analogue output data VOUTL/R, is a phase inverted representation of the digital input signal. w PD, Rev 4.8, January 2012 16 WM8726 Production Data DIGITAL FILTER CHARACTERISTICS PARAMETER SYMBOL TEST CONDITIONS Passband Edge -3dB Passband Ripple f < 0.444fs Stopband Attenuation f > 0.555fs MIN TYP MAX UNIT 0.05 dB 0.487fs -60 dB Table 6 Digital Filter Characteristics DAC FILTER RESPONSES 0.2 0 0.15 -20 -40 Response (dB) Response (dB) 0.1 -60 0.05 0 -0.05 -80 -0.1 -100 -0.15 -120 -0.2 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 Figure 12 DAC Digital Filter Frequency Response 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5 0.35 0.4 0.45 0.5 Figure 13 DAC Digital Filter Ripple -44.1, 48 and 96kHz -44.1, 48 and 96kHz 0.2 0 0 -0.2 Response (dB) Response (dB) -20 -40 -0.4 -0.6 -60 -0.8 -80 -1 0 0.2 0.4 0.6 Frequency (Fs) 0.8 1 Figure 14 DAC Digital Filter Frequency Response -192kHz w 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) Figure 15 DAC Digital Filter Ripple -192kHz PD, Rev 4.8, January 2012 17 WM8726 Production Data DIGITAL DE-EMPHASIS CHARACTERISTICS 0 1 0.5 -2 Response (dB) Response (dB) 0 -4 -6 -0.5 -1 -1.5 -2 -8 -2.5 -10 -3 0 2 4 6 8 10 Frequency (kHz) 12 14 16 Figure 16 De-Emphasis Frequency Response (32kHz) 0 2 4 6 8 10 Frequency (kHz) 12 14 16 Figure 17 De-Emphasis Error (32kHz) 0 0.4 0.3 -2 Response (dB) Response (dB) 0.2 -4 -6 0.1 0 -0.1 -0.2 -8 -0.3 -10 -0.4 0 5 10 Frequency (kHz) 15 20 Figure 18 De-Emphasis Frequency Response (44.1kHz) 0 5 10 Frequency (kHz) 15 20 Figure 19 De-Emphasis Error (44.1kHz) 0 1 0.8 -2 0.6 Response (dB) Response (dB) 0.4 -4 -6 0.2 0 -0.2 -0.4 -8 -0.6 -0.8 -10 -1 0 5 10 15 Frequency (kHz) 20 Figure 20 De-Emphasis Frequency Response (48kHz) w 0 5 10 15 Frequency (kHz) 20 Figure 21 De-Emphasis Error (48kHz) PD, Rev 4.8, January 2012 18 WM8726 Production Data APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS VDD 8 + C1 VDD C2 7 GND AGND 13 12 Hardware Control 10 FORMAT DEEMPH MUTE 6 WM8726 1 14 3 Audio Serial Data I/F 2 AC-Coupled VOUTR/L to External LPF 9 C4 + VOUTL C3 + VOUTR LRCIN MCLK BCKIN DIN CAP 5 + C5 C6 AGND Notes: 1. C2, C5 should be positioned as close to the WM8726 as possible. 2. Capacitor types should be carefully chosen. Capacitors with very low ESR are recommended for optimum performance. 3. C3 and C4 not required if using the recommended low pass filter in Figure 20. Figure 22 External Component Diagram RECOMMENDED EXTERNAL COMPONENTS VALUES COMPONENT REFERENCE SUGGESTED VALUE DESCRIPTION De-coupling for VDD C1 10F C2 0.1F De-coupling for VDD C3 and C4 10F Output AC coupling caps to remove midrail DC level from outputs C5 C6 0.1F 10F Reference de-coupling capacitors for CAP pin Table 7 External Components Description w PD, Rev 4.8, January 2012 19 WM8726 Production Data RECOMMENDED ANALOGUE LOW PASS FILTER 4.7k 4.7k +VS _ 51 10uF + 1.8k 7.5K + 1.0nF 680pF -VS 47k nd Figure 23 Recommended 2 Order Low Pass Filter An external low pass filter is recommended (see Figure 20) if the device is driving a wideband amplifier. In some applications, a passive RC filter may be adequate. PCB LAYOUT RECOMMENDATIONS Care should be taken in the layout of the PCB that the WM8726 is to be mounted to. The following notes will help in this respect: 1. The VDD supply to the device should be as noise free as possible. This can be accomplished to a large degree with a 10uF bulk capacitor placed locally to the device and a 0.1uF high frequency decoupling capacitor placed as close to the VDD pin as possible. It is best to place the 0.1uF capacitor directly between the VDD and GND pins of the device on the same layer to minimize track inductance and thus improve device decoupling effectiveness. 2. The CAP pin should be as noise free as possible. This pin provides the decoupling for the on chip reference circuits and thus any noise present on this pin will be directly coupled to the device outputs. In a similar manner to the VDD decoupling described in 1. above, this pin should be decoupled with a 10uF bulk capacitor local to the device and a 0.1uF capacitor as close to the CAP pin as possible. 3. Separate analogue and digital track routing from each other. The device is split into analogue (pins 5 – 9) and digital (pins 1 – 4 & pins 10 – 14) sections that allow the routing of these signals to be easily separated. By physically separating analogue and digital signals, crosstalk from the PCB can be minimized. 4. Use an unbroken solid GND plane. To achieve best performance from the device, it is advisable to have either a GND plane layer on a multilayer PCB or to dedicate one side of a 2 layer PCB to be a GND plane. For double sided implementations it is best to route as many signals as possible on the device mounted side of the board, with the opposite side acting as a GND plane. The use of a GND plane greatly reduces any electrical emissions from the PCB and minimizes crosstalk between signals. An evaluation board is available for the WM8726 that demonstrates the above techniques and the excellent performance achievable from the device. This can be ordered or the User manual downloaded from the Wolfson web site at www.wolfsonmicro.com w PD, Rev 4.8, January 2012 20 WM8726 Production Data PACKAGE DIMENSIONS DM001.C D: 14 PIN SOIC 3.9mm Wide Body e B 14 8 H E 1 7 D L h x 45o A1 -CA C 0.10 (0.004) A A1 B C D E e H h L Dimensions (mm) MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.27 o o 0 8 REF: JEDEC.95, MS-012 Symbols SEATING PLANE Dimensions (Inches) MIN MAX 0.0532 0.0688 0.0040 0.0098 0.0130 0.0200 0.0075 0.0098 0.3367 0.3444 0.1497 0.1574 0.05 BSC 0.2284 0.2440 0.0099 0.0196 0.0160 0.0500 o o 0 8 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES). B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN). D. MEETS JEDEC.95 MS-012, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. w PD, Rev 4.8, January 2012 21 WM8726 Production Data IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer’s own risk. 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Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: [email protected] w PD, Rev 4.8, January 2012 22 WM8726 Production Data REVISION HISTORY REV ORIGINATOR 28/06/11 DATE 4.7 BT Added 192fs and 384fs recommended operating conditions to avoid unspecified operation in Audio Data Sampling Rates section, p14 23/09/11 4.8 JMacD Order codes updated from WM8726GED/V and WM8726GED/RV to WM8726CGED and WM8726CGED/R to reflect copper wire bonding and MSL change. 23/09/11 4.8 JMacD MSL level changed from MSL2 to MSL1. w CHANGES PD, Rev 4.8, January 2012 23