ADC122S625 Dual 12-Bit, 50 kSPS to 200 kSPS, Simultaneous Sampling A/D Converter General Description Features The ADC122S625 is a dual 12-bit, 50 kSPS to 200 kSPS simultaneous sampling Analog-to-Digital (A/D) converter. The analog inputs on both channels are sampled simultaneously to preserve their relative phase information to each other. The converter is based on a successive-approximation register architecture where the differential nature of the analog inputs is maintained from the internal track-and-hold circuits throughout the A/D converter to provide excellent commonmode signal rejection. The ADC122S625 features an external reference that can be varied from 1.0V to VA. The ADC122S625's serial data output is binary 2's complement and is compatible with several standards, such as SPI™, QSPI™, MICROWIRE™, and many common DSP serial interfaces. The serial clock (SCLK) and chip select bar (CS) are shared by both channels. Operating from a single 5V analog supply and a reference voltage of 2.5V, the total power consumption while operating at 200 kSPS is typically 8.6 mW. With the ADC122S625 operating in power-down mode, the power consumption reduces to 2.6 µW. The differential input, low power consumption, and small size make the ADC122S625 ideal for direct connection to sensors in motor control applications. Operation is guaranteed over the industrial temperature range of −40°C to +105°C and clock rates of 1.6 MHz to 6.4 MHz. The ADC122S625 is available in a 10-lead MSOP package. ■ ■ ■ ■ ■ ■ ■ True Simultaneous Sampling Differential Inputs Guaranteed performance from 50 kSPS to 200 kSPS External Reference Wide Input Common-Mode Voltage Range Single High-Speed Serial Data Output Operating Temperature Range of −40°C to +105°C SPI™/QSPI™/MICROWIRE™/DSP compatible Serial Interface Key Specifications ■ ■ ■ ■ ■ ■ ■ Conversion Rate 50 kSPS to 200 kSPS INL ±1 LSB (max) DNL ±0.95 LSB (max) SNR 71 dBc (min) THD -72 dBc (min) ENOB 11.25 bits (min) Power Consumption at 200 kSPS 8.6 mW (typ) — Converting, VA = 5V, VREF = 2.5V 2.6 µW (typ) — Power-Down, VA = 5V, VREF = 2.5V Applications ■ ■ ■ ■ ■ ■ ■ Motor Control Power Meters/Monitors Multi-Axis Positioning Systems Instrumentation and Control Systems Data Acquisition Systems Medical Instruments Direct Sensor Interface Connection Diagram 30055305 TRI-STATE® is a trademark of National Semiconductor Corporation. MICROWIRE™ is a trademark of National Semiconductor Corporation. QSPI™ and SPI™ are trademarks of Motorola, Inc. © 2008 National Semiconductor Corporation 300553 www.national.com ADC122S625 Dual 12-Bit, 50 kSPS to 200 kSPS, Simultaneous Sampling A/D Converter February 25, 2008 ADC122S625 Ordering Information Order Code Temperature Range Description Top Mark ADC122S625CIMM −40°C to +105°C 10-Lead MSOP Package, 1000 Units Tape & Reel X35C ADC122S625CIMMX −40°C to +105°C 10-Lead MSOP Package, 3500 Units Tape & Reel X35C ADC122S625EB Evaluation Board Block Diagram 30055302 www.national.com 2 Pin No. Symbol Description 1 VREF Voltage Reference Input. A voltage reference between 1V and VA must be applied to this input. VREF must be decoupled to GND with a minimum ceramic capacitor value of 0.1 µF. A bulk capacitor value of 1.0 µF to 10 µF in parallel with the 0.1 µF is recommended for enhanced performance. 2 CHA+ Non-Inverting Input for Channel A. CHA+ is the positive analog input for the differential signal applied to Channel A. 3 CHA− Inverting Input for Channel A. CHA− is the negative analog input for the differential signal applied to Channel A. 4 CHB− Inverting Input for Channel B. CHB− is the negative analog input for the differential signal applied to Channel B. 5 CHB+ Non-Inverting Input for Channel B. CHB+ is the positive analog input for the differential signal applied to Channel B. 6 GND Ground. GND is the ground reference point for all signals applied to the ADC122S625. VA Analog Power Supply input. A voltage source between 4.5V and 5.5V must be applied to this input. VA must be decoupled to GND with a minimum ceramic capacitor value of 0.1 µF. A bulk capacitor value of 1.0 µF to 10 µF in parallel with the 0.1 µF is recommended for enhanced performance. 8 DOUT Serial Data Output for Channel A and Channel B. The serial data output word is comprised of 4 null bits, 12 data bits (ChA conversion result), 4 null bits, and 12 data bits (ChB conversion result). During a conversion, the data is output on the falling edges of SCLK and is valid on the rising edges. 9 SCLK Serial Clock. SCLK is used to control data transfer and serves as the conversion clock. 10 CS Chip Select Bar. CS is active low. The ADC122S625 is actively converting when CS is LOW and Power-Down Mode when CS is HIGH. A conversion begins on the fall of CS. 7 3 www.national.com ADC122S625 Pin Descriptions and Equivalent Circuits ADC122S625 Operating Ratings Absolute Maximum Ratings (Notes 1, 2) −40°C ≤ TA ≤ +105°C Supply Voltage, VA +4.5V to +5.5V Reference Voltage, VREF 1.0V to VA Input Common-Mode Voltage, VCM See Figure 9 (Sect 2.3) Digital Input Pins Voltage Range 0 to VA Clock Frequency 1.6 MHz to 6.4 MHz Differential Analog Input Voltage −VREF to +VREF If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Analog Supply Voltage VA Voltage on Any Pin to GND Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Consumption at TA = 25°C ESD Susceptibility (Note 5) Human Body Model Machine Model Charge Device Model Junction Temperature Storage Temperature (Notes 1, 2) Operating Temperature Range −0.3V to 6.5V −0.3V to (VA +0.3V) ±10 mA ±50 mA See (Note 4) Package Thermal Resistance 2500V 250V 1000V +150°C −65°C to +150°C Package θJA 10-lead MSOP 240°C / W Soldering process must comply with National Semiconductor's Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 6) ADC122S625 Converter Electrical Characteristics (Note 7) The following specifications apply for VA = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 1.6 to 6.4 MHz, fIN = 20 kHz, CL = 25 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits are at TA = 25°C. Symbol Parameter Conditions Typical Limits Units 12 Bits ±0.5 ±1 LSB (max) ±0.95 LSB (max) STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes INL DNL OE GE Integral Non-Linearity Integral Non-Linearity Matching 0.02 Differential Non-Linearity ±0.4 Differential Non-Linearity Matching 0.02 Offset Error 0.2 Offset Error Matching 0.1 Positive Gain Error −2 Positive Gain Error Matching 0.2 Negative Gain Error 3 Negative Gain Error Matching LSB LSB ±3 LSB (max) ±5 LSB (max) ±8 LSB (max) LSB LSB 0.2 LSB DYNAMIC CONVERTER CHARACTERISTICS SINAD Signal-to-Noise Plus Distortion Ratio fIN = 20 kHz, −0.1 dBFS 72.5 69.5 dBc (min) SNR Signal-to-Noise Ratio fIN = 20 kHz, −0.1 dBFS 73.2 71 dBc (min) THD Total Harmonic Distortion fIN = 20 kHz, −0.1 dBFS −83 −72 dBc (max) SFDR Spurious-Free Dynamic Range fIN = 20 kHz, −0.1 dBFS 84 72 dBc (min) ENOB Effective Number of Bits fIN = 20 kHz, −0.1 dBFS 11.8 11.25 bits (min) −3 dB Full Power Bandwidth Differential Output at 70.7%FS with Input FS Input Single-Ended Input FPBW ISOL Channel-to-Channel Isolation fIN < 1 MHz 26 MHz 22 MHz −90 dBc ANALOG INPUT CHARACTERISTICS VIN Differential Input Range IDCL DC Leakage Current CINA Input Capacitance CMRR Common Mode Rejection Ratio www.national.com −VREF VIN = VREF or VIN = -VREF V (min) +VREF V (max) ±1 µA (max) In Track Mode 20 pF In Hold Mode 3 pF −90 dB See the Specification Definitions for the test condition 4 VREF Parameter Conditions Typical Reference Voltage Range Limits Units 1.0 V (min) VA V (max) DIGITAL INPUT CHARACTERISTICS VIH Input High Voltage 2.4 V (min) VIL Input Low Voltage 0.8 V (max) IIN Input Current CIND Input Capacitance VIN = 0V or VA ±1 µA (max) 2 4 pF (max) ISOURCE = 200 µA VA − 0.02 VA − 0.2 V (min) ISOURCE = 1 mA VA − 0.09 ISINK = 200 µA 0.01 0.4 V (max) ISINK = 1 mA 0.08 ±1 µA (max) 4 pF (max) DIGITAL OUTPUT CHARACTERISTICS VOH Output High Voltage VOL Output Low Voltage IOZH, IOZL TRI-STATE Leakage Current Force 0V or VA COUT TRI-STATE Output Capacitance Force 0V or VA 2 Output Coding V V Binary 2'S Complement POWER SUPPLY CHARACTERISTICS 4.5 V (min) 5.5 V (max) 1.7 2.45 mA (max) fSCLK = 6.4 MHz, fS = 200 kSPS, VREF = 2.5V 20 40 µA (max) Analog Supply Current, Power Down Mode (CS high) fSCLK = 6.4 MHz, VA = 5.0V 10 fSCLK = 0, VA = 5.0V (Note 8) 0.5 IVREF (PD) Reference Current, Power Down Mode (CS high) fSCLK = 6.4 MHz, VREF = 2.5V 0.05 fSCLK = 0, VREF = 2.5V (Note 8) 0.05 0.1 µA (max) PWR (Conv) Power Consumption, Continuously Converting fSCLK = 6.4 MHz, fS = 200 kSPS, fIN = 20 kHz, VA = 5.0V, VREF = 2.5V 8.6 12.4 mW (max) PWR (PD) Power Consumption, Power Down Mode fSCLK = 6.4 MHz, VA = 5.0V, VREF = 2.5V (CS high) fSCLK = 0, VA = 5.0V, VREF = 2.5V 5.8 µW (max) PSRR Power Supply Rejection Ratio VA Analog Supply Voltage IVA (Conv) Analog Supply Current, Continuously Converting fSCLK = 6.4 MHz, fS = 200 kSPS, fIN = 20 kHz, VA = 5V IVREF (Conv) Reference Current, Continuously Converting IVA (PD) See the Specification Definitions for the test condition µA 1.1 µA 50 2.6 µA (max) µW −85 dB AC ELECTRICAL CHARACTERISTICS fSCLK Maximum Clock Frequency fSCLK Minimum Clock Frequency 0.8 1.6 MHz (max) Maximum Sample Rate 625 200 kSPS (min) Minimum Sample Rate 25 50 kSPS (min) fS 20 6.4 MHz (min) tACQ Track/Hold Acquisition Time 3 SCLK cycles tCONV Conversion Time 12 SCLK cycles tAD Aperture Delay 6 5 ns www.national.com ADC122S625 Symbol ADC122S625 ADC122S625 Timing Specifications (Note 7) The following specifications apply for VA = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 1.6 MHz to 6.4 MHz, CL = 25 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol tCSSU Parameter Conditions CS Setup Time prior to an SCLK rising edge Typical Limits Units 4 7 ns (min) 1/ fSCLK 1/ fSCLK - 3 ns (max) tEN DOUT Enable Time after the falling edge of CS 9 20 ns (max) tDH DOUT Hold time after an SCLK Falling edge 9 6 ns (min) tDA DOUT Access time after an SCLK Falling edge 20 26 ns (max) tDIS DOUT Disable Time after the rising edge of CS (Note 10) 10 20 ns (max) tCH SCLK High Time 25 ns (min) tCL SCLK Low Time 25 ns (min) tr DOUT Rise Time 7 ns tf DOUT Fall Time 7 ns Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended. Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < GND or VIN > VA), the current at that pin should be limited to 10 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to five. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. The values for maximum power dissipation listed above will be reached only when the ADC122S625 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided. Note 5: Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is a 220 pF capacitor discharged through 0 Ω. Charge device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged. Note 6: Reflow temperature profiles are different for lead-free packages. Note 7: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 8: Guaranteed by design, characterization, or statistical analysis and is not tested at final test. Note 9: While the maximum sample rate is fSCLK/32, the actual sample rate may be lower than this by having the CS rate slower than fSCLK/32. Note 10: tDIS is the time for DOUT to change 10%. www.national.com 6 ADC122S625 Timing Diagrams 30055342 FIGURE 1. ADC122S625 Single Conversion Timing Diagram 30055304 FIGURE 2. ADC122S625 Continuous Conversion Timing Diagram 30055306 FIGURE 3. DOUT Rise and Fall Times 30055310 FIGURE 5. Valid CS Assertion Times 30055311 FIGURE 4. DOUT Hold and Access Times 30055312 FIGURE 6. Voltage Waveform for tDIS 7 www.national.com ADC122S625 POSITIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output code transitions to positive full scale and VREF minus 1.5 LSB. POSITIVE GAIN ERROR is the difference between the positive full-scale error and the offset error. POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well a change in supply voltage is rejected. PSRR is calculated from the ratio of the change in offset error for a given change in supply voltage, expressed in dB. For the ADC122S625, VA is changed from 4.5V to 5.5V. Specification Definitions APERTURE DELAY is the time between the fourth falling edge of SCLK and the time when the input signal is acquired or held for conversion. COMMON MODE REJECTION RATIO (CMRR) is a measure of how well in-phase signals common to both input pins are rejected. To calculate CMRR, the change in output offset is measured while the common mode input voltage is changed from 2V to 3V. PSRR = 20 LOG (ΔOffset / ΔVA) CMRR = 20 LOG ( Δ Output Offset / Δ Common Input) SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is any signal present in the output spectrum that is not present at the input and may or may not be a harmonic. TOTAL HARMONIC DISTORTION (THD) is the ratio of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output, expressed in dB. THD is calculated as CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input voltage to a digital word. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the SCLK. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC122S625 is guaranteed not to have any missing codes. NEGATIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output code transitions from negative full scale to the next code and −VREF + 0.5 LSB. NEGATIVE GAIN ERROR is the difference between the negative full-scale error and the offset error. OFFSET ERROR is the difference between the differential input voltage at which the output code transitions from code 000h to 001h and 1/2 LSB. www.national.com where Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the first 5 harmonic frequencies. THROUGHPUT TIME is the minimum time required between the start of two successive conversion. 8 VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 200 kSPS, fSCLK = DNL - 200 kSPS INL - 200 kSPS 30055321 30055322 DNL vs. VA INL vs. VA 30055323 30055324 DNL vs. VREF INL vs. VREF 30055318 30055319 9 www.national.com ADC122S625 Typical Performance Characteristics 6.4 MHz, fIN = 20 kHz unless otherwise stated. ADC122S625 Typical Performance Characteristics VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 200 kSPS, fSCLK = 6.4 MHz, fIN = 20 kHz unless otherwise stated. DNL vs. SCLK FREQUENCY INL vs. SCLK FREQUENCY 30055325 30055326 DNL vs. TEMPERATURE INL vs. TEMPERATURE 30055329 30055330 SINAD vs. VA THD vs. VA 30055333 www.national.com 30055332 10 VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 200 kSPS, fSCLK = SINAD vs. VREF THD vs. VREF 30055337 30055336 SINAD vs. SCLK FREQUENCY THD vs. SCLK FREQUENCY 30055341 30055340 SINAD vs. INPUT FREQUENCY THD vs. INPUT FREQUENCY 30055349 30055348 11 www.national.com ADC122S625 Typical Performance Characteristics 6.4 MHz, fIN = 20 kHz unless otherwise stated. ADC122S625 Typical Performance Characteristics VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 200 kSPS, fSCLK = 6.4 MHz, fIN = 20 kHz unless otherwise stated. SINAD vs. TEMPERATURE THD vs. TEMPERATURE 30055372 30055371 VA CURRENT vs. VA VA CURRENT vs. SCLK FREQ 30055374 30055355 VA CURRENT vs. TEMPERATURE VREF CURRENT vs. SCLK FREQ 30055354 www.national.com 30055352 12 VA = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 200 kSPS, fSCLK = VREF CURRENT vs. TEMP CMRR vs. CM RIPPLE FREQ 30055373 30055351 SPECTRAL RESPONSE - 200 kSPS 30055314 13 www.national.com ADC122S625 Typical Performance Characteristics 6.4 MHz, fIN = 20 kHz unless otherwise stated. ADC122S625 crease. Since the noise is Gaussian in nature, the effects of this noise can be reduced by averaging the results of a number of consecutive conversions. Additionally, since offset and gain errors are specified in LSB, any offset and/or gain errors inherent in the A/D converter will increase in terms of LSB size as the reference voltage is reduced. The reference input and the analog inputs are connected to the capacitor array through a switch matrix when the input is sampled. Hence, the current requirements at the reference and at the analog inputs are a series of transient spikes that occur at a frequency dependent on the operating sample rate of the ADC122S625. The reference current changes only slightly with temperature. See the curves, “Reference Current vs. SCLK Frequency” and “Reference Current vs. Temperature” in the Typical Performance Curves section for additional details. Functional Description The ADC122S625 is a dual 12-bit, simultaneous sampling Analog-to-Digital (A/D) converter. The converter is based on a successive-approximation register (SAR) architecture where the differential nature of the analog inputs is maintained from the internal track-and-hold circuits throughout the A/D converter. The analog inputs on both channels are sampled simultaneously to preserve their relative phase information to each other. The architecture and process allow the ADC122S625 to acquire and convert dual analog signals at sample rates up to 200 kSPS while consuming very little power. The ADC122S625 requires an external reference, external clock, and an analog power supply. The analog supply (VA) can range from 4.5V to 5.5V and the external reference can be any voltage between 1V and VA. The value of the reference voltage determines the range of the analog input, while the reference input current depends upon the conversion rate. Analog inputs are presented at the inputs of Channel A and Channel B. Upon initiation of a conversion, the differential input at these pins is sampled on the internal capacitor array. The analog input signals are disconnected from the external circuitry while a conversion is in progress. The external clock can take on values as indicated in the Electrical Characteristics Table. The duty cycle of the clock is essentially unimportant, provided the minimum clock high and low times are met. The minimum clock frequency is set by internal capacitor leakage. Each conversion requires thirytwo clock cycles to complete. The ADC122S625 offers a high-speed serial data output that is binary 2's complement and compatible with several standards, such as SPI™, QSPI™, MICROWIRE™, and many common DSP serial interfaces. The digital conversion result of Channel A and Channel B is clocked out on the falling edges of the SCLK input and is provided serially at DOUT, most significant bit first. The result of Channel A is output before the result of Channel B, with four zeros in between the two results. The digital data provided on DOUT is that of the conversion currently in progress. With CS held low after the result of Channel B is output, the ADC122S625 will continuously convert the analog inputs until CS is de-asserted (brought high). Having a single, serial DOUT makes the ADC122S625 an excellent replacement for two independent ADCs that are part of a daisy chain configuration and allows a system designer to save valuable board space and power. 2.0 ANALOG SIGNAL INPUTS The ADC122S625 has dual differential inputs where the effective input voltage that is digitized is CHA+ minus CHA− (DIFFINA) and CHB+ minus CHB− (DIFFINB). As is the case with all differential input A/D converters, operation with a fully differential input signal or voltage will provide better performance than with a single-ended input. However, the ADC122S625 can be presented with a single-ended input as shown in Section 2.2 and the Application Circuits. The current required to recharge the input sampling capacitor will cause voltage spikes at the + and − inputs. Do not try to filter out these noise spikes. Rather, ensure that the noise spikes settle out during the acquisition period (three SCLK cycles after the fall of CS). This is true for both Channel A and Channel B since both channels are converted simultaneously on the fourth falling edge of SCLK after CS is asserted. 2.1 Differential Input Operation With a fully differential input voltage or signal, a positive full scale output code (0111 1111 1111b or 7FFh) will be obtained when DIFFINA or DIFFINB is greater than or equal to VREF − 1.5 LSB. A negative full scale code (1000 0000 0000b or 800h) will be obtained when DIFFINA or DIFFINB is greater than or equal to −VREF + 0.5 LSB. This ignores gain, offset and linearity errors, which will affect the exact differential input voltage that will determine any given output code. Figure 7 shows the ADC122S625 being driven by a full-scale differential source. 1.0 REFERENCE INPUT The externally supplied reference voltage sets the analog input range. The ADC122S625 will operate with a reference voltage in the range of 1V to VA. Operation with a reference voltage below 1V is also possible with slightly diminished performance. As the reference voltage (V REF) is reduced, the range of acceptable analog input voltages is reduced. Assuming a proper common-mode input voltage, the differential peak-to-peak input range is limited to twice VREF. See Section 2.3 for more details. Reducing the value of VREF also reduces the size of the least significant bit (LSB). The size of one LSB is equal to twice the reference voltage divided by 4096. When the LSB size goes below the noise floor of the ADC122S625, the noise will span an increasing number of codes and overall performance will suffer. For example, dynamic signals will have their SNR degrade, while D.C. measurements will have their code uncertainty in- www.national.com 30055380 FIGURE 7. Differential Input 14 ADC122S625 2.2 Single-Ended Input Operation For single-ended operation, the non-inverting inputs of the ADC122S625 can be driven with a signal that has a maximum to minimum value range that is equal to or less than twice the reference voltage. The inverting inputs should be biased at a stable voltage that is halfway between these maximum and minimum values. In order to utilize the entire dynamic range of the ADC122S625, the reference voltage is limited at VA / 2. This allows the non-inverting inputs the maximum swing range of ground to VA. Figure 8 shows the ADC122S625 being driven by a full-scale single-ended source. Even though the design of the ADC122S625 is optimized for a differential input, there is very little performance degradation while operating the ADC122S625 in single-ended fashion. 30055362 FIGURE 10. VCM range for single-ended operation TABLE 1. Allowable VCM Range Input Signal Differential Single-Ended 30055381 Minimum VCM Maximum VCM VREF / 2 VA − VREF / 2 VREF VA − VREF 3.0 SERIAL DIGITAL INTERFACE The ADC122S625 communicates via a synchronous serial interface as shown in the Timing Diagram section. CS, chip select, initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of the serial data. DOUT is the serial data output pin, where the conversion results of Channel A and Channel B are sent as a serial data stream, with the result of Channel A output before the result of Channel B. A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. The ADC122S625's DOUT is in a high impedance state when CS is high (asserted) and is active when CS is low (de-asserted); thus CS acts as an output enable. A timing diagram for a single conversion is shown in Figure 1. During the first three cycles of SCLK, the ADC122S625 is in acquisition mode (tACQ), tracking the input voltage on both Channel A and Channel B. For the next twelve SCLK cycles (tCONV), the conversion of Channel A and Channel B is accomplished simultaneously and data is presented on DOUT, one bit at a time. SCLK falling edges one through four clock out leading zeros while falling edges five through sixteen clock out the conversion result of Channel A, MSB first. The process is repeated in order to clock out the result of Channel B, with SCLK falling edges seventeen through twenty clocking out four zeros followed by falling edges twenty-one through thirty-two clokcing out the conversion result of Channel B. If there is more than one conversion in a frame (continuous conversion mode), the ADC122S625 will re-enter acquisition mode on the falling edge of SCLK after the N*32 rising edge of SCLK and re-enter conversion mode on the N*32+4 falling edge of SCLK as shown in Figure 2. "N" is an integer value. The ADC122S625 can enter acquisition mode under three different conditions. The first condition involves CS going low (asserted) with SCLK high. In this case, the ADC122S625 enters acquisition mode on the first falling edge of SCLK after CS is asserted. In the second condition, CS goes low with SCLK low. Under this condition, the ADC122S625 automatically enters acquisition mode and the falling edge of CS is FIGURE 8. Single-Ended Input 2.3 Input Common Mode Voltage The allowable input common mode voltage (VCM) range depends upon the supply and reference voltages used for the ADC122S625. The ranges of VCM for differential and singleended operation are depicted in Figure 9 and Figure 10. Equations for calculating the minimum and maximum common mode voltages for differential and single-ended operation are shown in Table 1. 30055361 FIGURE 9. VCM range for Differential Input operation 15 www.national.com ADC122S625 seen as the first falling edge of SCLK. In the third condition, CS and SCLK go low simultaneously and the ADC122S625 immediately enters acquisition mode. While there is no timing restriction with respect to the falling edges of CS and the falling edge of SCLK, see Figure 5 for setup and hold time requirements for the falling edge of CS with respect to the rising edge of SCLK. TABLE 2. Ideal Output Code vs. Input Voltage Analog Input (+IN) − (−IN) VREF − 1.5 LSB 0111 1111 1111 3.1 CS Input The CS (chip select bar) is an active low input that is TTL and CMOS compatible. The ADC122S625 transitions from acquisition mode, to conversion mode, to power-down mode when CS is low and is always in power-down mode when CS is high. The falling edge of CS marks the beginning of a conversion where the input to Channel A and Channel B are tracked by the input sampling capacitor. The rising edge of CS marks the end of a conversion window. As a result, CS frames the conversion window and can be used to control the sample rate of the ADC122S625. While the SCLK frequency is limited to a range of 1.6 MHz to 6.4 MHz, the frequency of CS has no limitation. This allows a system designer to operate the ADC122S625 at sample rates approaching zero samples per second if conserving power is very important. See Burst Mode Operation for more details. Multiple conversions can occur within a given conversion frame with each conversion requiring thirty-two SCLK cycles. This is referred to as continuous conversion mode and is shown in Figure 2 of the Timing Diagram section. Proper operation requires that the fall of CS not occur simultaneously with a rising edge of SCLK. If the fall of CS occurs during the rising edge of SCLK, the data might be clocked out one bit early. Whether or not the data is clocked out early depends upon how close the CS transition is to the SCLK transition, the device temperature, and characteristics of the individual device. To ensure that the MSB is always clocked out at a given time (the 5th falling edge of SCLK), it is essential that the fall of CS always meet the timing requirement specified in the Timing Specification table. 7FF 2047 + 0.5 LSB 0000 0000 0001 001 1 − 0.5 LSB 0000 0000 0000 000 0 0V − 1.5 LSB 1111 1111 1111 FFF −1 −VREF + 0.5 LSB 1000 0000 0000 800 −2048 While data is output on the falling edges of SCLK, receiving systems have the option of capturing the data from the ADC122S625 on the subsequent rising or falling edge of SCLK. If a receiving system is going to capture data on the subsequent falling edges of SCLK, it is important to make sure that the minimum hold time after an SCLK falling edge (tDH) is acceptable. See Figure 4 for DOUT hold and access times. DOUT is enabled on the falling edge of CS and disabled on the rising edge of CS. If CS is raised prior to the 16th falling edge of SCLK, the current conversion is aborted and DOUT will go into its high impedance state. A new conversion will begin when CS is taken LOW. Applications Information OPERATING CONDITIONS We recommend that the following conditions be observed for operation of the ADC122S625: −40°C ≤ TA ≤ +105°C +4.5V ≤ VA ≤ +5.5V 1V ≤ VREF ≤ VA 1.6 MHz ≤ fSCLK ≤ 6.4 MHz VCM: See Section 2.3 4.0 POWER CONSUMPTION The architecture, design, and fabrication process allow the ADC122S625 to operate at conversion rates up to 200 kSPS while consuming very little power. The ADC122S625 consumes the least amount of power while operating in power down mode. For applications where power consumption is critical, the ADC122S625 should be operated in power down mode as often as the application will tolerate. To further reduce power consumption, stop the SCLK while CS is high. 3.2 SCLK Input The SCLK (serial clock) serves two purposes in the ADC122S625. It is used by the ADC122S625 as the conversion clock and it is used as the serial clock to output the conversion results. The SCLK input is TTL and CMOS compatible. Internal settling time requirements limit the maximum clock frequency while internal capacitor leakage limits the minimum clock frequency. The ADC122S625 offers guaranteed performance with the clock rates indicated in the Electrical Characteristics Table. 4.1 Burst Mode Operation Normal operation of the ADC122S625 requires the SCLK frequency to be thirty-two times the sample rate and the CS rate to be the same as the sample rate. However, in order to minimize power consumption in applications requiring sample rates below 50 kSPS, the ADC122S625 should be run with an SCLK frequency of 6.4 MHz and a CS rate as slow as the system requires. When this is accomplished, the ADC122S625 is operating in burst mode. The ADC122S625 enters into power down mode at the end of each conversion, minimizing power consumption. This causes the converter to spend the longest possible time in power down mode. Since power consumption scales directly with conversion rate, minimizing power consumption requires determining the lowest conversion rate that will satisfy the requirements of the system. 3.3 Data Output(s) The conversion result of Channel A and Channel B is output on DOUT, with the result of Channel A being output before the result of Channel B. The data output format of the ADC122S625 is binary, two’s complement, as shown in Table 2. This table indicates the ideal output code for a given input voltage and does not include the effects of offset, gain error, linearity errors, or noise. Each data output bit is output on the falling edges of SCLK. www.national.com 2's 2's 2's Complement Comp. Comp. Binary Output Hex Code Dec Code 16 5.1 Analog Power Supply Any ADC architecture is sensitive to spikes on the power supply, reference, and ground pins. These spikes may originate from switching power supplies, digital logic, high power devices, and other sources. Power to the ADC122S625 should be clean and well bypassed. A 0.1 µF ceramic bypass capacitor and a 1 µF to 10 µF capacitor should be used to bypass the ADC122S625 supply, with the 0.1 µF capacitor placed as close to the ADC122S625 package as possible. Since the ADC122S625 has a separate analog and reference pin, the user has two options. The first option is to tie the analog and reference supply pins together and power them with the same power supply. This is the most cost effective way of powering the ADC122S625 but it is also the least ideal. As stated previously, noise from the analog supply pin can couple into the reference supply pin and adversely affect performance. The other option involves the user powering the analog and reference supply pins with separate supply voltages. These supply voltages can have the same amplitude or they can be different. The only design constraint is that the reference supply voltage be less than the analog supply voltage. 6.0 APPLICATION CIRCUITS The following figures are examples of the ADC122S625 in typical application circuits. These circuits are basic and will generally require modification for specific circumstances. 6.1 Data Acquisition Figure 11 shows a basic low cost, low power data acquisition circuit. The analog supply pin is powered by the system +5V supply and the 2.5V reference voltage is generated by the LM4040-2.5 shunt reference. 5.2 Voltage Reference The reference source must have a low output impedance and needs to be bypassed with a minimum capacitor value of 0.1 µF. A larger capacitor value of 1 µF to 10 µF placed in parallel with the 0.1 µF is preferred. While the ADC122S625 draws very little current from the reference on average, there are higher instantaneous current spikes at the reference input. The reference input of the ADC122S625, like all A/D converters, does not reject noise or voltage variations. Keep this in mind if the reference voltage is derived from the power supply. Any noise and/or ripple from the supply that is not rejected by the external reference circuitry will appear in the digital results. The use of an active reference source is recommended. The LM4040 and LM4050 shunt reference families and the LM4132 and LM4140 series reference families are excellent choices for a reference source. 30055334 FIGURE 11. Low cost, low power Data Acquisition System 5.3 PCB Layout Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. The solution is to keep the analog circuitry separated from the digital circuitry and the clock line as short as possible. Digital circuits create substantial supply and ground current transients. The logic noise generated could have significant impact upon system noise performance. To avoid performance degradation of the ADC122S625 due to supply noise, avoid sharing the power supplies for VA and VREF with other digital circuity on the board. Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. However, to maximize accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep clock lines as short as possible and isolated from other lines, including other digital lines. In addition, the clock line should also be treated as a transmission line and be properly terminated. The analog input 6.2 Current Sensing Application Figure 12 shows an example of interfacing a pair of current transducers to the ADC122S625. The current transducers convert an input current into a voltage that is converted by the ADC122S625. Since the output voltage of the current transducers are single-ended and centered around a commonmode voltage of 2.5V, the ADC122S625 is configured with the output of the transducer driving the non-inverting inputs and the common-mode output voltage of the transducer driving the inverting input. The output of the transducer has an output range of ±2V around the common-mode voltage of 2.5V. As a result, a series reference voltage of 2.0V is connected to the ADC122S625. This will allow all of the codes of the ADC122S625 to be available for the application. This configuration of the ADC122S625 is referred to as a single-ended application of a differential ADC. All of the elements in the 17 www.national.com ADC122S625 should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to the reference input pin and ground should be connected to a very clean point in the ground plane. A single, uniform ground plane and the use of split power planes are recommended. The power planes should be located within the same board layer. All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed over the analog power plane. All digital circuitry and I/O lines should be placed over the digital power plane. Furthermore, the GND pin on the ADC122S625 and all the components in the reference circuitry and input signal chain that are connected to ground should be connected to the ground plane at a quiet point. Avoid connecting these points too close to the ground point of a microprocessor, microcontroller, digital signal processor, or other high power digital device. 5.0 POWER SUPPLY CONSIDERATIONS AND PCB LAYOUT For best performance, care should be taken with the physical layout of the printed circuit board. This is especially true with a low reference voltage or when the conversion rate is high. At high clock rates there is less time for settling, so it is important that any noise settles out before the conversion begins. ADC122S625 application are conveniently powered by the same +5V power supply, keeping circuit complexity and cost to a minimum. 30055338 FIGURE 12. Interfacing the ADC122S625 to a Current Transducer other hand, it offers no common-mode rejection of noise coming from the bridge sensors. The application circuit assumes the bridge sensors are powered from the same +5V power supply voltage as the analog supply pin on the ADC122S625. This has the benefit of providing the ideal common-mode input voltage for the ADC122S625 while keeping design complexity and cost to a minimum. The LM4132-4.1, a 4.1V series reference, is used as the reference voltage in the application. 6.3 Bridge Sensor Application Figure 13 shows an example of interfacing the ADC122S625 to a pair of bridge sensors. The application assumes that the bridge sensors require buffering and amplification to fully utilize the dynamic range of the ADC and thus optimize the performance of the entire signal path. The amplification stage for each ADC input consists of a pair of opamps from the LMP7704. The amplification stage offers the benefit of high input impedance and potentially high amplification. On the 30055335 FIGURE 13. Interfacing the ADC122S625 to Bridge Sensors www.national.com 18 ADC122S625 Physical Dimensions inches (millimeters) unless otherwise noted 10-Lead MSOP Order Number ADC122S625CIMM NS Package Number MUB10A 19 www.national.com ADC122S625 Dual 12-Bit, 50 kSPS to 200 kSPS, Simultaneous Sampling A/D Converter Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH www.national.com/webench Audio www.national.com/audio Analog University www.national.com/AU Clock Conditioners www.national.com/timing App Notes www.national.com/appnotes Data Converters www.national.com/adc Distributors www.national.com/contacts Displays www.national.com/displays Green Compliance www.national.com/quality/green Ethernet www.national.com/ethernet Packaging www.national.com/packaging Interface www.national.com/interface Quality and Reliability www.national.com/quality LVDS www.national.com/lvds Reference Designs www.national.com/refdesigns Power Management www.national.com/power Feedback www.national.com/feedback Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www.national.com/led PowerWise www.national.com/powerwise Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors Wireless (PLL/VCO) www.national.com/wireless THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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