LF13006/LF13007 Digital Gain Set General Description The LF13006 and LF13007 are precision digital gain sets used for accurately setting non-inverting op amp gains. Gains are set with a 3-bit digital word which can be latched in with WR and CS pins. All digital inputs are TTL and CMOS compatible. The LF13006 shown below will set binary scaled gains of 1, 2, 4, 8, 16, 32, 64, and 128. The LF13007 will set gains of 1, 2, 5, 10, 20, 50, and 100 (a common attenuator sequence). In addition, both versions have several taps and two uncommitted matching resistors that allow customization of the gain. The gains are set with precision thin film resistors. The low temperature coefficient of the thin film resistors and their excellent tracking result in gain ratios which are virtually independent of temperature. The LF13006, LF13007 used in conjunction with an amplifier not only satisfies the need for a digitally programmable amplifier in microprocessor based systems, but is also useful for discrete applications, eliminating the need to find 0.5% resistors in the ratio of 100 to 1 which track each other over temperature. Features Y Y Y Y Y Y TTL and CMOS compatible logic levels Microprocessor compatible Gain error 0.5% max Binary or scope knob gains Wide supply range a 5V to g 18V Packaged in 16-pin DIP Block Diagram and Typical Application (LF13006) TL/H/5114 – 1 Note: R j 15 kX Order Number LF13006N or LF13007N See NS Package Number N16A C1995 National Semiconductor Corporation TL/H/5114 RRD-B30M115/Printed in U. S. A. LF13006/LF13007 Digital Gain Set February 1995 Absolute Maximum Ratings Operating Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Operating Temperature Range Lead Temp. (Soldering, 10 seconds) Supply Voltage, Va to Vb Supply Voltage, V a to GND Voltage at Any Digital Input Analog Voltage Va b 40§ C to a 85§ C 260§ C 36V 25V V a to GND to (Vb a 2V) Electrical Characteristics (Note 2) Parameter Conditions Typ (Note 3) Tested Limit (Note 4) Design Limit (Note 5) Units 0.5 0.5 %(max) Gain Error AOUT e g 10V ANA GND e 0V IINPUTk10 nA 0.3 Gain Temperature Coefficient AOUT e g 10V ANA GND e 0V 0.001 Digital Input Voltage Low High %/§ C 1.4 1.6 0.8 2.0 0.8 2.0 V(max) V(min) b 38 0.0001 b 100 b 100 1 1 mA(max) mA(max) Digital Input Current Low High VIL e 0V VIH e 5V Positive Power Supply Current All Logic Inputs Low 2 5 5 mA(max) Negative Power Supply Current All Logic Inputs Low b 1.7 b5 b5 mA(max) Write Pulse Width, tW VIL e 0V, VIH e 5V 150 ns(min) Chip Select Set-Up Time, tCS VIL e 0V, VIH e 5V 250 ns(min) Chip Select Hold Time, tCH VIL e 0V, VIH e 5V 0 ns(min) DIG IN Set-Up Time, tDS VIL e 0V, VIH e 5V 150 ns(min) DIG IN Hold Time, tDH VIL e 0V, VIH e 5V 60 Switching Time for Gain Change (Note 4) ns(min) 200 ns(max) Switch On Resistance 3 Unit Resistance, R 15 12 – 18 R1 and R2 Mismatch 0.3 0.5 R1/R2 Temperature Coefficient 0.001 kX kX 0.5 %(max) %/§ C Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: Parameters are specified at V a e 15V and Vb e b 15V. Min V a to ground voltage is 5V. Min V a to Vb voltage is 5V. Boldface numbers apply over full operating temperature ranges. All other numbers apply at TA e Tj e 25§ C. Note 3: Typicals are at 25§ C and represent most likely parametric norm. Note 4: Guaranteed and 100% production tested. Note 5: Guaranteed (but not 100% production tested) over the operating temperature. These limits are not used to calculate outgoing quality levels. Note 6: Settling time for gain change is the switching time for gain change plus settling time (see section on Settling Time). Note 7: WR minimum high threshold voltage increases to 2.4V under the extreme conditions when all three digital inputs are simultaneously taken from 0V to 5V at a slew rate of greater than 500V/mS. Connection Diagram GAIN TABLE Dual-In-Line Package Gain Digital Input LF13006 LF13007 DIG in 3 DIG in 2 DIG in 1 AOUT BOUT AOUT BOUT 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 2 4 8 16 32 64 128 1 1.25 2.5 5 10 20 40 80 1 1.25 2 5 10 20 50 100 1 1 1.6 4 8 16 40 80 2 TL/H/5114 – 2 Switching Waveforms TL/H/5114 – 3 Block Diagram and Typical Application (Continued) (LF13007) TL/H/5114 – 4 Note: R j 15 kX 3 Typical Performance Characteristics Positive Power Supply Current vs Temperature Negative Power Supply Current vs Temperature Digital Input Threshold vs Temperature Logical 0 Input Bias Current vs Temperature Digital Input Threshold vs Supply Voltage Write Width, tw Data Set-Up Time, tDS Chip Select Set-Up Time, tcs TL/H/5114–5 4 Application Information use of a lead capacitor from the inverting input to the output of the amplifier. A lead capacitor is effective whenever the feedback around an amplifier is resistive, whether with discrete resistors or with the LF13006/7. It compensates for the feedback pole created by the parallel resistance and capacitance from the inverting input of the op amp to AC ground. Settling Time Test Circuit FLOW-THROUGH OPERATION THE LF13006, LF13007 can be operated with control lines CS and WR grounded. In this mode new data on the digital inputs will immediately set the new gain value. Input data cannot be latched in this mode. INPUT CURRENT Current flowing through the input (pin 2) due to bias current of the op amp will result in a gain error due to switch impedance. Normally this error is very small. For example, 10 nA of bias current flowing through 3 kX of switch resistance will result in an error of 30 mV at the summing node. However, applications that have significant current flowing through the input must take this effect into account. SETTLING TIME Settling time is a function of the particular op amp used with the LF13006/7 and the gain that is selected. It can be optimized and stability problems can be prevented through the TL/H/5114 – 6 Typical Settling Time Curves TL/H/5114 – 7 * Unstable at CL less than 2 pF Typical Applications Variable Capacitance Multiplier Variable Time Constant Filter Ceffective e C1(gain set Ý) Time constant e Note: Output swing at input op amp R C1 N N e setting of LF13006 is multiplied by set gain. Signal range may be limited. (range e 1 to 1) 128 TL/H/5114 – 9 TL/H/5114 – 8 5 Typical Applications (Continued) Switchable Gain of g 1 Programmable Current Source TL/H/5114 – 11 Note: Digital code e 000, VOUT e VIN; Digital code e 001, VOUT eb VIN Programmable Differential Amp TL/H/5114–10 1OUT e Ð 1.2V 1 120X gain set Ý ( Inverting Gains TL/H/5114–12 Inverting gain with high input impedance can be obtained with the LF13006, LF13007 by using the two TL/H/5114 – 13 on-board resistors and a dual op amp as shown. Note 1: Actual gain e set gain b 1 since LF13006s are in ‘‘inverting mode’’. Note 2: Set gain must be same on both LF13006s. 6 Typical Applications Altered Gain Range (Continued) One Octave per Bit Function Generator Variable Gains of Almost 1 TL/H/5114–14 TL/H/5114–16 TL/H/5114–15 GAINS AOUT 1 1.8 3 4.5 6 7.2 8 8.47 GAINS 9 1.8 1.29 1.125 1.059 1.029 1.014 1.007 BOUT 1 1.2 2 3 4 4.8 5.33 5.65 Programmable Instrumentation Amp Attenuator (0 dB to b42 dB in 6 dB steps) TL/H/5114 – 17 Note 1: VOUT e N (A b B), N e set gain. TL/H/5114 – 18 Note 2: All 10k resistors 0.1% matched. 7 LF13006/LF13007 Digital Gain Set Physical Dimensions inches (millimeters) Molded Dual-In-Line Package (N) Order Number LF13006N or LF13007N NS Package Number N16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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