DC Electrical Characteristics b40§ C s TA s a 85§ C unless otherwise specified (Continued) Parameter Conditions Maximum Input Current without Latchup (Note 4) Room Temperature RAM Retention Voltage, Vr 500 ns Rise and Fall Time (Min) Min Typ Max Units g 100 mA 2.0 V Input Capacitance Load Capacitance on D2 7 pF 1000 pF Note 1: Rate of voltage change must be less than 10 V/mS. Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open. Note 3: The HALT mode will stop CKI from oscillating in the RC and crystal configurations. HALT test conditions: L, and G0..G5 ports configured as outputs and set high. The D port set to zero. All inputs tied to VCC. The comparator and the Brown Out circuits are disabled. Note 4: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages greater than VCC and the pins will have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750X (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V. AC Electrical Characteristics b40§ C s TA s a 85§ C unless otherwise specified Parameter Instruction Cycle Time (tc) Crystal/Resonator Conditions Min 4.5V s VCC s 6.0V 2.5V s VCC s 4.5V 4.5V s VCC s 6.0V 2.5V s VCC s 4.5V 1 2.5 3 7.5 VCC Rise Time when Using Brown Out Frequency at Brown Out Reset CKI Frequency For Modular Output VCC e 0V to 6V 50 CKI Clock Duty Cycle (Note 5) Rise Time (Note 5) Fall Time (Note 5) fr e Max fr e 10 MHz ext. Clock fr e 10 MHz ext. Clock 40 4.5V s VCC s 6.0V 2.5V s VCC s 4.5V 4.5V s VCC s 6.0V 2.5V s VCC s 4.5V 200 500 60 150 R/C Oscillator Inputs tSetup tHold Output Propagation Delay tPD1, tPD0 SO, SK All Others Typ Max Units DC DC DC DC ms ms ms ms 4 4 ms MHz MHz 60 12 8 % ns ns ns ns ns ns RL e 2.2k, CL e 100 pF 4.5V s VCC s 6.0V 2.5V s VCC s 4.5V 4.5V s VCC s 6.0V 2.5V s VCC s 4.5V Input Pulse Width Interrupt Input High Time Interrupt Input Low Time Timer Input High Time Timer Input Low Time 0.7 1.75 1 5 ms ms ms ms 1 1 1 1 tc tc tc tc MICROWIRE Setup Time (tmWS) MICROWIRE Hold Time (tmWH) MICROWIRE Output Propagation Delay (tmPD) 20 56 ns ns Reset Pulse Width 1.0 220 ns ms Note 5: Parameter characterized but not production tested. 3 http://www.national.com AC Electrical Characteristics (Continued) TL/DD/11208 – 2 FIGURE 2. MICROWIRE/PLUS Timing Comparator DC and AC Characteristics 4V s VCC s 6V, b40§ C s TA s a 85§ C (Note 1) Parameters Conditions Input Offset Voltage Min 0.4V k VIN k VCC b 1.5V Input Common Mode Voltage Range Type Max Units g 10 g 25 mV 0.4 Voltage Gain VCC b 1.5 300k DC Supply Current (when enabled) VCC e 6.0V Response Time TBD mV Step, TBD mV Overdrive, 100 pF Load V V/V 250 mA 1 ms Note 1: For comparator output current characteristics see L-Port specs. Connection Diagrams TL/DD/11208 – 5 TL/DD/11208 – 4 Top View TL/DD/11208–3 Top View Order Number COPCJ822-XXX/N or COPCJ822-XXX/WM Order Number COPCJ820-XXX/N or COPCJ820-XXX/WM FIGURE 3. Connection Diagrams http://www.national.com 4 Top View Order Number COPCJ823-XXX/WM Typical Performance Characteristics DynamicÐIDD vs VCC (Crystal Clock Option) HaltÐIDD vs VCC (Brown Out Disabled) HaltÐIDD vs VCC (Brown Out Enabled) Ports L/G Weak Pull-Up Source Current Ports L/G Push-Pull Source Current Ports L/G Push-Pull Sink Current Ports L4–L7 Sink Current Port D Source Current Port D Sink Current Brown Out Voltage vs Temperature TL/DD/11208 – 28 5 http://www.national.com I/O bit can be individually configured under software control as shown below: COP820CJ Pin Assignment Port Pin Typ ALT Funct. 16 Pin L0 I/O MIWU/CMPOUT 5 L1 I/O MIWU/CMPINb 6 L2 I/O MIWU/CMPIN a 7 9 13 L3 I/O MIWU 8 10 14 L4 I/O MIWU 9 11 15 L5 I/O MIWU 10 12 16 L6 I/O MIWU 11 13 17 L7 I/O MIWU/MODOUT 12 14 18 G0 I/O INTR 17 25 G1 I/O 18 26 G2 I/O 19 27 G3 I/O TIO 20 28 G4 I/O SO 1 1 G5 I/O SK 16 2 2 G6 I SI 1 3 3 G7 I CKO 2 4 I0 I 7 I1 I 8 I2 I 9 I3 I 10 D0 O 19 D1 O 20 D2 O 21 D3 O 22 15 20 Pin 28 Pin Port L Config. Port L Data Port L Setup 7 11 8 12 0 0 1 1 0 1 0 1 Hi-Z Input (TRI-STATE) Input with Weak Pull-up Push-pull Zero Output Push-pull One Output Three data memory address locations are allocated for this port, one each for data register [00D0], configuration register [00D1] and the input pins [00D2]. Port L has the following alternate features: L0 MIWU or CMPOUT L1 MIWU or CMPINb L2 MIWU or CMPIN a L3 MIWU L4 MIWU (high sink current capability) L5 MIWU (high sink current capability) L6 MIWU (high sink current capability) L7 MIWU or MODOUT (high sink current capability) The selection of alternate Port L functions is done through registers WKEN [00C9] to enable MIWU and CNTRL2 [00CC] to enable comparator and modulator. All eight L-pins have Schmitt Triggers on their inputs. PORT G is an 8-bit port with 6 I/O pins (G0 – G5) and 2 input pins (G6, G7). All eight G-pins have Schmitt Triggers on the inputs. There are two registers associated with the G port: a data register and a configuration register. Therefore each G port bit can be individually configured under software control as shown below: 4 VCC 4 6 6 GND 13 15 23 CKI 3 5 5 RESET 14 16 24 Port G Data Port G Setup 0 0 1 1 0 1 0 1 Hi-Z Input (TRI-STATE) Input with Weak Pull-up Push-pull Zero Output Push-pull One Output Three data memory address locations are allocated for this port, one for data register [00D3], one for configuration register [00D5] and one for the input pins [00D6]. Since G6 and G7 are Hi-Z input only pins, any attempt by the user to configure them as outputs by writing a one to the configuration register will be disregarded. Reading the G6 and G7 configuration bits will return zeros. Note that the device will be placed in the Halt mode by writing a ‘‘1’’ to the G7 data bit. Six pins of Port G have alternate features: G0 INTR (an external interrupt) G3 TIO (timer/counter input/output) G4 SO (MICROWIRE serial data output) G5 SK (MICROWIRE clock I/O) G6 SI (MICROWIRE serial data input) G7 CKO crystal oscillator output (selected by mask option) or HALT restart input/general purpose input (if clock option is R/C or external clock) Pin Description VCC and GND are the power supply pins. CKI is the clock input. This can come from an external source, a R/C generated oscillator or a crystal (in conjunction with CKO). See Oscillator description. RESET is the master reset input. See Reset description. PORT I is a 4-bit Hi-Z input port. PORT L is an 8-bit I/O port. There are two registers associated with the L port: a data register and a configuration register. Therefore, each L http://www.national.com Port G Config. 6 Any bit of data memory can be directly set, reset or tested. All I/O and registers (except A and PC) are memory mapped; therefore, I/O bits and register bits can be directly and individually set, reset and tested, except the write once only bit (WDREN, WATCHDOG Reset Enable), and the unused and read only bits in CNTRL2 and WDREG registers. Pin Description (Continued) Pins G1 and G2 currently do not have any alternate functions. The selection of alternate Port G functions are done through registers PSW [00EF] to enable external interrupt and CNTRL1 [00EE] to select TIO and MICROWIRE operations. PORT D is a four bit output port that is preset when RESET goes low. One data memory address location is allocated for the data register [00DC]. Note: RAM contents are undefined upon power-up. Reset EXTERNAL RESET The RESET input pin when pulled low initializes the microcontroller. The user must insure that the RESET pin is held low until VCC is within the specified voltage range and the clock is stabilized. An R/C circuit with a delay 5x greater than the power supply rise time is recommended (Figure 4) . The device immediately goes into reset state when the RESET input goes low. When the RESET pin goes high the device comes out of reset state synchronously. The device will be running within two instruction cycles of the RESET pin going high. The following actions occur upon reset: Note: Care must be exercised with the D2 pin operation. At RESET, the external loads on this pin must ensure that the output voltages stay above 0.8 VCC to prevent the chip from entering special modes. Also keep the external loading on D2 to less than 1000 pF. Functional Description The internal architecture is shown in the block diagram. Data paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implementing the instruction set of the device. ALU and CPU Registers The ALU can do an 8-bit addition, subtraction, logical or shift operations in one cycle time. There are five CPU registers: A is the 8-bit Accumulator register PC is the 15-bit Program Counter register PU is the upper 7 bits of the program counter (PC) PL is the lower 8 bits of the program counter (PC) B is the 8-bit address register and can be auto incremented or decremented. X is the 8-bit alternate address register and can be auto incremented or decremented. SP is the 8-bit stack pointer which points to the subroutine stack (in RAM). B, X and SP registers are mapped into the on chip RAM. The B and X registers are used to address the on chip RAM. The SP register is used to address the stack in RAM during subroutine calls and returns. The SP must be preset by software upon initialization. Memory Port L TRI-STATE Port G TRI-STATE Port D HIGH PC CLEARED RAM Contents RANDOM with Power-OnReset UNAFFECTED with external Reset (power already applied) B, X, SP Same as RAM PSW, CNTRL1, CNTRL2 and WDREG Reg. CLEARED Multi-Input Wakeup Reg. WKEDG, WKEN WKPND CLEARED UNKNOWN Data and Configuration Registers for L & G CLEARED WATCHDOG Timer The memory is separated into two memory spaces: program and data. Prescaler/Counter each loaded with FF The device comes out of the HALT mode when the RESET pin is pulled low. In this case, the user has to ensure that the RESET signal is low long enough to allow the oscillator to restart. An internal 256 tc delay is normally used in conjunction with the two pin crystal oscillator. When the device comes out of the HALT mode through Multi-Input Wakeup, this delay allows the oscillator to stabilize. The following additional actions occur after the device comes out of the HALT mode through the RESET pin. If a two pin crystal/resonator oscillator is being used: PROGRAM MEMORY Program memory consists of 1024 x 8 ROM. These bytes of ROM may be instructions or constant data. The memory is addressed by the 15-bit program counter (PC). ROM can be indirectly read by the LAID instruction for table lookup. DATA MEMORY The data memory address space includes on chip RAM, I/O and registers. Data memory is addressed directly by the instruction or indirectly through B, X and SP registers. The device has 64 bytes of RAM. Sixteen bytes of RAM are mapped as ‘‘registers’’, these can be loaded immediately, decremented and tested. Three specific registers: X, B, and SP are mapped into this space, the other registers are available for general usage. RAM Contents 7 UNCHANGED Timer T1 and A Contents UNKNOWN WATCHDOG Timer Prescaler/Counter ALTERED http://www.national.com Functional Description (Continued) RESET as long as VCC is below the Brown Out Voltage. The Device will resume execution if VCC rises above the Brown Out Voltage. If a two pin crystal/resonator clock option is selected, the Brown Out reset will trigger a 256tc delay. This delay allows the oscillator to stabilize before the device exits the reset state. The delay is not used if the clock option is either R/C or external clock. The contents of data registers and RAM are unknown following a Brown Out reset. The external reset takes priority over Brown Out Reset and will deactivate the 256 tc cycles delay if in progress. The Brown Out reset takes priority over the WATCHDOG reset. The following actions occur as a result of Brown Out reset: If the external or RC Clock option is being used: RAM Contents UNCHANGED Timer T1 and A Contents UNCHANGED WATCHDOG Timer Prescaler/Counter ALTERED The external RESET takes priority over the Brown Out Reset. Note: If the RESET pin is pulled low while Brown Out occurs (Brown Out circuit has detected Brown Out condition), the external reset will not occur until the Brown Out condition is removed. External reset has priority only if VCC is greater than the Brown Out voltage. RC l 5 c Power Supply Rise Time TL/DD/11208–6 FIGURE 4. Recommended Reset Circuit WATCHDOG RESET With WATCHDOG enabled, the WATCHDOG logic resets the device if the user program does not service the WATCHDOG timer within the selected service window. The WATCHDOG reset does not disable the WATCHDOG. Upon WATCHDOG reset, the WATCHDOG Prescaler/ Counter are each initialized with FF Hex. The following actions occur upon WATCHDOG reset that are different from external reset. WDREN WATCHDOG Reset Enable bit UNCHANGED WDUDF WATCHDOG Underflow bit UNCHANGED Additional initialization actions that occur as a result of WATCHDOG reset are as follows: Port L TRI-STATE Port G TRI-STATE Port D HIGH PC CLEARED Ram Contents UNCHANGED B, X, SP UNCHANGED Data and Configuration Registers for L & G WATCHDOG Timer TRI-STATE Port D HIGH PC CLEARED RAM Contents RANDOM B, X, SP UNKNOWN PSW, CNTRL1, CNTRL2 and WDREG Registers CLEARED Multi-Input Wakeup Registers WKEDG, WKEN WKPND CLEARED UNKNOWN Data and Configuration Registers for L & G CLEARED WATCHDOG Timer Prescalar/Counter each loaded with FF Timer T1 and Accumulator Unknown data after coming out of the HALT (through Brown Out Reset) with any Clock option Brown Out Detection An on-board detection circuit monitors the operating voltage (VCC) and compares it with the minimum operating voltage specified. The Brown Out circuit is designed to reset the device if the operating voltage is below the Brown Out voltage (between 1.8V to 4.2V at b40§ C to a 85§ C). The Minimum operating voltage for the device is 2.5V with Brown Out disabled, but with BROWN OUT enabled the device is guaranteed to operate properly down to minimum Brown Out voltage (Max frequency 4 MHz), For temperature range of 0§ C to 70§ C the Brown Out voltage is expected to be between 1.9V to 3.9V. The circuit can be enabled or disabled by Brown Out mask option. If the device is intended to operate at lower VCC (lower than Brown Out voltage VBO max), the Brown Out circuit should be disabled by the mask option. The Brown Out circuit may be used as a power-up reset provided the power supply rise time is slower than 50 ms (0V to 6.0V). CLEARED UNKNOWN CLEARED Prescalar/Counter each loaded with FF BROWN OUT RESET The on-board Brown Out protection circuit resets the device when the operating voltage (VCC) is lower than the Brown Out voltage. The device is held in reset when VCC stays below the Brown Out Voltage. The device will remain in http://www.national.com TRI-STATE Port G Note: The development system will detect the BROWN OUT RESET externally and will force the RESET pin low. The Development System does not emulate the 256tc delay. PSW, CNTRL1 and CNTRL2 (except WDUDF Bit) Registers CLEARED Multi-Input Wakeup Registers WKEDG, WKEN WKPND Port L Note: Brown Out Circuit is active in HALT mode (with the Brown Out mask option selected). 8 Functional Description (Continued) Oscillator Circuits EXTERNAL OSCILLATOR CKI can be driven by an external clock signal provided it meets the specified duty cycle, rise and fall times, and input levels. CKO is available as a general purpose input G7 and/or Halt control. CRYSTAL OSCILLATOR By selecting CKO as a clock output, CKI and CKO can be connected to create a crystal controlled oscillator. Table I shows the component values required for various standard crystal values. R/C OSCILLATOR By selecting CKI as a single pin oscillator, CKI can make a R/C oscillator. CKO is available as a general purpose input and/or HALT control. Table II shows variation in the oscillator frequencies as functions of the component (R and C) values. TL/DD/11208 – 7 FIGURE 5. Clock Oscillator Configurations TABLE I. Crystal Oscillator Configuration R1 (kX) R2 (MX) C1 (pF) C2 (pF) CKI Freq. (MHz) Conditions 0 1 30 30 – 36 10 VCC e 5V 0 1 30 30 – 36 4 VCC e 5V 5.6 1 100 100 – 156 0.455 VCC e 5V TABLE II. RC Oscillator Configuration (Part-To-Part Variation) R (kX) C (pF) CK1 Freq. (MHz) Instr. Cycle (ms) Conditions 3.3 82 2.2 to 2.7 3.7 to 4.6 VCC e 5V 5.6 100 1.1 to 1.3 7.4 to 9.0 VCC e 5V 6.8 100 0.9 to 1.1 8.8 to 10.8 VCC e 5V 9 http://www.national.com Functional Description (Continued) is clocked only when the oscillator has a sufficiently large amplitude to meet the Schmitt trigger specs. This Schmitt trigger is not part of the oscillator closed loop. The start-up timeout from the WATCHDOG timer enables the clock signals to be routed to the rest of the chip. The delay is not activated when the device comes out of HALT mode through RESET pin. Also, if the clock option is either RC or External clock, the delay is not used, but the WATCHDOG Prescaler/-Counter contents are changed. The Development System will not emulate the 256tc delay. The RESET pin or Brown Out will cause the device to reset and start executing from address X’0000. A low to high transition on the G7 pin (if single pin oscillator is used) or MultiInput Wakeup will cause the device to start executing from the address following the HALT instruction. When RESET pin is used to exit the device from the HALT mode and the two pin crystal/resonator (CKI/CKO) clock option is selected, the contents of the Accumulator and the Timer T1 are undetermined following the reset. All other information except the WATCHDOG Prescaler/Counter contents is retained until continuing. If the device comes out of the HALT mode through Brown Out reset, the contents of data registers and RAM are unknown following the reset. All information except the WATCHDOG Prescaler/Counter contents is retained if the device exits the HALT mode through G7 pin or Multi-Input Wakeup. G7 is the HALT-restart pin, but it can still be used as an input. If the device is not halted, G7 can be used as a general purpose input. If the Brown Out Enable mask option is selected, the Brown Out circuit remains active during the HALT mode causing additional current to be drawn. Halt Mode The device is a fully static device. The device enters the HALT mode by writing a one to the G7 bit of the G data register. Once in the HALT mode, the internal circuitry does not receive any clock signal and is therefore frozen in the exact state it was in when halted. In this mode the chip will only draw leakage current (output current and DC current due to the Brown Out circuit if Brown Out is enabled). The device supports four different methods of exiting the HALT mode. The first method is with a low to high transition on the CKO (G7) pin. This method precludes the use of the crystal clock configuration (since CKO is a dedicated output). It may be used either with an RC clock configuration or an external clock configuration. The second method of exiting the HALT mode is with the multi-Input Wakeup feature on the L port. The third method of exiting the HALT mode is by pulling the RESET input low. The fourth method is with the operating voltage going below Brown Out voltage (if Brown Out is enabled by mask option). If the two pin crystal/resonator oscillator is being used and Multi-Input Wakeup or Brown Out causes the device to exit the HALT mode, the WAKEUP signal does not allow the chip to start running immediately since crystal oscillators have a delayed start up time to reach full amplitude and freuqency stability. The WATCHDOG timer (consisting of an 8-bit prescaler followed by an 8-bit counter) is used to generate a fixed delay of 256tc to ensure that the oscillator has indeed stabilized before allowing instruction execution. In this case, upon detecting a valid WAKEUP signal only the oscillator circuitry is enabled. The WATCHDOG Counter and Prescaler are each loaded with a value of FF Hex. The WATCHDOG prescaler is clocked with the tc instruction cycle. (The tc clock is derived by dividing the oscillator clock down by a factor of 10). The Schmitt trigger following the CKI inverter on the chip ensures that the WATCHDOG timer http://www.national.com Note: To allow clock resynchronization, it is necessary to program two NOP’s immediately after the device comes out of the HALT mode. The user must program two NOP’s following the ‘‘enter HALT mode’’ (set G7 data bit) instruction. 10 Functional Description (Continued) TABLE III MICROWIRE/PLUS MICROWIRE/PLUS is a serial synchronous bidirectional communications interface. The MICROWIRE/PLUS capability enables the device to interface with any of National Semiconductor’s MICROWIRE peripherals (i.e. A/D converters, display drivers, EEPROMS, etc.) and with other microcontrollers which support the MICROWIRE/PLUS interface. It consists of an 8-bit serial shift register (SIO) with serial data input (SI), serial data output (SO) and serial shift clock (SK). Figure 6 shows the block diagram of the MICROWIRE/PLUS interface. SL1 SL0 SK Cycle Time 0 0 1 0 1 x 2tc 4tc 8tc where, tc is the instruction cycle time. MICROWIRE/PLUS OPERATION Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS arrangement to start shifting the data. It gets reset when eight data bits have been shifted. The user may reset the BUSY bit by software to allow less than 8 bits to shift. The device may enter the MICROWIRE/PLUS mode either as a Master or as a Slave. Figure 7 shows how two device microcontrollers and several peripherals may be interconnected using the MICROWIRE/PLUS arrangement. Master MICROWIRE/PLUS Operation In the MICROWIRE/PLUS Master mode of operation the shift clock (SK) is generated internally by the device. The MICROWIRE/PLUS Master always initiates all data exchanges (Figure 7). The MSEL bit in the CNTRL register must be set to enable the SO and SK functions on the G Port. The SO and SK pins must also be selected as outputs by setting appropriate bits in the Port G configuration register. Table IV summarizes the bit settings required for Master mode of operation. TL/DD/11208 – 8 FIGURE 6. MICROWIRE/PLUS Block Diagram The shift clock can be selected from either an internal source or an external source. Operating the MICROWIRE/ PLUS interface with the internal clock source is called the Master mode of operation. Operating the MICROWIRE/ PLUS interface with an external shift clock is called the Slave mode of operation. The CNTRL register is used to configure and control the MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS , the MSEL bit in the CNTRL register is set to one. The SK clock rate is selected by the two bits, SL0 and SL1, in the CNTRL register. Table III details the different clock rates that may be selected. SLAVE MICROWIRE/PLUS OPERATION In the MICROWIRE/PLUS Slave mode of operation the SK clock is generated by an external source. Setting the MSEL bit in the CNTRL register enables the SO and SK functions on the G Port. The SK pin must be selected as an input and the SO pin selected as an output pin by appropriately setting up the Port G configuration register. Table IV summarizes the settings required to enter the Slave mode of operation. TL/DD/11208 – 23 FIGURE 7. MICROWIRE/PLUS Application 11 http://www.national.com MODE 1. TIMER WITH AUTO-LOAD REGISTER Functional Description (Continued) In this mode of operation, the timer T1 counts down at the instruction cycle rate. Upon underflow the value in the register R1 gets automatically reloaded into the timer which continues to count down. The timer underflow can be programmed to interrupt the microcontroller. A bit in the control register CNTRL enables the TIO (G3) pin to toggle upon timer underflows. This allows the generation of square-wave outputs or pulse width modulated outputs under software control (Figure 8) . The user must set the BUSY flag immediately upon entering the Slave mode. This will ensure that all data bits sent by the Master will be shifted properly. After eight clock pulses the BUSY flag will be cleared and the sequence may be repeated. TABLE IV G4 G5 G4 G5 G6 Fun. Fun. Fun. SO Int. SK SI MICROWIRE Master TRI-STATE Int. SK SI MICROWIRE Master Ext. SK SI MICROWIRE Slave TRI-STATE Ext. SK SI MICROWIRE Slave Config. Config. Bit Bit 1 1 0 1 1 0 0 0 SO Operation MODE 2. EXTERNAL COUNTER In this mode, the timer T1 becomes a 16-bit external event counter. The counter counts down upon an edge on the TIO pin. Control bits in the register CNTRL program the counter to decrement either on a positive edge or on a negative edge. Upon underflow the contents of the register R1 are automatically copied into the counter. The underflow can also be programmed to generate an interrupt (Figure 9) . Timer/Counter The device has a powerful 16-bit timer with an associated 16-bit register enabling it to perform extensive timer functions. The timer T1 and its register R1 are each organized as two 8-bit read/write registers. Control bits in the register CNTRL allow the timer to be started and stopped under software control. The timer-register pair can be operated in one of three possible modes. Table V details various timer operating modes and their requisite control settings. TL/DD/11208 – 24 FIGURE 8. Timer/Counter Auto Reload Mode Block Diagram TABLE V. Timer Operating Modes CNTRL Bits 765 Operation Mode T Interrupt Timer Counts On 000 001 010 011 100 101 110 111 External Counter w/Auto-Load Reg. External Counter w/Auto-Load Reg. Not Allowed Not Allowed Timer w/Auto-Load Reg. Timer w/Auto-Load Reg./Toggle TIO Out Timer w/Capture Register Timer w/Capture Register Timer Underflow Timer Underflow Not Allowed Not Allowed Timer Underflow Timer Underflow TIO Pos. Edge TIO Neg. Edge TIO Pos. Edge TIO Neg. Edge Not Allowed Not Allowed tc tc tc tc TL/DD/11208 – 29 FIGURE 9. Timer in External Event Counter Mode http://www.national.com 12 Timer/Counter (Continued) Watchdog MODE 3. TIMER WITH CAPTURE REGISTER Timer T1 can be used to precisely measure external frequencies or events in this mode of operation. The timer T1 counts down at the instruction cycle rate. Upon the occurrence of a specified edge on the TIO pin the contents of the timer T1 are copied into the register R1. Bits in the control register CNTRL allow the trigger edge to be specified either as a positive edge or as a negative edge. In this mode the user can elect to be interrupted on the specified trigger edge (Figure 10) . The device has an on-board 8-bit WATCHDOG timer. The timer contains an 8-bit READ/WRITE down counter clocked by an 8-bit prescaler. Under software control the timer can be dedicated for the WATCHDOG or used as a general purpose counter. Figure 12 shows the WATCHDOG timer block diagram. MODE 1: WATCHDOG TIMER The WATCHDOG is designed to detect user programs getting stuck in infinite loops resulting in loss of program control or ‘‘runaway’’ programs. The WATCHDOG can be enabled or disabled (only once) after the device is reset as a result of brown out reset or external reset. On power-up the WATCHDOG is disabled. The WATCHDOG is enabled by writing a ‘‘1’’ to WDREN bit (resides in WDREG register). Once enabled, the user program should write periodically into the 8-bit counter before the counter underflows. The 8-bit counter (WDCNT) is memory mapped at address 0CE Hex. The counter is loaded with n-1 to get n counts. The counter underflow resets the device, but does not disable the WATCHDOG. Loading the 8-bit counter initializes the prescaler with FF Hex and starts the prescaler/counter. Prescaler and counter are stopped upon counter underflow. Prescaler and counter are each loaded with FF Hex when the device goes into the HALT mode. The prescaler is used for crystal/resonator start-up when the device exits the HALT mode through Multi-Input Wakeup. In this case, the prescaler/counter contents are changed. TL/DD/11208 – 25 FIGURE 10. Timer Capture Mode Block Diagram TIMER PWM APPLICATION Figure 11 shows how a minimal component D/A converter can be built out of the Timer-Register pair in the Auto-Reload mode. The timer is placed in the ‘‘Timer with auto reload’’ mode and the TIO pin is selected as the timer output. At the outset the TIO pin is set high, the timer T1 holds the on time and the register R1 holds the signal off time. Setting TRUN bit starts the timer which counts down at the instruction cycle rate. The underflow toggles the TIO output and copies the off time into the timer, which continues to run. By alternately loading in the on time and the off time at each successive interrupt a PWM frequency can be easily generated. MODE 2: TIMER In this mode, the prescaler/counter is used as a timer by keeping the WDREN (WATCHDOG reset enable) bit at 0. The counter underflow sets the WDUDF (underflow) bit and the underflow does not reset the device. Loading the 8-bit counter (load n-1 for n counts) sets the WDTEN bit (WATCHDOG Timer Enable) to ‘‘1’’, loads the prescaler with FF, and starts the timer. The counter underflow stops the timer. The WDTEN bit serves as a start bit for the WATCHDOG timer. This bit is set when the 8-bit counter is loaded by the user program. The load could be as a result of WATCHDOG service (WATCHDOG timer dedicated for WATCHDOG function) or write to the counter (WATCHDOG timer used as a general purpose counter). The bit is cleared upon Brown Out reset, WATCHDOG reset or external reset. The bit is not memory mapped and is transparent to the user program. TL/DD/11208 – 26 FIGURE 11. Timer Application TABLE VI. WATCHDOG Control/Status HALT Mode WD Reset EXT/BOR Reset (Note 1) 8-Bit Prescaler FF FF FF FF 8-Bit WD Counter FF FF FF User Value Parameter Counter Load WDREN Bit Unchanged Unchanged 0 No Effect WDUDF Bit 0 Unchanged 0 0 Unchanged 0 0 1 WDTEN Signal Note 1: BOR is Brown Out Reset. 13 http://www.national.com Functional Description (Continued) WDREN: WD Reset Enable WDREN bit resides in a separate register (bit 0 of WDREG). This bit enables the WATCHDOG timer to generate a reset. The bit is cleared upon Brown Out reset, or external reset. The bit under software control can be written to only once (once written to, the hardware does not allow the bit to be changed during program execution). WDREN e 1 WATCHDOG reset is enabled. WDREN e 0 WATCHDOG reset is disabled. Table VI shows the impact of Brown Out Reset, WATCHDOG Reset, and External Reset on the Control/Status bits. CONTROL/STATUS BITS WDUDF: WATCHDOG Timer Underflow Bit This bit resides in the CNTRL2 Register. The bit is set when the WATCHDOG timer underflows. The underflow resets the device if the WATCHDOG reset enable bit is set (WDREN e 1). Otherwise, WDUDF can be used as the timer underflow flag. The bit is cleared upon Brown-Out reset, external reset, load to the 8-bit counter, or going into the HALT mode. It is a read only bit. TL/DD/11208 – 15 FIGURE 12. WATCHDOG Timer Block Diagram http://www.national.com 14 Modulator/Timer The Modulator/Timer contains an 8-bit counter and an 8-bit autoreload register (MODRL address 0CF Hex). The Modulator/Timer has two modes of operation, selected by the control bit MC3. The Modulator/Timer Control bits MC1, MC2 and MC3 reside in CNTRL2 Register. control bit by software loads the counter with the value of the autoreload register and starts the counter. The counter underflow toggles the (L7) output pin. The 50% duty cycle signal will be continuously generated until MC1 is reset by the user program. MODE 1: MODULATOR The Modulator is used to generate high frequency pulses on the modulator output pin (L7). The L7 pin should be configured as an output. The number of pulses is determined by the 8-bit down counter. Under software control the modulator input clock can be either CKI or tC. The tC clock is derived by dividing down the oscillator clock by a factor of 10. Three control bits (MC1, MC2, and MC3) are used for the Modulator/Timer output control. When MC2 e 1 and MC3 e 1, CKI is used as the modulator input clock. When MC2 e 0, and MC3 e 1, tC is used as the modulator input clock. The user loads the counter with the desired number of counts (256 max) and sets MC1 to start the counter. The modulator autoreload register is loaded with n-1 to get n pulses. CKI or tc pulses are routed to the modulator output (L7) until the counter underflows (Figure 13). Upon underflow the hardware resets MC1 and stops the counter. The L7 pin goes low and stays low until the counter is restarted by the user program. The user program has the responsibility to timeout the low time. Unless the number of counts is changed, the user program does not have to load the counter each time the counter is started. The counter can simply be started by setting the MC1 bit. Setting MC1 by software will load the counter with the value of the autoreload register. The software can reset MC1 to stop the counter. b. Variable Duty Cycle: When MC3 e 0 and MC2 e 1, a variable duty cycle PWM signal is generated on the L7 output pin. The counter is clocked by tC. In this mode the 16-bit timer T1 along with the 8-bit down counter are used to generate a variable duty cycle PWM signal. The timer T1 underflow sets MC1 which starts the down counter and it also sets L7 high (L7 should be configured as an output).When the counter underflows the MC1 control bit is reset and the L7 output will go low until the next timer T1 underflow. Therefore, the width of the output pulse is controlled by the 8-bit counter and the pulse duration is controlled by the 16-bit timer T1 (Figure 15). Timer T1 must be configured in ‘‘PWM Mode/Toggle TIO Out’’ (CNTRL1 Bits 7,6,5 e 101). Table VII shows the different operation modes for the Modulator/Timer. TABLE VII. Modulator/Timer Modes Control Bits in CNTRL2(00CC) MODE 2: PWM TIMER The counter can also be used as a PWM Timer. In this mode, an 8-bit register is used to serve as an autoreload register (MODRL). a. 50% Duty Cycle: When MC1 is 1 and MC2, MC3 are 0, a 50% duty cycle free running signal is generated on the L7 output pin (Figure 14). The L7 pin must be configured as an output pin. In this mode the 8-bit counter is clocked by tC. Setting the MC1 Operation Mode L7 Function MC3 MC2 MC1 0 0 0 Normal I/O 0 0 1 50% Duty Cycle Mode (Clocked by tc) 0 1 X Variable Duty Cycle Mode (Clocked by tc) Using Timer 1 Underflow 1 0 X Modulator Mode (Clocked by tc) 1 1 X Modulator Mode (Clocked by CKI) Note: MC1, MC2 and MC3 control bits are cleared upon reset. Internal Data Bus TL/DD/11208 – 16 FIGURE 13. Mode 1: Modulator Block Diagram/Output Waveform 15 http://www.national.com Modulator/Timer (Continued) TL/DD/11208 – 17 TL/DD/11208 – 18 FIGURE 14. Mode 2a: 50% Duty Cycle Output TL/DD/11208 – 19 TL/DD/11208 – 20 FIGURE 15. Mode 2b: Variable Duty Cycle Output http://www.national.com 16 the edge select change in WKEDG. Next, the associated WKPND bit should be cleared, followed by the associated WKEN bit being re-enabled. Comparator The device has one differential comparator. Ports L0 – L2 are used for the comparator. The output of the comparator is brought out to a pin. Port L has the following assignments: An example may serve to clarify this procedure. Suppose we wish to change the edge select from positive (low going high) to negative (high going low) for L port bit 5, where bit 5 has previously been enabled for an input. The program would be as follows: RBIT 5,WKEN SBIT 5,WKEDG RBIT 5,WKPND SBIT 5,WKEN If the L port bits have been used as outputs and then changed to inputs with Multi-Input Wakeup, a safety procedure should also be followed to avoid inherited pseudo wakeup conditions. After the selected L port bits have been changed from output to input but before the associated WKEN bits are enabled, the associated edge select bits in WKEDG should be set or reset for the desired edge selects, followed by the associated WKPND bits being cleared. This same procedure should be used following RESET, since the L port inputs are left floating as a result of RESET. The occurrence of the selected trigger condition for Multi-Input Wakeup is latched into a pending register called Reg:WKPND. The respective bits of the WKPND register will be set on the occurrence of the selected trigger edge on the corresponding Port L pin. The user has the responsibility of clearing these pending flags. Since the Reg:WKPND is a pending register for the occurrence of selected wakeup conditions, the device will not enter the HALT mode if any Wakeup bit is both enabled and pending. Setting the G7 data bit under this condition will not allow the device to enter the HALT mode. Consequently, the user has the responsibility of clearing the pending flags before attempting to enter the HALT mode. If a crystal oscillator is being used, the Wakeup signal will not start the chip running immediately since crystal oscillators have a finite start up time. The WATCHDOG timer prescaler generates a fixed delay to ensure that the oscillator has indeed stabilized before allowing the device to execute instructions. In this case, upon detecting a valid Wakeup signal only the oscillator circuitry and the WATCHDOG timer are enabled. The WATCHDOG timer prescaler is loaded with a value of FF Hex (256 counts) and is clocked from the tc instruction cycle clock. The tc clock is derived by dividing down the oscillator clock by a factor of 10. A Schmitt trigger following the CKI on chip inverter ensures that the WATCHDOG timer is clocked only when the oscillator has a sufficiently large amplitude to meet the Schmitt trigger specs. This Schmitt trigger is not part of the oscillator closed loop. The startup timeout from the WATCHDOG timer enables the clock signals to be routed to the rest of the chip. L0 Comparator output L1 Comparator negative input L2 Comparator positive input THE COMPARATOR STATUS/CONTROL BITS These bits reside in the CNTRL2 Register (Address 0CC) CMPEN Enables comparator (‘‘1’’ e enable) CMPRD Reads comparator output internally (CMPEN e 1, CMPOE e X) CMPOE Enables comparator output to pin L0 (‘‘1’’ e enable), CMPEN bit must be set to enable this function. If CMPEN e 0, L0 will be 0. The Comparator Select/Control bits are cleared on RESET (the comparator is disabled). To save power the program should also disable the comparator before the device enters the HALT mode. The user program must set up L0, L1 and L2 ports correctly for comparator Inputs/Output: L1 and L2 need to be configured as inputs and L0 as output. Multi-Input Wake Up The Multi-Input Wakeup feature is used to return (wakeup) the device from the HALT mode. Figure 16 shows the MultiInput Wakeup logic. This feature utilizes the L Port. The user selects which particular L port bit or combination of L Port bits will cause the device to exit the HALT mode. Three 8-bit memory mapped registers, Reg:WKEN, Reg:WKEDG, and Reg:WKPND are used in conjunction with the L port to implement the MultiInput Wakeup feature. All three registers Reg:WKEN, Reg:WKPND, and Reg:WKEDG are read/write registers, and are cleared at reset, except WKPND. WKPND is unknown on reset. The user can select whether the trigger condition on the selected L Port pin is going to be either a positive edge (low to high transition) or a negative edge (high to low transition). This selection is made via the Reg:WKEDG, which is an 8bit control register with a bit assigned to each L Port pin. Setting the control bit will select the trigger condition to be a negative edge on that particular L Port pin. Resetting the bit selects the trigger condition to be a positive edge. Changing an edge select entails several steps in order to avoid a pseudo Wakeup condition as a result of the edge change. First, the associated WKEN bit should be reset, followed by 17 http://www.national.com Multi-Input Wakeup (Continued) The software interrupt does not reset the GIE bit. This means that the controller can be interrupted by other interrupt sources while servicing the software interrupt. INTERRUPT PROCESSING The interrupt, once acknowledged, pushes the program counter (PC) onto the stack and the stack pointer (SP) is decremented twice. The Global Interrupt Enable (GIE) bit is reset to disable further interrupts. The microcontroller then vectors to the address 00FFH and resumes execution from that address. This process takes 7 cycles to complete. At the end of the interrupt subroutine, any of the following three instructions return the processor back to the main program: RET, RETSK or RETI. Either one of the three instructions will pop the stack into the program counter (PC). The stack pointer is then incremented twice. The RETI instruction additionally sets the GIE bit to re-enable further interrupts. Any of the three instructions can be used to return from a hardware interrupt subroutine. The RETSK instruction should be used when returning from a software interrupt subroutine to avoid entering an infinite loop. TL/DD/11208–21 FIGURE 16. Multi-Input Wakeup Logic Note: There is always the possibility of an interrupt occurring during an instruction which is attempting to reset the GIE bit or any other interrupt enable bit. If this occurs when a single cycle instruction is being used to reset the interrupt enable bit, the interrupt enable bit will be reset but an interrupt may still occur. This is because interrupt processing is started at the same time as the interrupt bit is being reset. To avoid this scenario, the user should always use a two, three, or four cycle instruction to reset interrupt enable bits. INTERRUPTS The device has a sophisticated interrupt structure to allow easy interface to the real world. There are three possible interrupt sources, as shown below. A maskable interrupt on external G0 input (positive or negative edge sensitive under software control) A maskable interrupt on timer carry or timer capture A non-maskable software/error interrupt on opcode zero DETECTION OF ILLEGAL CONDITIONS The device incorporates a hardware mechanism that allows it to detect illegal conditions which may occur from coding errors, noise, and ‘‘brown out’’ voltage drop situations. Specifically, it detects cases of executing out of undefined ROM area and unbalanced tack situations. Reading an undefined ROM location returns 00 (hexadecimal) as its contents. The opcode for a software interrupt is also ‘‘00’’. Thus a program accessing undefined ROM will cause a software interrupt. Reading an undefined RAM location returns an FF (hexadecimal). The subroutine stack on the device grows down for each subroutine call. By initializing the stack pointer to the top of RAM, the first unbalanced return instruction will cause the stack pointer to address undefined RAM. As a result the program will attempt to execute from FFFF (hexadecimal), which is an undefined ROM location and will trigger a software interrupt. INTERRUPT CONTROL The GIE (global interrupt enable) bit enables the interrupt function. This is used in conjunction with ENI and ENTI to select one or both of the interrupt sources. This bit is reset when interrupt is acknowledged. ENI and ENTI bits select external and timer interrupts respectively. Thus the user can select either or both sources to interrupt the microcontroller when GIE is enabled. IEDG selects the external interrupt edge (0 e rising edge, 1 e falling edge). The user can get an interrupt on both rising and falling edges by toggling the state of IEDG bit after each interrupt. IPND and TPND bits signal which interrupt is pending. After an interrupt is acknowledged, the user can check these two bits to determine which interrupt is pending. This permits the interrupts to be prioritized under software. The pending flags have to be cleared by the user. Setting the GIE bit high inside the interrupt subroutine allows nested interrupts. TL/DD/11208 – 27 FIGURE 17. Interrupt Block Diagram http://www.national.com 18 Control Registers The Half-Carry bit is also effected by all the instructions that effect the Carry flag. The flag values depend upon the instruction. For example, after executing the ADC instruction the values of the Carry and the Half-Carry flag depend upon the operands involved. However, instructions like SET C and RESET C will set and clear both the carry flags. Table XIII lists the instructions that effect the HC and the C flags. CNTRL1 REGISTER (ADDRESS 00EE) The Timer and MICROWIRE control register contains the following bits: SL1 and SL0 Select the MICROWIRE clock divide-by (00 e 2, 01 e 4, 1x e 8) IEDG MSEL External interrupt edge polarity select Selects G5 and G4 as MICROWIRE signals SK and SO respectively Used to start and stop the timer/counter (1 e run, 0 e stop) Timer T1 Mode Control Bit Timer T1 Mode Control Bit Timer T1 Mode Control Bit TRUN TC1 TC2 TC3 Bit 7 TC1 TC2 TC3 TRUN MSEL IEDG SL1 TABLE XIII. Instructions Effecting HC and C Flags Instr. HC Depends on Operands Depends on Operands SUBC Depends on Operands Depends on Operands SET C Set Set Bit 0 RESET C Set Set SL0 RRC TPND ENTI IPND BUSY ENI Depends on Operands Depends on Operands CNTRL2 REGISTER (ADDRESS 00CC) Bit 7 Bit 0 MC3 MC2 MC1 CMPEN CMPRD CMPOE WDUDF R/W R/W R/W MC3 MC2 MC1 CMPEN CMPRD CMPOE WDUDF Bit 0 C C Flag ADC PSW REGISTER (ADDRESS 00EF) The PSW register contains the following select bits: GIE Global interrupt enable (enables interrupts) ENI External interrupt enable BUSY MICROWIRE busy shifting flag PND External interrupt pending ENTI Timer T1 interrupt enable TPND Timer T1 interrupt pending (timer Underflow or capture edge) C Carry Flip/Flop HC Half-Carry Flip/Flop Bit 7 HC Flag R/W R/O R/W R/O unused Modulator/Timer Control Bit Modulator/Timer Control Bit Modulator/Timer Control Bit Comparator Enable Bit Comparator Read Bit Comparator Output Enable Bit WATCHDOG Timer Underflow Bit (Read Only) GIE WDREG REGISTER (ADDRESS 00CD) WDREN WATCHDOG Reset Enable Bit (Write Once Only) Bit 7 Bit 0 UNUSED 19 WDREN http://www.national.com Memory Map Addressing Modes All RAM, ports and registers (except A and PC) are mapped into data memory address space. There are ten addressing modes, six for operand addressing and four for transfer of control. TABLE IX. Memory Map OPERAND ADDRESSING MODES REGISTER INDIRECT This is the ‘‘normal’’ addressing mode for the chip. The operand is the data memory addressed by the B or X pointer. REGISTER INDIRECT WITH AUTO POST INCREMENT OR DECREMENT This addressing mode is used with the LD and X instructions. The operand is the data memory addressed by the B or X pointer. This is a register indirect mode that automatically post increments or post decrements the B or X pointer after executing the instruction. DIRECT The instruction contains an 8-bit address field that directly points to the data memory for the operand. IMMEDIATE The instruction contains an 8-bit immediate field as the operand. SHORT IMMEDIATE This addressing mode issued with the LD B,Ý instruction, where the immediate Ý is less than 16. The instruction contains a 4-bit immediate field as the operand. INDIRECT This addressing mode is used with the LAID instruction. The contents of the accumulator are used as a partial address (lower 8 bits of PC) for accessing a data operand from the program memory. Address Contents 00 to 2F On-chip RAM bytes (48 bytes) 30 to 7F Unused RAM Address Space (Reads as All Ones) 80 to BF Expansion Space for On-Chip EERAM (Reads Undefined Data) C0 to C7 C8 C9 CA CB CC CD CE CF Reserved MIWU Edge Select Register (Reg:WKEDG) MIWU Enable Register (Reg:WKEN) MIWU Pending Register (Reg:WKPND) Reserved Control2 Register (CNTRL2) WATCHDOG Register (WDREG) WATCHDOG Counter (WDCNT) Modulator Reload (MODRL) D0 D1 D2 D3 D4 D5 D6 D7 D8 to DB DC DD to DF Port L Data Register Port L Configuration Register Port L Input Pins (Read Only) Reserved for Port L Port G Data Register Port G Configuration Register Port G Input Pins (Read Only) Port I Input Pins (Read Only) Reserved for Port C Port D Data Register Reserved for Port D E0 to EF E0 to E7 E8 E9 EA EB EC ED EE EF On-Chip Functions and Registers Reserved for Future Parts Reserved MICROWIRE Shift Register Timer Lower Byte Timer Upper Byte Timer1 Autoreload Register Lower Byte Timer1 Autoreload Register Upper Byte CNTRL1 Control Register PSW Register F0 to FF FC FD FE On-Chip RAM Mapped as Registers X Register SP Register B Register TRANSFER OF CONTROL ADDRESSING MODES RELATIVE This mode is used for the JP instruction with the instruction field being added to the program counter to produce the next instruction address. JP has a range from b31 to a 32 to allow a one byte relative jump (JP a 1 is implemented by a NOP instruction). There are no ‘‘blocks’’ or ‘‘pages’’ when using JP since all 15 bits of the PC are used. ABSOLUTE This mode is used with the JMP and JSR instructions with the instruction field of 12 bits replacing the lower 12 bits of the program counter (PC). This allows jumping to any location in the current 4k program memory segment. ABSOLUTE LONG This mode is used with the JMPL and JSRL instructions with the instruction field of 15 bits replacing the entire 15 bits of the program counter (PC). This allows jumping to any location in the entire 32k program memory space. INDIRECT This mode is used with the JID instruction. The contents of the accumulator are used as a partial address (lower 8 bits of PC) for accessing a location in the program memory. The contents of this program memory location serves as a partial address (lower 8 bits of PC) for the jump to the next instruction. Reading other unused memory locations will return undefined data. http://www.national.com 20 Instruction Set Symbols [B] Memory indirectly addressed by B register [X] Memory indirectly addressed by X register Mem Direct address memory or [B] MemI Direct address memory or [B] or Immediate data Imm 8-bit Immediate data Reg Register memory: addresses F0 to FF (Includes B, X and SP) Bit Bit number (0 to 7) w Loaded with Ý Exchanged with REGISTER AND SYMBOL DEFINITIONS Registers A 8-bit Accumulator register B 8-bit Address register X 8-bit Address register SP 8-bit Stack pointer register PC 15-bit Program counter register PU upper 7 bits of PC PL lower 8 bits of PC C 1-bit of PSW register for carry HC Half Carry GIE 1-bit of PSW register for global interrupt enable Instruction Set A w A a MemI A w A a MemI a C, C w Carry HC w Half Carry A w A a MemI a C, C w Carry HC w Half Carry A w A and MemI A w A or MemI A w A xor MemI Compare A and MemI, Do next if A e MemI Compare A and MemI, Do next if A l MemI Do next if lower 4 bits of B i Imm Reg w Reg b 1, skip if Reg goes to 0 1 to bit, Mem (bit e 0 to 7 immediate) 0 to bit, Mem If bit, Mem is true, do next instr. ADD ADC add add with carry SUBC subtract with carry AND OR XOR IFEQ IFGT IFBNE DRSZ SBIT Logical AND Logical OR Logical Exclusive-OR IF equal IF greater than IF B not equal Decrement Reg. ,skip if zero Set bit RBIT Reset bit IFBIT If bit X LD A LD mem LD Reg Exchange A with memory Load A with memory Load Direct memory Immed. Load Register memory Immed. A Ý Mem A w MemI Mem w Imm Reg w Imm X X LD A LD A LD M Exchange A with memory [B] Exchange A with memory [X] Load A with memory [B] Load A with memory [X] Load Memory Immediate (B w B g 1) A Ý [B] (X w X g 1) A Ý [X] (B w B g 1) A w [B] (X w X g 1) A w [X] [B] w Imm (B w B g 1) CLRA INCA DECA LAID DCORA RRCA SWAPA SC RC IFC IFNC Clear A Increment A Decrement A Load A indirect from ROM DECIMAL CORRECT A ROTATE A RIGHT THRU C Swap nibbles of A Set C Reset C If C If not C Aw0 AwAa1 AwAb1 A w ROM(PU,A) A w BCD correction (follows ADC, SUBC) C x A7 x . . . x A0 x C A7 . . . A4 Ý A3 . . . A0 C w 1, HC w 1 C w 0, HC w 0 If C is true, do next instruction If C is not true, do next instruction JMPL JMP JP JSRL JSR JID RET RETSK RETI INTR NOP Jump absolute long Jump absolute Jump relative short Jump subroutine long Jump subroutine Jump indirect Return from subroutine Return and Skip Return from Interrupt Generate an interrupt No operation PC w ii (ii e 15 bits, 0 to 32k) PC11..0 w i (i e 12 bits) PC w PC a r (r is b31 to a 32, not 1) [SP] w PL,[SP-1] w PU,SP-2,PC w ii [SP] w PL,[SP-1] w PU,SP-2,PC11.. 0 w i PL w ROM(PU,A) SP a 2,PL w [SP],PU w [SP-1] SP a 2,PL w [SP],PU w [SP-1],Skip next instruction SP a 2,PL w [SP],PU w [SP-1],GIE w 1 [SP] w PL,[SPb1] w PU,SP-2,PC w 0FF PC w PC a 1 21 http://www.national.com http://www.national.com 22 JP -17 JP -16 JP -1 JP -0 D LD 0FF,Ý1 LD 0FE,Ýi LD 0FD,Ýi LD 0FC,Ýi LD 0FB,Ýi LD 0FA,Ýi LD 0F9,Ýi LD 0F8,Ýi LD 0F7,Ýi LD 0F6,Ýi LD 0F5,Ýi LD 0F4,Ýi LD 0F3,Ýi LD 0F2,Ýi LD 0F1,Ýi LD 0F0,Ýi C B * LD A, [X] DIR LD Md, Ýi LD A, [X b] LD A, [X a ] * NOP * X A, [X] * * X A, [X b] X A, [X a ] * RRCA A * LD A, [B] JSRL JMPL LD A, [Bb] LD A, [B a ] * * * X A, [B] JID LAID X A, [Bb] X A, [B a ] SC RC 9 * LD [B], Ýi LD A, Md X A,Md LD [Bb],Ýi LD [B a ],Ýi * LD A, Ýi OR A, Ýi XOR A, Ýi AND A, Ýi ADD A, Ýi IFGT A, Ýi IFEQ A, Ýi SUBC A, Ýi ADC A, Ýi 8 RETI RET RETSK * DECA INCA IFNC IFC OR A,[B] XOR A,[B] AND A,[B] ADD A,[B] IFGT A,[B] IFEQ A,[B] SUBC A,[B] ADC A, [B] Md is a directly addressed memory location DRSZ 0FF DRSZ 0FE DRSZ 0FD DRSZ 0FC DRSZ 0FB DRSZ 0FA DRSZ 0F9 DRSZ 0F8 DRSZ 0F7 DRSZ 0F6 DRSZ 0F5 DRSZ 0F4 DRSZ 0F3 DRSZ 0F2 DRSZ 0F1 DRSZ 0F0 is the immediate data JP -18 JP -2 i JP -19 JP -3 where, JP -20 JP -24 JP -8 JP -4 JP -25 JP -9 JP -21 JP -26 JP -10 JP -5 JP -27 JP -11 JP -22 JP -28 JP -12 JP -6 JP -29 JP -13 JP -23 JP -30 JP -14 JP -7 E JP -31 F JP -15 RBIT 7,[B] RBIT 6, [B] RBIT 5,[B] RBIT 4,[B] RBIT 3,[B] RBIT 2,[B] RBIT 1,[B] RBIT 0,[B] * DCORA SWAPA CLRA * * * * 6 5 LD B, 0 LD B, 1 LD B, 2 LD B, 3 LD B, 4 LD B, 5 LD B, 6 LD B, 7 LD B, 8 LD B, 9 LD B, 0A LD B, 0B LD B, 0C LD B, 0D LD B, 0E LD B, 0F 4 IFBNE 0F IFBNE 0E IFBNE 0D IFBNE 0C IFBNE 0B IFBNE 0A IFBNE 9 IFBNE 8 IFBNE 7 IFBNE 6 IFBNE 5 IFBNE 4 IFBNE 3 IFBNE 2 IFBNE 1 IFBNE 0 * is an unused opcode (see following table) SBIT 7,[B] SBIT 6, [B] SBIT 5,[B] SBIT 4,[B] SBIT 3,[B] SBIT 2,[B] SBIT 1,[B] SBIT 0,[B] IFBIT 7,[B] IFBIT 6,[B] IFBIT 5,[B] IFBIT 4,[B] IFBIT 3,[B] IFBIT 2,[B] IFBIT 1,[B] IFBIT 0,[B] 7 Bits 7 – 4 3 JSR 0F00 –0FFF JSR 0E00 –0EFF JSR 0D00 –0DFF JSR 0C00 –0CFF JSR 0B00 –0BFF JSR 0A00 –0AFF JSR 0900 –09FF JSR 0800 –08FF JSR 0700 –07FF JSR 0600 –06FF JSR 0500 –05FF JSR 0400 –04FF JSR 0300 –03FF JSR 0200 –02FF JSR 0100 –01FF JSR 0000 –00FF 2 JMP 0F00 –0FFF JMP 0E00 –0EFF JMP 0D00 –0DFF JMP 0C00 –0CFF JMP 0B00 –0BFF JMP 0A00 –0AFF JMP 0900 –09FF JMP 0800 –08FF JMP 0700 –07FF JMP 0600 –06FF JMP 0500 –05FF JMP 0400 –04FF JMP 0300 –03FF JMP 0200 –02FF JMP 0100 –01FF JMP 0000 –00FF 1 JP a 32 JP a 31 JP a 30 JP a 29 JP a 28 JP a 27 JP a 26 JP a 25 JP a 24 JP a 23 JP a 22 JP a 21 JP a 20 JP a 19 JP a 18 JP a 17 0 JP a 16 JP a 15 JP a 14 JP a 13 JP a 12 JP a 11 JP a 10 JP a 9 JP a 8 JP a 7 JP a 6 JP a 5 JP a 4 JP a 3 JP a 2 INTR F E D C B A 9 8 7 6 5 4 3 2 1 0 OPCODE LIST Bits 3 – 0 Instruction Execution Time Bytes and Cycles per Most instructions are single byte (with immediate addressInstruction ing mode instruction taking two bytes). The following table shows the number of bytes and cycles Most single instructions take one cycle time to execute. for each instruction in the format of byte/cycle. Skipped instructions require x number of cycles to be skipped, where x equals the number of bytes in the skipped instruction opcode. See the BYTES and CYCLES per INSTRUCTION table for details. Arithmetic Instructions (Bytes/Cycles) [B] Direct Immed. ADD ADC SUBC AND OR XOR IFEQ IFGT IFBNE DRSZ 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 2/2 2/2 2/2 2/2 2/2 2/2 2/2 2/2 SBIT RBIT IFBIT 1/1 1/1 1/1 1/3 3/4 3/4 3/4 Memory Transfer Instructions (Bytes/Cycles) Register Register Indirect Indirect Direct Immed. Auto Incr & Decr [B] [X] [B a , Bb] [X a , Xb] X A,* 1/1 LD A,* 1/1 LD B,Imm LD B,Imm LD Mem,Imm LD Reg,Imm 1/3 1/3 2/3 2/3 2/2 1/1 2/3 3/3 1/2 1/2 1/3 1/3 (If B k 16) (If B l 15) 2/2 2/3 * e l Memory location addressed by B or X or directly. Instructions Using A & C Instructions CLRA INCA DECA LAID DCORA RRCA SWAPA SC RC IFC IFNC Transfer of Control Instructions Bytes/Cycles Instructions 1/1 1/1 1/1 1/3 1/1 1/1 1/1 1/1 1/1 1/1 1/1 JMPL JMP JP JSRL JSR JID RET RETSK RETI INTR NOP 23 Bytes/Cycles 3/4 2/3 1/3 3/5 2/5 1/3 1/5 1/5 1/5 1/7 1/1 http://www.national.com Bytes and Cycles per Instruction (Continued) OPTION 2: BROWN OUT The following table shows the instructions assigned to unused opcodes. This table is for information only. The operations performed are subject to change without notice. Do not use these opcodes. Unused Opcode Instruction 60 61 62 63 67 8C 99 9F A7 A8 NOP NOP NOP NOP NOP RET NOP LD [B], Ýi X A, [B] NOP Unused Opcode Instruction A9 AF B1 B4 B5 B7 B9 BF NOP LD A, [B] C x HC NOP NOP X A, [X] NOP LD A, [X] e1 e2 Enable Brown Out Detection Disable Brown Out Detection OPTION 3: BONDING e1 e2 e3 e4 28-pin 20-pin 16-pin 28-pin DIP DIP/SO SO SO Development Support SUMMARY # iceMASTERTM : IM-COP8/400ÐFull feature in-circuit emulation for all COP8 products. A full set of COP8 Basic and Feature Family device and package specific probes are available. # COP8 Debug Module: Moderate cost in-circuit emulation and development programming unit. # COP8 Evaluation and Programming Unit: EPUCOP8780Ðlow cost in-circuit simulation and development programming unit. Option List The mask programmable options are listed below. The options are programmed at the same time as the ROM pattern to provide the user with hardware flexibility to a variety of oscillation and packaging configuration. # Assembler: COP8-DEV-IBMA. A DOS installable cross OPTION 1: CKI INPUT # C Compiler: COP8C. A DOS installable cross develop- e1 e2 e3 development Assembler, Linker, Librarian and Utility Software Development Tool Kit. ment Software Tool Kit. Crystal (CKI/IO) CKO for crystal configuration External (CKI/IO) CKO available as G7 input R/C (CKI/IO) CKO available as G7 input http://www.national.com # OTP/EPROM Programmer Support: Covering needs from engineering prototype, pilot production to full production environments. 24 Development Support (Continued) # Instruction by instruction memory/register changes dis- IceMASTER (IM) IN-CIRCUIT EMULATION The iceMASTER IM-COP8/400 is a full feature, PC based, in-circuit emulation tool developed and marketed by MetaLink Corporation to support the whole COP8 family of products. National is a resale vendor for these products. See Figure 18 for configuration. played on source window when in single step operation. # Single base unit and debugger software reconfigurable to support the entire COP8 family; only the probe personality needs to change. Debugger software is processor customized, and reconfigured from a master model file. # Processor specific symbolic display of registers and bit The iceMASTER IM-COP8/400 with its device specific COP8 Probe provides a rich feature set for developing, testing and maintaining product: level assignments, configured from master model file. # Real-time in-circuit emulation; full 2.4V–5.5V operation # Halt/Idle mode notification. # On-Line HELP customized to specific processor using range, full DC-10 MHz clock. Chip options are programmable or jumper selectable. # Includes a copy of COP8-DEV-IBMA assembler and link- master model file. er SDK. # Direct connection to application board by package compatible socket or surface assembly. IM Order Information # Full 32 kbytes of loadable programming space that over- Base Unit lays (replaces) the on-chip ROM or EPROM. On-chip RAM and I/O blocks are used directly or recreated on the probe as necessary. # Full 4k frame synchronous trace memory. Address, instruction, and 8 unspecified, circuit connectable trace lines. Display can be HLL source (e.g., C source), assembly or mixed. IM-COP8/400-1 iceMASTER Base Unit, 110V Power Supply IM-COP8/400-2 iceMASTER Base Unit, 220V Power Supply iceMASTER Probe # A full 64k hardware configurable break, trace on, trace MHW-840CJ20DWPC MHW-840CJ28DWPC off control, and pass count increment events. # Tool set integrated interactive symbolic debuggerÐsup- 20 DIP 28 DIP Adapters for SO Packages ports both assembler (COFF) and C Compiler (.COD) linked object formats. # Real time performance profiling analysis; selectable bucket definition. # Watch windows, content updated automatically at each MHW-SOIC16 16 SO MHW-SOIC20 20 SO MHW-SOIC28 28 SO execution break. TL/DD/11208 – 30 FIGURE 18. COP8 iceMASTER Environment 25 http://www.national.com Development Support (Continued) # Debugger software is processor customized, and recon- iceMASTER DEBUG MODULE (DM) The iceMASTER Debug Module is a PC based, combination in-circuit emulation tool and COP8 based OTP/EPROM programming tool developed and marketed by MetaLink Corporation to support the whole COP8 family of products. National is a resale vendor for these products. See Figure 19 for configuration. figured from a master model file. # Processor specific symbolic display of registers and bit level assignments, configured from master model file. # Halt/Idle mode notification. # Programming menu supports full product line of programmable OTP and EPROM COP8 products. Program data is taken directly from the overlay RAM. The iceMASTER Debug Module is a moderate cost development tool. It has the capability of in-circuit emulation for a specific COP8 microcontroller and in addition serves as a programming tool for COP8 OTP and EPROM product families. Summary of features is as follows: # Programming of 44 PLCC and 68 PLCC parts requires external programming adapters. # Includes wallmount power supply. # On-board VPP generator from 5V input or connection to # Real-time in-circuit emulation; full operating voltage external supply supported. Requires VPP level adjustment per the family programming specification (correct level is provided on an on-screen pop-down display). range operation, full DC-10 MHz clock. # All processor I/O pins can be cabled to an application development board with package compatible cable to socket and surface mount assembly. # On-line HELP customized to specific processor using # Full 32 kbytes of loadable programming space that over- # Includes a copy of COP8-DEV-IBMA assembler and link- master model file. lays (replaces) the on-chip ROM or EPROM. On-chip RAM and I/O blocks are used directly or recreated as necessary. er SDK. DM Order Information # 100 frames of synchronous trace memory. The display Debug Module Unit can be HLL source (C source), assembly or mixed. The most recent history prior to a break is available in the trace memory. COP8-DM/840CJ Cable Adapters # Configured break points; uses INTR instruction which is modestly intrusive. # Software-only supported features are selectable. # Tool set integrated interactive symbolic debuggerÐsup- DM-COP8/20D 20 DIP DM-COP8/28D 28 DIP Adapters for SO Package ports both assembler (COFF) and C Compiler (.COD) SDK linked object formats. MHW-SOIC16 16 SO # Instruction by instruction memory/register changes dis- MHW-SOIC20 20 SO MHW-SOIC28 28 SO played when in single step operation. TL/DD/11208 – 31 FIGURE 19. COP8-DM Environment http://www.national.com 26 Development Support (Continued) COP8 C COMPILER COP8 ASSEMBLER/LINKER SOFTWARE DEVELOPMENT TOOL KIT A C Compiler is developed and marketed by Byte Craft Limited. The COP8C compiler is a fully integrated development tool specifically designed to support the compact embedded configuration of the COP8 family of products. Features are summarized as follows: National Semiconductor offers a relocatable COP8 macro cross assembler, linker, librarian and utility software development tool kit. Features are summarized as follows: # Basic and Feature Family instruction set by ‘‘device’’ type. # # # # # # # # ANSI C with some restrictions and extensions that optimize development for the COP8 embedded application. Nested macro capability. Extensive set of assembler directives. Supported on PC/DOS platform. Generates National standard COFF output files. Integrated Linker and Librarian. # BITS data type extension. Register declaration Ýpragma with direct bit level definitions. # C language support for interrupt routines. # Expert system, rule based code generation and optimization. Integrated utilities to generate ROM code file outputs. DUMPCOFF utility. This product is integrated as a part of MetaLink tools as a development kit, fully supported by the MetaLink debugger. It may be ordered separately or it is bundled with the MetaLink products at no additional cost. # Performs consistency checks against the architectural definitions of the target COP8 device. # Generates program memory code. # Supports linking of compiled object or COP8 assembled object formats. # Global optimization of linked code. # Symbolic debug load format fully source level supported Order Information by the MetaLink debugger. Assembler SDK COP8-DEV-IBMA Assembler SDK on installable 3.5× PC/DOS Floppy Disk Drive format. Periodic upgrades and most recent version is available on National’s BBS and Internet. Approved List Manufacturer North America Europe Asia BP Microsystems (800) 225-2102 (713) 688-4600 Fax: (713) 688-0920 a 49-8152-4183 a 49-8856-932616 a 852-234-16611 a 852-2710-8121 Data I/O (800) 426-1045 (206) 881-6444 Fax: (206) 882-1043 a 44-0734-440011 Call North America HI–LO (510) 623-8860 Call Asia a 886-2-764-0215 Fax: a 886-2-756-6403 ICE Technology (800) 624-8949 (919) 430-7915 a 44-1226-767404 Fax: 0-1226-370-434 MetaLink (800) 638-2423 (602) 926-0797 Fax: (602) 693-0681 a 49-80 9156 96-0 Fax: a 49-80 9123 86 a 852-737-1800 Systems General (408) 263-6667 a 41-1-9450300 a 886-2-917-3005 Fax: a 886-2-911-1283 Needhams (916) 924-8037 Fax: (916) 924-8065 27 http://www.national.com Development Support (Continued) SINGLE CHIP OTP/EMULATOR SUPPORT DIAL-A-HELPER BBS via a Standard Modem The COP8 family is supported by single chip OTP emulators. For detailed information refer to the emulator specific datasheet and the emulator selection table below: Modem: CANADA/U.S.: (800) NSC-MICRO (800) 672-6427 EUROPE: Baud: Set-up: OTP Emulator Ordering Information Device Number Clock Option Package Emulates COP87L22CJN-1N COP87L22CJN-2N COP87L22CJN-3N Crystal External R/C 20 DIP 20 DIP 20 DIP COP822CJ COP822CJ COP822CJ COP87L22CJM-1N COP87L22CJM-2N COP87L22CJM-3N Crystal External R/C 20 SO 20 SO 20 SO COP822CJ COP822CJ COP822CJ COP87L20CJN-1N COP87L20CJN-2N COP87L20CJN-3N Crystal External R/C 28 DIP 28 DIP 28 DIP COP820CJ COP820CJ COP820CJ COP87L20CJM-1N COP87L20CJM-2N COP87L20CJM-3N Crystal External R/C 28 SO 28 SO 28 SO COP820CJ COP820CJ COP820CJ Operation: DIAL-A-HELPER via FTP ftp nscmicro.nsc.com user: anonymous password: username @ yourhost.site.domain DIAL-A-HELPER via a WorldWide Web Browser ftp://nscmicro.nsc.com National Semiconductor on the WorldWide Web See us on the WorldWide Web at: http://www.national.com CUSTOMER RESPONSE CENTER Complete product information and technical support is available from National’s customer response centers. INDUSTRY WIDE OTP/EPROM PROGRAMMING SUPPORT Programming support, in addition to the MetaLink development tools, is provided by a full range of independent approved vendors to meet the needs from the engineering laboratory to full production. CANADA/U.S.: Tel: EUROPE: AVAILABLE LITERATURE For more information, please see the COP8 Basic Family User’s Manual, Literature Number 620895, COP8 Feature Family User’s Manual, Literature Number 620897 and National’s Family of 8-bit Microcontrollers COP8 Selection Guide, Literature Number 630009. DIAL-A-HELPER SERVICE Dial-A-Helper is a service provided by the Microcontroller Applications group. The Dial-A-Helper is an Electronic Information System that may be accessed as a Bulletin Board System (BBS) via data modem, as an FTP site on the Internet via standard FTP client application or as an FTP site on the Internet using a standard Internet browser such as Netscape or Mosaic. The Dial-A-Helper system provides access to an automated information storage and retrieval system. The system capabilities include a MESSAGE SECTION (electronic mail, when accessed as a BBS) for communications to and from the Microcontroller Applications Group and a FILE SECTION which consists of several file areas where valuable application software and utilities could be found. http://www.national.com ( a 49) 0-8141-351332 14.4k Length: 8-Bit Parity: None Stop Bit: 1 24 Hours, 7 Days (800) 272-9959 email: support @ tevm2.nsc.com email: europe.support @ nsc.com Deutsch Tel: a 49 (0) 180-530 85 85 English Tel: a 49 (0) 180-532 78 32 Fran3ais Tel: a 49 (0) 180-532 93 58 Italiano Tel: a 49 (0) 180-534 16 80 JAPAN: Tel: a 81-043-299-2309 S.E. ASIA: Beijing Tel: ( a 86) 10-6856-8601 Shanghai Tel: ( a 86) 21-6415-4092 Hong Kong Tel: ( a 852) 2737-1600 28 Korea Tel: ( a 82) 2-3771-6909 Malaysia Tel: ( a 60-4) 644-9061 Singapore Tel: ( a 65) 255-2226 Taiwan Tel: a 886-2-521-3288 AUSTRALIA: Tel: ( a 61) 3-9558-9999 INDIA: Tel: ( a 91) 80-559-9467 29 http://www.national.com Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Molded Package S.O. (M) Order Number COPCJ823-XXX/WM NS Package Number M16B 20-Lead Surface Mount Package (M) Order Number COPCJ822-XXX/WM NS Package Number M20B http://www.national.com 30 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Molded Package S.O. (M) Order Number COPCJ820-XXX/WM NS Package Number M28B 20-Lead Molded Dual-In-Line Package (N) Order Number COPCJ822-XXX/N NS Package Number N20A 31 http://www.national.com COP820CJ/COP822CJ/COP823CJ 8-Bit Microcontroller with Multi-Input Wake Up and Brown Out Detector Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Molded Dual-In-Line Package (N) Order Number COPCJ820-XXX/N NS Package Number N28B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 http://www.national.com 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: a49 (0) 180-530 85 86 Email: europe.support @ nsc.com Deutsch Tel: a49 (0) 180-530 85 85 English Tel: a49 (0) 180-532 78 32 Fran3ais Tel: a49 (0) 180-532 93 58 Italiano Tel: a49 (0) 180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2308 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.