5497/DM7497 Synchronous Modulo-64 Bit Rate Multiplier General Description The ’97 contains a synchronous 6-stage binary counter and six decoding gates that serve to gate the clock through to the output at a sub-multiple of the input frequency. The output pulse rate, relative to the clock frequency, is determined by signals applied to the Select (S0–S5) inputs. Both true and complement outputs are available, along with an enable input for each. A Count Enable input and a Terminal Count output are provided for cascading two or more packages. An asynchronous Master Reset input prevents counting and resets the counter. Connection Diagram Logic Symbol Dual-In-Line Package TL/F/9780 – 2 VCC e Pin 16 GND e Pin 8 TL/F/9780 – 1 Order Number 5497DMQB, 5497FMQB or DM7497N See NS Package Number J16A, N16E or W16A Pin Names S0–S5 EZ EY CE CP MR OZ Oy TC C1995 National Semiconductor Corporation TL/F/9780 Description Rate Select Inputs OZ Enable Input (Active LOW) OY Enable Input Count Enable Input (Active LOW) Clock Pulse Input (Active Rising Edge) Asynchronous Master Reset Input (Active HIGH) Gated Clock Output (Active LOW) Complement Output (Active HIGH) Terminal Count Output (Active LOW) RRD-B30M115/Printed in U. S. A. 5497/DM7497 Synchronous Modulo-64 Bit Rate Multiplier June 1989 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for acutual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range b 55§ C to a 125§ C 54 DM74 0§ C to a 70§ C b 65§ C to a 150§ C Storage Temperature Range Recommended Operating Conditions Symbol 5497 Parameter DM7497 Units Min Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current IOL Low Level Output Current TA Free Air Operating Temperature ts(L) Setup Time LOW, CE to CP Rising 25 25 ns th(H) Hold Time HIGH, CE to CP Rising 0 0 ns th(L) Hold Time LOW, CE to CP Falling 0 0 ns tw(H) CP Pulse Width HIGH 20 20 ns tw(L) CP Pulse Width LOW 20 tw(H) MR Pulse Width HIGH 15 2 2 V 0.8 0.8 V b 0.4 b 0.4 mA 16 mA 16 b 55 V 125 0 70 §C ns 15 ns Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ (Note 1) Max Units b 1.5 V VI Input Clamp Voltage VCC e Min, II e b12 mA VOH High Level Output Voltage VCC e Min, IOH e Max, VIL e Max VOL Low Level Output Voltage VCC e Min, IOL e Max, VIH e Min II Input Current @ Max Input Voltage VCC e Max, VI e 5.5V IIH High Level Input Current VCC e Max, VI e 2.4V Clock Inputs DM74 40 54 80 VCC e Max, VI e 0.4V Clock Inputs DM74 b 1.6 54 b 3.2 Short Circuit Output Current VCC e Max (Note 2) 54 b 20 b 55 DM74 b 18 b 55 Supply Current With Outputs High VCC e Max IIL IOS ICC Low Level Input Current 2.4 3.4 0.2 V 0.4 V 1 mA 120 2 mA mA mA mA Switching Characteristics VCC e a 5.0V, TA e a 25§ C (See Section 1 for waveforms and load configurations) Symbol Parameter 5497 DM7497 CL e 15 pF RL e 400X CL e 15 pF RL e 400X Min Max 25 Min Units Max fmax Maximum Clock Frequency tPLH tPHL Propagation Delay EZ to OZ 18 23 25 18 23 MHz ns tPLH tPHL Propagation Delay EZ to OY 30 33 30 33 ns tPLH tPHL Propagation Delay EY to OY 14 10 14 10 ns tPLH tPHL Propagation Delay Sn to OY 23 23 23 23 ns tPLH tPHL Propagation Delay Sn to OZ 14 14 14 14 ns tPLH tPHL Propagation Delay CP to OY 39 30 39 30 ns tPLH tPHL Propagation Delay CP to OZ 18 26 18 26 ns tPLH tPHL Propagation Delay CP to TC 35 33 30 33 ns tPLH tPHL Propagation Delay CE to TC 25 21 20 21 ns tPLH Propagation Delay MR to OY 43 36 ns tPHL Propagation Delay MR to OZ 34 23 ns Timing Diagrams TL/F/9780 – 5 TL/F/9780 – 6 3 Functional Description ing pulses passed by two or more of the AND gates. The Pulse Pattern Table indicates the output pattern for several values of m. In each row, a one means that the OZ output will be HIGH during that entire clock period, while a zero means that OZ will be LOW when the clock is LOW in that period. The first column in the output field coincides with the ‘‘all zeroes’’ condition of the counter, while the last column represents the ‘‘all ones’’ condition. The pulse pattern for any particular value of m can be deduced by factoring it into the sum of appropriate powers of two (e.g. 19 e 16 a 2 a 1) and combining the pulses (i.e., the zeroes) shown for each for the relevant powers of two (e.g. for m e 16, 2 and 1). The Y output OY is the complement of OZ and is thus normally LOW. A LOW signal on the Y-enable input, EY, disables Oy. To expand the multiplier to 12-bit rate select, two packages can be cascaded as shown in Figure A . Both circuits operate from the basic clock, with the TC output of the first acting to enable both counting and the output pulses of the second package. Thus the second counter advances at only (/64 the rate of the first and a full cycle of the two counters combined requires 4096 clocks. Each rate select input of the first package has 64 times the weight of its counterpart in the second package. The ’97 contains six JK flip-flops connected as a synchronous modulo-64 binary counter. A LOW signal on the Count Enable (CE) input permits counting, with all state changes initiated simultaneously by the rising edge of the clock. When the count reaches maximum (63), with all Qs HIGH, the Terminal Count (TC) output will be LOW if CE is LOW. A HIGH signal on Master Reset (MR) resets the flip-flops and prevents counting, although output pulses can still occur if the clock is running, EZ is LOW and S5 is HIGH. The flip-flop outputs are decoded by a 6-wide AND-OR-INVERT gate. Each AND gate also contains the buffered and inverted CP and Z-enable (EZ) functions, as well as one of the Select (S0 – S5) inputs. The Z output, OZ is normally HIGH and goes LOW when CP and EZ are LOW and any of the AND gates has its other inputs HIGH. The AND gates are enabled by the counter at different times and different rates relative to the clock. For example, the gate to which S5 is connected is enabled during every other clock period, assuming S5 is HIGH. Thus, during one complete cycle of the counter (64 clocks) the S5 gate is enabled 32 times and can therefore gate 32 clocks per cycle to the output. The S4 gate is enabled 16 times per cycle, the S3 gate 8 times per cycle, etc. The output pulse rate thus depends on the clock rate and which of the S0–S5 inputs is HIGH. fout e m # fin 64 fout e Where: m e S5 # 25 a S4 # 24 a S3 # 23 a S2 # 22 a S1 # 21 a S0 # 20 Thus by appropriate choice of signals applied to the S0–S5 inputs, the output pulse rate can range from (/64 to $*/64 of the clock rate, as suggested in Rate Select Table. There is no output pulse when the counter is in the ‘‘all ones’’ condition. When m is 1, 2, 4, 8, 16 or 32, the output pulses are evenly spaced, assuming that the clock frequency is constant. For any other value of m the output pulses are not evenly spaced, since the pulse train is formed by interleav- m1 a m2 # fin 64 # 64 Where: m1 e S5 # 211 a S4 # 210 a S3 # 29 a S2 # 28 a S1 # 27 a S0 # 26 (first package) m2 e S5 # 25 a S4 # 24 a S3 # 23 a S2 # 22 a S1 # 21 a S0 # 20 (second package) Combined output pulses are obtained in Figure A by letting the Z output of the first circuit act as the Y-enable function for the second, with the interleaved pulses obtained from the Y output of the second package being opposite in phase to the clock. TL/F/9780 – 3 FIGURE A. Cascading for 12-Bit Rate Select 4 Functional Description (Continued) Mode and Rate Select Table (Note 1) MR CE EZ S5 Inputs S4 S3 S2 S1 S0 Clock Pulses H L L X L L H L L X L L X L L X L L X L L X L L X L H L L L L L L L L L L L L L L L L L L L H L L H L L H L L H L L L L L L L L L L L L L L L H H H H L H H L L H H L L H H L L H H L Outputs Notes EY OY OZ TC X 64 64 H H H L L 1 H H 1 H 1 1 2 3 3 L L L L 64 64 64 64 H H H H 2 4 8 16 2 4 8 16 1 1 1 1 3 3 3 3 L H H L 64 64 64 64 H H L H 32 63 H 40 32 62 63 40 1 1 1 1 3 3 4 5 H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Note 1: Numerals indicate number of pulses per cycle. Note 2: This is a simplified illustration of the clear function. CP and EZ also affect the logic level of OY and OZ. A LOW signal on EY will cause OY to remain HIGH. Note 3: Each rate illustrated assumes S0–S5 are constant throughout the cycle; however, these illustrations in no way prohibit variablerate operation. Note 4: EY is used to inhibit output Y. fin (32 a 8) fin 40 fin e e e 0.625 fin Note 5: fout e m # 64 64 64 Pulse Pattern Table m Output Pulse Pattern at OZ 1 2 3 4 5 1111111111111111111111111111111011111111111111111111111111111111 1111111111111110111111111111111111111111111111101111111111111111 1111111111111110111111111111111011111111111111101111111111111111 1111111011111111111111101111111111111110111111111111111011111111 1111111011111111111111101111111011111110111111111111111011111111 6 8 10 12 14 1111111011111110111111101111111111111110111111101111111011111111 1110111111101111111011111110111111101111111011111110111111101111 1110111111101111111011111110111111101111111011101110111111101111 1110111011101111111011101110111111101110111011111110111011101111 1110111011101110111011101110111111101110111011101110111011101111 16 20 24 28 32 1011101110111011101110111011101110111011101110111011101110111011 1011101010111011101110101011101110111010101110111011101110111011 1010101110101011101010111010101110101011111010111010101110101011 1010101010101011101010101010101110101010101010111010101010101011 010101... . . .0 1 0 1 5 Logic Diagram TL/F/9780 – 4 6 Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number 5497DMQB NS Package Number J16A 16-Lead Molded Dual-In-Line Package (N) Order Number DM7497N NS Package Number N16E 7 5497/DM7497 Synchronous Modulo-64 Bit Rate Multiplier Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number 5497FMQB NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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