ZILOG Z8622912PSC

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Preprogrammed to Provide Full Compliance with
EIA–608 Specifications for Extended Data Services
Minimal Communications and Control Overhead Provide Simple Implementation of Violence Blocking,
Closed Captioning, and Auto Clock Set Features
•
Automatic Extraction and Serial Output of Special
XDS Packets (Time of Day, Local Time Zone, and
Program Blocking)
Programmable, On-Screen Display (OSD) for Creating Full Screen OSD or Captions inside a Picture-inPicture (PiP) Window
•
User-Programmable Horizontal Display Position for
easy OSD Centering and Adjustment
•
•
I2C Serial Data and Control Communication
•
Complete Stand-Alone Line 21 Decoder for ClosedCaptioned and Extended Data Services (XDS)
•
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Programmable XDS Filter for a Specific XDS Packet
Cost-Effective Solution for NTSC Violence Blocking
inside Picture-in-Picture (PiP) Windows
Supports 2 Selectable I2C Addresses
Capable of processing Vertical Blanking Interval (VBI)
data from both fields of the video frame in data, the Z86229
Line 21 Decoder offers a feature-rich solution for any television or set-top application. The robust nature of the
Z86229 helps the device conform to the transmission format
defined in the Television Decoder Circuits Act of 1990, and
in accordance with the Electronics Industry Association
specification 608 (EIA–608).
The Line 21 data stream can consist of data from several data
channels multiplexed together. Field 1 consists of four data
channels: two Captions and two Texts. Field 2 consists of
five additional data channels: two Captions, two Texts, and
Extended Data Services (XDS). The XDS data structure is
defined in EIA–608. The Z86229 can recover and display
data transmitted on any of these nine data channels.
The Z86229 can recover and output to a host processor via
the I2C serial bus. The recovered XDS data packet is further
defined in the EIA–608 specification. The on-chip XDS filters in the Z86229 are fully programmable, enabling recovery of only those XDS data packets selected by the user. This
functionality allows the device to extract the required XDS
information with proper XDS filter setup for compatibility
in a variety of TVs, VCRs, and Set-Top boxes.
In addition, the Z86229 is ideally suited to monitor Line 21
video displayed in a PiP window for violence blocking,
CCD, and other XDS data services. A block diagram of the
Z86229 is illustrated in Figure 1.
Lock
SIG
PG
FEW
Digital
II Lock
Row
Status Reg
Test Reg
Command
Processor
Row
Latch
4
10
CG Lines
DOT CLK
V Lock
OSC
Display
RAM
MSGR
Display 8
Latch
CHAR
CIR
SS CTR
Control
FR
FLD
LS
SFLD
SLS
Vss(A)
LPF
Loop
Filter
4
ADDR
Decoder
Line &
Field
Control
11
9
5
Character
Generator
Output
Logic
Line & Fld
Decodes
HIN
13
FLD
PH1
I Drive
& MUX
ADDR
DEC
CHAR CLK
CW
O/S
Address
MUX
6
DOT CLK
DIV
CG
Logic
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Serial
Control Port
Slice Level
PH2
V/I
Ref
10
RREF
POR
CKT
17 3 2 18
Z86229 only
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SMS
SEN
SCK
SDA
SDO
Data Line
Data Bus
AW
COMP SYNC
CSYNC
Data CLK
Recovery
SYNC
Slicer
8
MSYNC
Figure 1. Z86229 Block Diagram
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Clamp
Sliced
Data
Data
Slicer
Buffer
1
BOX
BLUE
GREEN
RED
7
VW
Video
VIN /
Intro
12
6 4 15 14 16
Addr Bus
13
I2C SEL
VDD
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PIN DESCRIPTION
Table 1. Z86229 Pin Identification*
I2C SEL
GREEN
BLUE
SEN
HIN
SMS
VIDEO
CSYNC
LPF
1
2
3
4
5
6
7
8
9
18-Pin
DIP/SOIC
18
17
16
15
14
13
12
11
10
RED
BOX
SDO
SCK
SDA
VIN/INTRO
VDD
VSS (A)
RREF
Figure 2. Z86229 Pin Configuration
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Notes:
*Voltages referenced to VSS (A). Values beyond the maximum ratings listed above may cause damage to the device. Functional
operation should be restricted to the limits specified in the DC and AC Characteristics tables or Pin Description section.
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STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (Figure 3).
+5V
2.1 kΩ
From Output
Under Test
150 pF
250 µA
Figure 3. Standard Test Load
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Notes: TA = 0°C to +70°C; VDD = +4.75V to +5.25V.
Table 2. Composite Video Input
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ELECTRICAL CHARACTERISTICS
Nonstandard Video Signals must have the characteristics
indicated in Tables 3–6.
Table 3. Non-Standard Video Signal Characteristics
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It is at least 3H +/– 0.5H wide.
It starts at the proper 2H boundary for its field.
If equalizing pulse serrations are present, they must be less than 0.125H in width.
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Table 4. Horizontal Signal Input
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Table 5. Line Input Parameters
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Note: Line 21 must be in its proper position to the leading edge of the Vertical Sync signal.
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Table 6. Timing Signals
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PIN DEFINITIONS
Reset Operation. When the SMS and SEN pins are both in
Inputs
I2C SEL (Pin 1). This pin selects 28h for writing and 29h for
reading when this input is Low(0). When the input is
High(1), the device selects 2Ah for writing and 2Bh for
reading.
the Low (0) state, the part is in the Reset state; therefore, in
the I2C mode, the SEN pin can be used as an NReset input.
When SPI mode is used, if three wire operation is required,
both SMS and SEN can be tied together and used as the
NReset input. In either mode, NReset must be held Low (0)
for at least 100 ns.
SEN (Pin 4). This pin enables the signal for the SPI mode
of operation on the Serial Control Port. When this pin is Low
(0), the SPI port is disabled and the SDO pin is in the highimpedance state. Transitions on the SCK and SDA pins are
ignored. SPI mode operation is enabled when SMS is High
(1).
HIN (Pin 5). For this pin, the Horizontal Sync input signal
at the CMOS level must be supplied. When the device is
used in VIDEO-LOCK mode, the signal pulls the on-chip
VCO within the proper range. The circuit uses the frequency
of this signal, which must be within +3% Fh, but the overall
signal can be of either polarity. When used in the H-lock
mode, the VCO phase locks to the rising edge of this signal.
The HPOL bit of the H Position register can be set to operate
with either polarity of input signal. This signal is usually
the H Flyback signal. The timing difference between HIN
rising edge and the leading edge of composite sync (of VIDEO input) is one of the factors which affects the horizontal
position of the display. Any shift resulting from the timing
of this signal can be compensated for with the horizontal
timing value in the H Position Register. H-lock is intended
for use when the part is generating an OSD display when
no video signal is present.
Input/Output
VIN/INTRO (Pin 13). In external (EXT) vertical lock mode
of operation, the internal vertical sync circuits lock to the
V IN input signal applied at this pin. The part locks to the
rising or falling edge of the signal in accordance with the
setting of the V Polarity command. The default is rising
edge. The VIN pulse must be at least 2 lines wide.
In INTRO Mode, when configured for internal vertical synchronization, this pin is an output pin providing an interrupt
signal to the master control device in accordance with the
settings in the Interrupt Mask Register.
SDA (Pin 14). When the Serial Control Port has been set to
I2C mode operation, this pin serves as the bidirectional data
line for sending and receiving serial data. In SPI mode operation, the device operates as a serial data input. SPI mode
output data is available on the SDO pin.
Outputs
RED, GREEN, BLUE (Pins 2, 3, 18). These pins are osi-
tive-acting CMOS-level signals.
•
Color Mode: Red, Green, and Blue characters are incorporated as video outputs for use in a color receiver
•
Mono Mode: In this mode, all three outputs carry the
character luminance information
SMS (Pin 6). This pin allows the mode select pin for the Se-
rial Control Port. When this input is at a CMOS High state
(1), the Serial Control Port operates in the SPI mode. When
the input is Low (0), the Serial Control Port operates in the
I2C slave mode. In SPI mode, the SEN pin must be tied High.
(See Reset Operation section.)
VIDEO (Pin 7). This pin is a composite NTSC video input,
Note: The selection of Color/Mono Mode is user controlled in
bit D1 of the Configuration Register (Address=00h). (See
Internal Registers section.)
1.0V p-p (nom), band limited to 600 kHz. The circuit operates with signal variation between 0.7–1.4V p-p. The polarity is sync tips negative. This signal pin should be AC
coupled through a 0.1 µF capacitor, driven by a source impedance of 470 ohms or less.
CSync (Pin 8). Sync slice level. A 0.1 µF capacitor must be
SCK (Pin 15). This pin is an input for a serial clock signal
LPF (Pin 9). Loop Filter. A series RC low-pass filter must
from the master control device. In I2C mode operation, the
clock rate is expected to be within I2C limits. In SPI mode,
the maximum clock frequency is 10 MHz.
tied between this pin and analog ground VSS(A). This capacitor stores the sync slice level voltage.
be tied between this pin and analog ground V SS(A). There
must also be second capacitor from the pin to V SS(A).
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RREF (Pin 10). Reference setting resistor. Resistor must be
Power Supply
10 kOhms, ±2%.
SDO (Pin 16). This pin provides the serial data output when
SPI mode communications have been selected. This pin is
not used in I2C mode operation.
BOX (Pin 17). Black box keying output is an active High,
CMOS-level signal used to key in the black box for captions/text displays. This output is in a high-impedance state
when the background attribute has been set to semi-transparent.
VSS (Pins 11). These pins are the lowest potential power
pins for the analog and digital circuits. They are normally
tied to system ground.
VDD (Pin 12). The voltage on this pin is nominally 5.0
Volts, and may range between 4.75 to 5.25 Volts with respect to the V SS pins.
Note: The recommended printed circuit pattern for implement-
ing the power connection and critical components is referenced in the Recommended Application Information
section on page 49.
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Z86229 BLOCK DIAGRAM DESCRIPTION
The Z86229 is designed to process both fields of Line 21
on a television VBI and provide the functional performance
of a Line 21 Closed-Caption decoder and Extended Data
Service decoder. This device requires two input signals,
Composite Video and a horizontal timing signal (HIN), and
several passive components for proper operation. A vertical
input signal is also required if OSD display mode is required
when no video signal is present. The Decoder performs several functions, including extraction of data from Line 21,
separation of the normal Line 21 data from the XDS data,
on-screen display of the selected data channel, and outputting of the XDS data through the serial communications
channel.
Input Signals
The Composite Video input signal is rated at a nominal 1.0
Volt p-p, with sync tips negative and band-limited to
600 kHz. The Z86229 operates with an input level variation
of ±3 dB.
The HIN input signal is necessary to bring the VCO close
to the required operating frequency. This signal must be a
CMOS-level signal. The HIN signal can have positive or
negative polarity, and the signal is only required to be within
3% of the standard H frequency. When configured for EXT
HLK operation, this signal should correspond to the H Flyback signal.
The timing difference between the HIN rising edge and the
leading edge of composite sync (of VIDEO input) is one of
the factors that affects the horizontal position of the display.
Any shift resulting from the timing of this signal can be compensated for with the horizontal timing value in the H Position register.
The Sync Slicer processes the clamped Comp Video signal
to extract Comp Sync. This signal is used to lock the internally generated sync to the incoming video when the videolock mode of operation has been enabled. Sync slicing is
performed in two steps. In the non-locked mode, the sync
is sliced at a fixed offset level from the sync tip. When proper lock operation has been achieved, the slice level voltage
switches from a fixed reference level to an adaptive level.
The slice level is stored on the sync slice capacitor
(CSYNC).
The Data Clock Recovery circuit operates in conjunction
with the Digital H-lock circuit. The circuit produces a 32H
clock signal (DCLK) that is locked in phase to the clock runin burst portion of the sliced data obtained from the Data
Slicer. When the Line 21 code appears, the DCLK phase
lock is achieved during the clock run-in burst and is used
to reclock the sliced data. After phase lock is established it
is maintained until a change in the video signal occurs.
The Digital H-Lock circuit produces a variety of signals, including the video timing gates, PG and STG. These signals
are all locked in-phase with the HSYNC and the video timing signal, no matter which H-lock mode is used in the display generation circuits. This independent phase lock loop
is able to respond quickly to changes in video timing without
concern for display stability requirements.
VCO and One Shot
Video Input Signal Processing
All internal timing and synchronizing signals are derived
from the on-board 12-MHz VCO. The VCO output is the
DOT CLK signal used to drive both the Horizontal and Vertical counter chains and display timing. The One Shot circuit
produces a horizontal timing signal which is derived from
the incoming video, and qualified by a Copy Guard logic
circuit.
The Composite Video input is AC-coupled to the device.
The sync tip is internally clamped to a fixed reference voltage by means of a dual clamp. Initially, the unlocked signal
is clamped using a simple clamp. Improved impulse noise
performance is then achieved after the internal sync circuits
lock to the incoming signal. Noise rejection is obtained by
making the clamp operative only during the sync tip. The
clamped composite video signal is fed to both the Data Slicer and Sync Slicer blocks.
The VCO can be locked in phase to two different sources.
For television operation, where a good horizontal display
timing signal is available, the VCO is locked to the HIN input through the action of the Phase Detector (PH2). When
a proper HIN signal is not available (such as in a VCR), the
VCO can be locked to the incoming video through the Phase
Detector (PH1). In this case, the frequency detector (FR)
circuit is activated (as required) to bring the VCO within
the pull-in range of PH1.
The Data Slicer generates a clean CMOS-level data signal
by slicing the signal at its midpoint. The slice level is established on an adaptive basis during Line 21. The resulting
value is stored until the next occurrence of Line 21. A high
level of noise immunity is achieved by using this process.
Timing and Counting Circuits
The DOT CLK is first divided down to produce the character timing clock CHAR CLK. This signal is then further
divided to generate the horizontal timing signals H, 2H and
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HSQR. These timing signals are used in the data output (display) circuits.
The H signal is further divided in the LINE and FLD CNTR
to produce the various decodes used to establish vertical
lock, time displays, and control functions required for proper operation. The H signal is also used to generate the
Smooth Scroll timing signal for display.
The V Lock circuits produce a noise free vertical pulse derived from the horizontal timing signal. When the user selects Video as the vertical lock source, the internal synchronizing signals are phased up with the incoming video by
comparing the internally generated vertical pulse to an input
vertical pulse. These pulses are derived from the Comp Sync
signal provided by the Sync Slicer. In the vertical lock set
to V IN mode, the VIN signal is used in place of the signal
derived from Comp Sync. In either case, when proper phasing has been established, this circuit outputs the LOCK signal which is used to provide additional noise immunity to
the slicing circuits.
The LOCKed state is established only after several successive fields have occurred and the two vertical pulses remain
in sync. When LOCKed, the internal timing will flywheel
until the timing of the two vertical pulses lose coincidence
for a number of consecutive fields. Until LOCK is established, the decoder operates on a pulse-by-pulse basis.
Command Processor
The Command Processor circuit controls the manipulation
of the data for storage and display. This circuit processes
the Control Port input commands to determine the display
status required and the data channel selected. During the display time (lines 43–237), this information is used to control
the loading, addressing, clearing of the Display RAM, and
the operations of the Character ROM and Output Logic circuits.
During data recovery time (TV lines 21–42), the Command
Processor, in conjunction with the data recovery circuits, recovers the XDS data and the data for the selected data channel. Data is sent to the RAM for storage and display and/or
to the serial port, as appropriate. Where necessary, the Command Processor converts the input data to the appropriate
form.
Output Logic
The Output Logic circuits operate together to generate the
output color signals RED, GREEN and BLUE, and the Box
signal. When MONOchrome mode is selected, all three color outputs carry the luminance information. These outputs
are positive output logic signals.
The character ROM contains the dot pattern for all the characters. The output logic provides the hardware underline,
graphics characters, and the Italics slant-generator circuits.
The smooth scroll display is achieved by the smooth scroll
counter logic, which controls the addressing of the Character ROM.
Decoder Control Circuit
The Decoder Control Circuit block is the users communications port. The circuit converts the information provided
to the control port into the necessary internal control signals
required to establish the operating mode of the decoder. This
port can be operated in one of two serial modes. The SMS
pin is used to establish either of the two serial control modes.
In the two wire (I2C) control mode, the Z86229 responds
to its slave address for both the read and write conditions.
If the read bit is Low (indicating a WRITE sequence), then
the Z86229 responds with an acknowledge. The master
should then send an address byte followed by a data byte.
If the read bit is High (indicating a READ sequence), then
the Z86229 responds with an acknowledge followed by a
status byte and a data byte, respectively. Read data, however, is only available through indirect addressing; write addressing exhibits both indirect and direct modes. The busy
bit in the status byte indicates whether the write operation
has been completed or if read data is available.
The SPI mode is a three wire bus with the Z86229 acting
as the slave device. Communication is synchronized by the
SCK signal generated by the master. Typically, the serial
data output is transmitted on the falling edge of SCK and
the received data is captured on the rising edge of SCK. All
data is exchanged as 8-bit bytes.
Voltage/Current Reference
The Voltage/Current Reference circuit uses an externallyconnected resistor to establish the reference levels that are
used throughout the Z86229. For a minimal cost, an external
resistor can provide improved internal precision.
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Z86229 FUNCTIONAL DESCRIPTION
The Z86229 provides full function NTSC, Line 21 performance. Input commands are included to enable the decoder
to process and display any of the eight Caption/Text data
channels (CC1, CC2, CC3, CC4, T1, T2, T3 or T4) contained in Line 21 of either field of the incoming video. XDS
data can also be selected for the display. The DECODER
ON/OFF commands control whether or not the Line 21 data
in the selected channel is actually displayed. When switched
to the DECODER OFF (TV) state, incoming data in the selected channel is still processed, but not displayed.
The Z86229 can also be configured to operate with PAL or
SECAM video signals. The device decodes information encoded into its VBI in Line 22. The encoded data must conform to the waveform and command structure defined for
NTSC Line 21 operation.
VCO Lock
The Z86229 includes a VCO with stable gain characteristics
and good power supply rejection. The internal horizontal
and vertical synchronizing circuits provide a high degree of
noise immunity. There are options for both horizontal and
vertical lock. The VCO can be phase locked either to the
horizontal signal derived from the video input signal (VIDEO) or to the externally supplied HIN signal, typically horizontal flyback.
A HIN lock is used to provide a display having a minimum
amount of observable jitter. The low jitter requires a HIN
signal derived from a TV display that exhibits proper polarity. This type of signal is readily available in a television
receiver. Video-Lock mode enables the VCO to lock inphase to the incoming video signal, thus providing good operation in an application where no display-related HIN signal is available (such as in a VCR).
Video Timing
Timing signals are derived from the VCO for use in the line
counting and display circuits. Line counting requires proper
identification of the input signal's vertical pulse. Default operation uses the vertical sync signal derived from the video
input signal as the source for vertical lock. This method results in locking characteristics having good performance
and good noise immunity.
In the event that OSD operation is required under conditions
when no input video is present, it would be necessary to set
the Z86229 for VIN lock. In this mode, the vertical timing
is determined from the vertical pulse signal supplied to the
VIN pin.
The horizontal position of the caption display is determined
by the internal timing circuits. A default condition has been
established that should result in a well centered display in
a typical application; however, signal delays through videoprocessing circuits can vary between designs. The Z86229
provides the user with the ability to change the default timing. No matter which of the horizontal lock modes are selected, the display horizontal position on the screen can be
adjusted in quarter character (330 ns) steps by serial port
commands.
Displayable Character Set
Normal Mode. Characters are displayed as white or colored
dot matrix characters on an opaque background. The Box
is normally black, but the Z86229 can be set to a blue background Box with a serial command. The characters are described by a 12 by 18 dot pattern within a character cell
which is 16 dots wide by 26 dots high per frame. The location of the character luminance within the character cell varies from character to character to allow for the display of
lower case letters with descenders. All characters have at
least a 1-dot border of black around each character. Underline is also provided. Figure 4 illustrates the Z86229 standard character map and font.
The character ROM consists of a 12 by 18 dot matrix pattern
per character. Alternate rows and columns are read out in
each field to produce an interleaved and rounded character.
A display row contains a maximum of 32 characters plus a
leading and trailing black box, each a character cell in width,
making the overall width of a display row 34 x 8 = 272 dots.
Successive display rows are butted together so that the total
display occupies 195 dots high.
The black box is 34 character cells wide by 195 dots high,
resulting in a box size of 45.018 µ s in width by 195 scan
lines in height. The Box starts in scan line 43 and extends
to scan line 237. Theoretically, the display is horizontally
centered in the video display when the Box starts 13.2 µs
after the leading edge of H.
The default setting of the Z86229 places the center of the
Box at about 13.5 µs to allow for some delay in the normal
video path. However, the Box horizontal position can be adjusted by the user in 330 ns increments. The display is approximately within the safe title area for NTSC receivers.
Character width is 42.37 µs, also centered on the screen, resulting in a leading and trailing 1.32 µ s black border.
An optional Caption display mode, Drop Shadow, can be
selected by the user through the serial port. This display
mode eliminates the black box around the characters, placing a 2-dot black shadow to the right and below the character
luminance dots when the 15 scan line per row mode is active. This display mode is usable in Captions, Text, and
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OSD displays. Figure 5 illustrates the characters with a
drop-shadow added.
line below the descenders of any lowercase characters in the
last row.
Extended Features
This approach is desirable because shrinking the capitals to
make room for the accent mark within the character cell
makes poor quality characters. In some cases, there would
be no differentiation between the capital and lower case letter. Extended characters also have the advantage of minimizing the ROM size and providing a good readable font
that closely matches what is normally seen in print.
The EIA–608 specification has defined new extended features such as optional Background and Foreground display
attributes and optional Extended Characters. The Z86229
always responds to the Extended Characters, but the Extended Background/Foreground response can be controlled
by the user. The Background and Foreground attributes add
codes for background colors, black and transparent foreground, opaque, and semi-transparent backgrounds. The
BOX signal output pin is set to a tri-state condition whenever one of the semi-transparent attribute codes is active.
The external keying circuits can then use this condition to
implement the intended video display.
The font for the Extended Characters are illustrated in Figure 6. The accented capital letters have been implemented
by placing the accent marks above the character cell. When
selected, this mode results in the accent marks being written
into the character cell space of the row above. In some operating modes, the Z86229 expands the size of the overall
box height by adding two additional scan lines at the top
and one additional line at the bottom. There is now room
for the accent marks in the topmost row and an added black
In the unlikely case of a conflict between an accented capital
letter in one row and a lower case descender in the same
character position in the row above, the descender is given
priority. The improved readability of this approach over
shrunk capital letters far outweighs this potential conflict
and results in a cost-effective compromise for providing a
full, extended features implementation.
The Extended Characters share their address space with the
OSD Graphics Characters. When a BOX display is used,
the Extended Character set is in force; however, if a Drop
Shadow display is used, the Graphics Characters are in
force. For Caption and Text display modes, if the Drop
Shadow is set, the user must also command the Z86229 to
switch back to Extended Characters.
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Figure 4. Z86229 Standard Character Map and Font
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Figure 5. Caption Display Mode, Drop Shadow
-
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Figure 6. Extended Characters Font
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Text Mode Display
When the Text mode is selected, a black box is displayed
as long as a valid Line 21 code in the specified field is being
detected. The Z86229 provides the option to make the box
blue instead of black. This option holds for captions and
text.
The default Text display mode uses a 15 row by 34 character
black box. Text characters are displayed as they are received
starting at the top row. Successive carriage returns move the
display down successive rows until all 15 rows have been
displayed. Thereafter, the text scrolls up as new characters
are added to the bottom row.
If the data for the selected channel is interrupted by a command for another channel, data processing stops; however,
the display remains. When a Resume Text command is received, data processing resumes and the new characters are
added.
Note: The data processing begins at the position that the display
row/column pointer was in at the interruption of data processing.
If a Start Text command is received, the display is cleared,
and the new characters are displayed starting in row 1, column 1 (left side).
The number of display rows and the location (base row) of
the Text box can be altered by the user. In this way, the user
can decide how much of the screen can be covered when
displaying non-program related information.
When scrolling, the display shifts one scan line per frame
until a complete row has been scrolled. If a carriage return
is received before scrolling is complete, the display immediately completes the “scroll” by jumping up the remaining
scan lines and starting the display of the new text.
Caption Display Mode
According to FCC specifications, caption data can appear
in any of the 15 display rows, but a single caption may consist of no more than 4 rows. The form of the caption display
depends on the caption mode indicated by the transmitted
caption command, Pop-on, Paint-on, or Roll-up. The
Z86229 can display a single caption having as many as eight
rows. When any of the caption display modes are selected,
the screen becomes transparent
Note: Display box is only present when a caption is being dis-
played.
Pop-on captions work with two caption memories. One of
them is normally displayed while the other is being used to
accumulate new caption data. A new caption is popped-on
by swapping the two memories with the End Of Caption
(EOC) command. When the on-screen memory is erased,
the screen is blank (transparent), and the memory defaults
to the row/column pointer at row 1, column 1, and monochrome are non-underlined.
When caption mode is selected, the decoder processes data
following the Resume Caption Loading (RCL) command
(or the EOC). Normally, this command is followed by a Preamble Address Code (PAC) to indicate the row, column,
and character attributes to be used with the following data.
If no PAC is received, the data is added to the location most
recently indicated by the row/column pointer prior to the
receipt of the RCL command.
The Paint-on caption mode is essentially equivalent to the
Pop-on mode; however, the data received after the Resume
Direct Captioning (RDC) command is written to the onscreen memory rather than the off-screen memory. All the
rules for PACs, Midcodes, and so on, are otherwise the
same.
The Roll-up caption mode presents a “text” like display that
is limited to 2, 3, or 4 rows, depending on the Resume Rollup (RUn) command used. The PAC following the RUn
command is used as the BASE ROW for the ROLL-UP display. The BASE ROW is the “bottom” row of the ROLLUP display. In this case, the black box does not appear until
characters are being displayed, and the Box is only wide
enough to provide a leading and trailing box in each line.
The new data appears in the bottom row, and as each carriage return is received, the row scrolls up and the new data
is added to the bottom. When the number of rows indicated
by the Resume command have been reached, the data in the
top row scrolls off as new data is added to the bottom.
The TAB (INDENT) PAC permits placing captions starting
at 4 character boundaries in any caption row. The TAB
OFFSET command provides the means for adjusting the
starting position for a caption at any column position in the
current row.
XDS Display Modes
Two preprogrammed XDS display modes are provided.
One provides information about the current program that
would be of interest for “channel grazing”. The second display shows the grazing packets, plus additional XDS packets which informs the viewer about the program content. Information is displayed as it is received. The displays use a
drop-shadow mode with 15 scan lines per row.
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The XDSG mode is the GRAZE (channel grazing) display
(Figure 7). The display contains three rows of information
at the top of the screen that have been formatted for easy
reading. They contain the following XDS packet information:
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OSD Row 2
OSD Row 1
Network Name
Program Name
Program Length
When an XDS display mode has been selected, the information is displayed as the appropriate packets are received.
The display remains on-screen as long as valid XDS data
continues to be received. If the 16-Second Erase Timer is
enabled (the default condition), the XDS display is erased
when no valid XDS data has been received for 16 Seconds.
If subsequent XDS data is received with displayable packets, that information reappears on the screen. XDS data recovery can be active in the XDS display mode.
OSD Row 1
Call Letters
Network Name
Program Name
Program Length
Time in Show
OSD Row 3
OSD Row 2
Call Letters
Time in Show
OSD Row 3
Program Description information goes
here on OSD rows 10, 11
12 and,
13
Figure 7. XDSG (Graze) Mode Sample Display
The XDSF mode is the FULL (information) display (Figure
8). This display shows the same information as the GRAZE
display; however, this display adds the program type as well
the first four program description rows (if transmitted). Although XDS defines eight program description rows, the
first four are identified as containing the most important information. The display of Program Description is limited
to the first four rows. This limitation occurs because:
1. Eight rows would obscure much of the screen.
2. More than four rows are not likely to be sent due to the
time required for transmission.
Because 15 scan lines per row mode are being used, rows
10–13 appear at the bottom of the screen.
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Figure 8. XDSF Mode Sample Display
The XDS display mode is turned off by selecting a different
display mode.
Display Erase and Autoblanking
The display is erased in the Text mode by the Start Text
command (but the box is maintained) and in the CAPTION
mode by the Erase Displayed Memory (EDM) command.
The non-displayed memory can be erased by the Erase Nondisplayed Memory (ENM) command.
Four other events can also cause the display to be erased.
1. The first action is a change in the display mode, such
as from CC1 to T1 or CC1 to XDSF. A change in
display mode clears the memory and the display.
2. A loss of video lock, such as on a channel change, can
cause the screen to be cleared. The current active
display mode is not changed. For example, if CC1 is
selected and ON before the channel change, the device
will remain in the CC1/ON state after the channel
change.
3. The third action that clears the displayed memory is
when the autoblanking circuit is activated. The
autoblanking circuit monitors the presence of a Line
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21 waveform in the video field corresponding to the
data channel selected for display. The decoder is held
in the Decoder OFF (TV) state until a Line 21
waveform is continuously detected for a period of 0.5
seconds. After a valid Line 21 waveform has been
detected for 0.5 seconds, and assuming that the user
has selected the Decoder ON state, the normal display
for the data channel selected is presented. The
autoblanking circuit is not activated again until a valid
Line 21 waveform has been lost for 1.5 seconds. Any
data received during the 1.5-second period resets the
counter. As a result, autoblanking is only activated on
continuous loss of the Line 21 waveform for 1.5
seconds.
Note: A valid Line 21 waveform is defined as the presence of a
7-cycle run-in clock, in addition to a start bit on Line 21
of the field being examined.
4. The fourth method of clearing the screen is by the
action of the 16-Second Erase Timer. This function is
only active when a CAPTION or XDS display mode
has been selected. If no data is received for the display
channel selected for a 16-Second period, the on-screen
memory is erased; however, the decoder is still on the
selected channel (with the decoder ON), allowing data
for the selected channel to be displayed.
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Z86229 FEATURE SET
The primary features of the Z86229 are summarized below.
More complete descriptions can be found in later sections
of this document.
supplied through its serial port. This condition is referred
to as On-Screen Display (OSD) mode. This mode provides:
•
Programmable Full Screen OSD: 15 display rows by
32 character columns
•
•
•
Graphics characters
•
Accepts externally supplied (or internally generated
VSYNC to enable OSD even when no video is present)
VBI Data Processing
The Z86229 extracts Line 21 data from the incoming video
signal. All data channels in both video fields are supported.
Incorporating the VBI decoding feature, the Z86229 can
perform the following:
•
•
Process data from both fields of Line 21 simultaneously
•
•
Output XDS data through the serial port raw or filtered
•
Output XDS data through the serial port while displaying selected data
Select XDS filters from a list of pre-programmed values including Program Rating and Time of Day/Local
Time
Select NTSC or PAL operation
The video data extracted from Line 21 may be displayed in
different ways according to the user selection and the type
of data. Display choices include:
•
Ten different Line 21 data-display modes; CC1–CC4
and T1–T4, plus two standard templates for XDS displays
•
•
•
Pop-on, Paint-on, and Roll-up CAPTION displays
•
•
Color or Monochrome display mode selectable
•
Fully programmable display positioning (information
may be placed anywhere on the screen)
Character Set
The Z86229 has a new character set with extended features,
such as:
•
•
New font with descenders on lower case letters
•
•
•
EIA–608 Extended Characters
•
Double-High and Double-Wide character display for
OSD
•
Fifteen scan lines per character row for OSD and Text
Text display default as a full screen, 15 row display
User can vertically reduce and reposition the Text display as required
Double-High and Double-Wide characters
Optional display mode using the drop-shadow font (in
other words, fringing appears on each character rather
than a solid, “black box” background)
EIA–608 Background and Foreground attributes
Special framing and graphics characters for OSD display
Note: Contact the nearest ZiLOG Sales office for additional in-
formation on how to define your own custom OSD character set.
XDSG Display Mode (channel grazing): automatic
display of Network Name, Call Letters, Program
Name, Program Length, and Time In Show data packets
Serial Communications Interface
XDSF Display Mode (full information): automatic
display of XDSG Display Mode information in addition to Program Type (only basic types) and Program
Description
Communications and control of the Z86229 is possible
through a serial control interface. Two Serial Control
Modes are available with the Z86229 performing as a slave
device. These modes are:
1. A two wire, I2C interface.
General Purpose OSD Modes
Apart from displaying data extracted from Line 21 of the
incoming video, the Z86229 can also display information
2. A three wire, Serial Peripheral Interface (SPI).
A total of five device pins are dedicated to the serial control
port function. These pins are indicated in Table 7.
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Table 7. Z86229 Serial Control Signals
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1. An INPUT pin for acceptance of an external VSYNC
timing signal.
2. An OUTPUT pin for interrupt generation on selected
events.
Note: Configuring VIN/INTRO as an output for interrupt gener-
ation is particularly useful when implementing the Program Blocking feature with the Z86229 in TVs and
VCRs. In this configuration, Pin 13 is used to interrupt the
host processor when the XDS Program Rating data packet
is found. As a result, the host processor is not burdened
with monitoring or filtering the line 21 data stream. The
Z86229 filters the Line 21 data stream for the host processor, and generates an interrupt only when the required
packet is found.
Notes:
SMS = Serial Mode Select High = SPI and Low = I2C.
SCK = Serial port clock for either Serial Mode.
SDA = Serial port data for I2C Mode and Data In for SPI Mode.
SDO = Serial Data Out for SPI Mode. Not used in I2C Mode.
SEN = SPI Mode Enable signal. Must be High for I2C Mode.
I2C Mode. The I2C port on the Z86229 always acts as a slave
device. I2C Mode is selected by bringing the SMS pin Low
and the SEN pin High. SEN must remain High whenever
I2C mode is required. If the SEN pin is brought Low, with
the SMS also Low, the part is reset. SDA and SCK are the
data and clock lines of the I2C port, respectively. During I2C
mode operation, the V IN/INTRO signal (pin 13), can be configured to generate interrupt requests to the master device
on selected events (see Note paragraph page 22).
SPI Mode. SPI Mode is selected by making the SMS pin
High. In SPI mode, the Z86229 acts as a slave device. All
communications are clocked in and out as 8-bit bytes. SCK
is the serial clock (input), SDA is Data-In, and SDO is DataOut. The SEN pin enables communication when High.
When Low, the SDO pin is tri-stated.
When SEN is brought High, the part is synchronized and
waiting for a Command. If SEN is tied High, the part can
also be synchronized by a command string. During SPI
mode operation, the VIN/INTRO signal (pin 13) can be configured to generate interrupt requests to the master device
on selected events
Caution: When the SEN and SMS pins are made Low simulta-
neously, the part is reset.
Interrupt Generation. The VIN/INTRO signal (pin 13) can
be configured to provide an interrupt output on selected
events. The configuration of V IN/INTRO (pin 13) is user
programmable to be either:
Setup and Operational Control
The Z86229 is extremely flexible and fully programmable
through its serial communication port. The following tables
provide a partial list of User-Programmable Features, User
Selectable Display Modes, and Default Conditions upon
Reset.
Z86229 Programmable Features
•
•
•
•
•
•
•
•
•
•
•
•
Decoder ON/OFF
TV scan lines per OSD row (13 or 15 lines)
EIA–608 extended attributes ON/OFF
OSD drop shadow ON/OFF
Color/Monochrome
OSD Horizontal start position
Text box size (# of rows)
Text box starting row position
NTSC or PAL
Vertical Lock Source: Video or External VIN
XDS Data Output, Raw or Filtered
H-lock Source: Video or External HIN
In addition to the programmable features just listed, the
Z86229 offers a choice of eleven display modes for user selection.
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Table 8. Z86229 Display Modes
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The Z86229 is initialized on RESET to the following default
conditions:
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Notes:
1. In NTSC-interlaced mode, there are two fields, or horizontal pixel-display lines, exhibiting alternate refreshes to the
display.
2. Language I refers to synchronous captioning, and language II refers to supplementary captioning.
Table 9. RESET Default Conditions
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SERIAL COMMUNICATIONS INTERFACE
Commands and data are sent to and from the Z86229
through its serial communications interface. Two Serial
Control Modes are available. One mode is a two wire I2C
bus interface. The other serial mode is a three wire, synchronous serial peripheral interface (SPI). In both cases, the
Z86229 acts as a slave device.
The serial communications port is the path for setting the
configuration and operational modes of the device. It is also
the port for outputting the recovered XDS data and for inputting the OSD data for display.
When the Vertical Lock = VIDEO, the VIN/INTRO (pin13)
is configured as an output, providing the INTRO signal.
This interrupt operation is available in either serial control
mode.
The Z86229 is able to generate an interrupt on the occurrence
of any set of specified events. The master device clears the
interrupt by writing to the Interrupt Request Register.
I2C Bus Operation
The I2C Bus Protocol
Under the I2C bus protocol, the following conditions must
be present:
1. Data transfer can only be started when the bus is not busy.
2. During data transfer, data transitions must not occur
while the clock is High.
Bus Conditions are Defined as:
Not Busy. Data and Clock lines are both High.
Start. A High to Low transition of an SDA line while the
SCK line is High.
Stop. A Low to High transition of an SDA line while the
SCK line is High.
Acknowledge. When addressed, the receiving device must
output an acknowledge after the reception of each byte. The
master device must generate the clock for the acknowledge
bit. Acknowledge is SDA=Low. A Not ACKnowledge result (NACK) is SDA=High.
The serial control mode in use is selected by the state of the
SMS pin. When SMS is set Low, the Z86229 is in the I2C
mode. In this mode, the Z86229 also supports a bidirectional
two wire bus and data transmission protocol. The bus is controlled by the master device, which generates the serial
clock (SCK), controls the bus access, and generates the Start
and Stop conditions. The SDA pin is the bidirectional data
line. In this mode, the SDO output is not used, and the pin
is in its high-impedance state.
on the falling edge of SCK, MSB first. The receiving device
reads the data, MSB first, on the rising edge of SCK.
The Z86229 can receive or transmit data under the control
of a master device. Remember that the Z86229 is a slave
device. Communication is initiated when the master device
sends the start condition followed by the Z86229 Slave Address Read byte (29h or 2Bh) or Slave Address Write byte
(28h or 2Ah). The Z86229 responds with an Acknowledge.
The I2C RD/nWR bit is the Least Significant Bit (LSB) of
the I2C addresses (Table 10).
Writing to the I2C Bus
Table 10. Z8612 I2C Slave Addresses*
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Note: *When the SMS and SEN pins are both Low, the part is in
the Reset state. Therefore, the SEN pin can be used to reset the
part while in the I2C mode. The SEN pin may be tied to a NReset
signal or tied High if no reset is required. The I2C Address is
selected by pin 1 input. When pin 1 input is Low(0), it selects the
1st address. When pin 1 input is High(1), it selects the second
address.
Data. The data (SDA) is output by the transmitting device
Communication with the Z86229 is initiated when the master device sends the Z86229 slave address following a start
condition. The Z86229 has a single preset, consisting of a
seven-bit slave address. The Z86229 responds with an acknowledge. The eighth bit of the slave address is driven
High for Read operations and Low for Write operations.
All write commands are either one- or two-byte commands.
The Z86229 is enabled when a Start condition, followed by
its Slave Address Write byte, is received. The Start condition is disabled when it deems the command to have been
completed, or when a Stop condition occurs. A new Start
condition without a Stop condition begins a new sequence.
Therefore, successive commands may be executed by successive strings of “Start—Slave Address—Command” sequences without any intervening Stop condition being sent.
Note: The number of data bytes to be received by the Z86229 is
inherent in the command. The Z86229 responds with the
acknowledge signal only for the number of bytes expected. If the master writes more bytes than expected, there is
no acknowledge for the extra bytes.
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A write command to the Z86229 should always be preceded
by executing a Status read to verify that the Z86229 is not
busy. The Status register data is output immediately following the reception of the Slave Address Read. If the RDY
bit is set, the master device can initiate its write sequence,
always beginning with the Start condition. The first byte of
a two-byte command is always written first.
An example of the master’s sequence for writing a two-byte
command (after RDY had been checked) would be:
Start
Slave Address Write/Slave ACK
CMD (master)/ Slave ACK
DATA (master)/Slave ACK
Stop
SLAVE
ADDR
WRITE
CMD
WRITE
DATA
STOP
(WRITE=28h)
I2C One-Byte Write (Command)
SLAVE
ADDR
STRT
WRITE
CMD
STOP
The number of data bytes available is indicated by the state
of the RD2 bit of the serial status. In a typical read operation,
the status byte is read, and the DAV and RD2 bits are examined. If one or two data bytes are available, the data is
read in sequence, separated by acknowledges.
fined in Figure 10) the most recent byte read from the
Z86229 should be acknowledged by the master with a
NACK (Not ACKnowledge). It is also necessary to read
all available data in a read operation to clear the DAV bit
and permit subsequent reads. The DAV is cleared by the
master clocking out of the eighth bit of the most recent
data-byte read. The DAV is never cleared by just reading
the SSB (one-byte read) alone. All data is first output as
MSB.
The slave’s sequence for reading two data bytes (total of
three bytes including SSB) from the Z86229 is given as:
(WRITE=28h)
Note: A Status Register RDY bit must be read and checked prior to
the STRT condition of either WRITE sequence above. See the OneByte Read (Status Only) in Figure 10 for more information on reading
the Status Register.
Figure 9. I2C Bus WRITE (Command)
Reading Data Using the I2C Bus
Start
Slave Address Read/Slave ACK
SS Byte/Master ACK
Byte (slave)/Master ACK
Byte (slave)/Master NACK
Stop
I2C One-Byte Read (Status Only)
With the exception of the Serial Status (SS) register, which
may be read at any time, each read operation must be set
up before the data can be read from the serial output registers
of the Z86229. Data is set up for a read operation either automatically or manually. The XDS data reads are set up automatically upon recovery by setting a valid XDS FILTER
register selection. All other data read operations must be set
up manually using the READ SELECT commands RDS1
and RDS2. These commands load the selected data byte or
pair of bytes into the serial output register(s), setting the SS
register RD2 bit according to the number of data bytes requested. The SS register DAV bit is also set at that time to
indicate the availability of data.
The Z86229 I2C Bus supports one-, two-, and three-byte
read sequences. All read sequences output the SS register
as the first output byte. If the serial status DAV bit is set, a
two or three byte read sequence can then be initiated, beginning with a new STRT condition.
not attempt to read any data bytes. Attempting to read
data bytes from the I2C master device may cause a loss
of data from the Z86229 output registers.
Note: In all I2C Read operations (one, two, and three byte as de-
I2CTwo-Byte Write (Command & Data)
STRT
Caution: If the DAV bit is not set, the I2C master device should
STRT
SLAVE
ADDR
(READ=29h)
SERIAL
STATUS
(SSB)
STOP
NACK
I2C Two-Byte Read (Status & Data1)
STRT
SLAVE
ADDR
(READ=29h)
READ
DATA1
SERIAL
STATUS
(SSB)
STOP
NACK
I2C Three-Byte Read (Status, Data1, & Data2)
SLAVE
ADDR
STRT
(READ=29h)
SERIAL
STATUS
READ
DATA1
READ
DATA2
STOP
(SSB)
NACK
2
Note: In all I C Read operations defined herein, the last byte read
from the Z86229 must be acknowledged by the master with a
NACK (Not ACKnowledge).
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Figure 10. I2C Bus READ (Command)
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Clock and Data Transitions. The SCK and SDA bus lines
are normally pulled High with a resistor. Data on the SDA
bus may only change during SCK Low time periods. Data
changes during SCK High periods indicate a start or stop
condition (Table 11) defined as:
Start Condition. A High-to-Low transition of SDA, with a SCK
tF
SCK
tSU.STA
tHD.DAT
High as a start condition which must precede any other command.
Stop Condition. A Low-to-High transition of SDA, with a SCK
High as a stop condition which terminates all communications.
tSU.DAT
tSU.STO
tHD.STA
SDA (IN)
tBUF
Acknowledge. All address and data words are serially transmitted
to and from the Z86229 in eight-bit words. The instance of a ninth
bit generates an acknowledge. The device acknowledges the data
by pulling the SDA bus Low during the ninth bit. A Not ACKnowledge (NACK) is given by SDA=High during the ninth
clock time.
tR
tHigh tLow
tAA
tDH
SDA (OUT)
Figure 11. I2C Serial Timing
Table 11. I2C Serial Timing Min/Max
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SPI Bus Operation
When the SMS pin is High, the Z86229 is in the SPI serial
control mode. The clock line should be tied to the SCK pin.
The DATA IN signal and DATA OUT signal from the master device should be connected to the SDA and SDO pins,
respectively. The SEN pin is used to select the Z86229 when
there are multiple peripherals on the bus.
As noted above, when both the SMS and SEN pins are Low,
the part is in the RESET state. When the SPI bus is used in
a dedicated fashion between the master and the Z86229,
both the SEN and SMS pins would be tied High. The RESET
-
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9
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-9
-9
-9
@
@
9
9
@
@
@
@
@
@
@
3
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µ
µ
µ
µ
µ
µ
µ
µ
µ
function would require that both of these pins be tied to the
NReset signal. To ensure synchronization, the master device should send the serial synchronization signal after the
reset is released.
When the SPI mode is used in a multiple peripheral environment, the SEN pin is used as the Z86229 enable signal.
The SMS could then be used for the NReset signal as long
as the reset was only applied while SEN is Low. In this case,
there would be no requirement for the master device to send
a serial synchronization string after reset if there was at least
100 ns between the end of the reset and the start of the port
enable.
!"
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ZiLOG
A command string can be interrupted at any time. The port
is resynchronized by sending the Serial Sync signal or by
activating the rising edge of SEN.
The SPI bus is a three-wire bus when used in a dedicated
manner between the Z86229 and the master device. If other
peripherals are connected to the bus, then the SEN pin must
be used to place this device on the bus at the appropriate
time. When SEN is Low, the SDO pin becomes tri-stated,
transitioning on the SCK and SDA pins, which, as a result,
are ignored.
If data output is not required from the Z86229, then control
can be accomplished using only the SCK and SDA pins. Because this type of operation precludes the ability to check
the RDY bit, it is very important that commands be spaced
by at least two frames (66 msec) to ensure that one command
has been executed before initiating another.
The bus is controlled by the master device, which generates
the serial clock (SCK) and initiates all actions. Clocking
data in on the SDA simultaneously produces a data out on
the SDO. The master should always check for the appropriate handshake signal before executing any command other than a NOP.
Writing to the part requires that the RDY bit be set, while
reading from the part requires checking the SS register to
see if the DAV bit is set. Both of these bits are contained
in the Serial Status (SS) register. Writing to the Z86229 concurrently outputs the contents of the SS register, MSB first,
unless other data is being output as a result of one of the
READ commands. If it is required to read the SS without
executing a command, the NOP command can be written
at any time, even if the serial status RDY bit is not set.
The RDY status bit is driven onto the SDO pin between
command transmissions. The controlling MCU can test the
state of this pin, without clocking, in order to determine if
subsequent serial transfers are possible. The DAV bit can
only be checked by outputting the contents of the SS register.
Writing to the SPI Bus
All write commands are either one or two-byte commands.
The number of data bytes to be received by the Z86229 is
inherent in the command. If the master device writes more
bytes than expected, the command may be overwritten or
corrupted by the extraneous bytes.
A write to the Z86229 should always be preceded by executing a Status read to verify that the device is ready. The
serial status is output by the device, concurrent with the input of any command byte. If the RDY bit of the serial status
register is set, the master device can write a new command.
The command and data bytes are written MSB first. Typically, the first byte of a two-byte command is sent first. The
bits are clocked into the Z86229 by placing the data on the
SDA input and bringing the SCK High.
Reading Data Using the SPI Bus
With the exception of the SS read, each read operation must
be set up before the data can actually be read from the serial
output registers of the device. Data is set up for a read operation either automatically or manually. The XDS data is
set up for a READ automatically upon recovery by setting
a valid XDS FILTER register selection. All other data read
operations must be set up manually, using the READ SELECT commands RDS1 and RDS2. These commands load
the selected data byte( or pair of bytes) into the serial output
registers, set the SS register RD2 bit according to the number of data bytes requested, and set the serial status DAV
bit to indicate the availability of data.
The Z86229 SPI Bus supports two and three byte read sequences. In SPI mode, the SS must be read before a read
sequence is started, so that the DAV and RD2 bits can be
checked. The number of data bytes available is indicated by
the state of the RD2 bit. The special command, READ1 or
READ2, is then used to read the one or two available data
bytes. The serial status is clocked out during the write of
the READ1 or READ2 command. The data byte or bytes
are then clocked-out in sequence, MSB first, while the NOP
commands are written into the device. Data bits are clockedout on the rising edge of SCK. All available data bytes must
be read to clear the DAV bit and permit subsequent reads.
The SPI Bus Protocol
The SPI Bus Protocol is defined as follows:
1. The first bit of the first output byte is driven out on the
SDO. This action is followed by the rising edge of
SCK on the last bit (LSB) of the READ1 or READ2
command.
2. A three-wire bus is defined with a Clock signal on the
SCK pin, a Serial Data Input on the SDA pin, and a
Serial Data Output on the SDO pin.
3. The SEN pin Low disables the port, placing the SDO
pin in a tri-state. Signal transitions on SCK and SDA
are ignored.
4. The SEN pin High enables the port for operation.
5. The SEN and SMS pins Low indicate a hardware reset
for the part. These pins must be held Low for at least
100 ns.
6. Serial synchronization can be established by clocking
in the minimum required SSR string of FFh, FFh, FEh.
More than two bytes of FFh may be input, but the
string must end with FEh.
!"
()*++,
-.+/
ZiLOG
COMMANDS
Serial Port Commands
Caption/Text Display Mode Commands
The majority of the Z86229 commands are common to both
the I2C and SPI modes. In the I2C mode, the commands must
be contained within the specified sequence (Start—Slave
Address—etc.).
CPTX = 10h–1Fh. These caption and text display-mode
commands are one-byte commands that select the Line 21
data stream (caption or text) for display.
CM6
CM5
CM4
CM3
CM2
CM1
0
0
0
1
FLD
CPTX
LANG DONOF
R/W
R/W
R/W
R/W
R/W
R/W
Bit CM7
Note: In the following Command descriptions, the letter “h” fol-
lowing a command code designates hexadecimal notation.
R/W
CM0
R/W
Figure 12. CPTX–Caption/Text Display
(CPTX = 10h–1Fh)
Reset
RESET = FBh, FCh, 00h. RESET is a three byte command
sequence in SPI or I2C mode. The RESET command establishes all the specified default settings in the device, but it
does not reset the serial port itself. This sequence can be entered without RDY being set.
A data channel can be selected for display with the display
either enabled (DEC ON) or disabled (DEC OFF). All these
commands turn off the active XDS display mode. Table 13
summarizes the device’s caption and text display modes and
the proper command code to activate them.
No Operation
Table 13. Caption and Display Commands
NOP = 00h. NOP is a one-byte command for use in SPI or
I2C mode. The NOP command does not affect the status of
the RDY bit in the Serial Status (SS) register and can be executed independent of the RDY status.
Serial Sync Bytes
SSB = FFh,....,FFh,FEh. Serial Sync Bytes are used in SPI
mode only. This command actually consists of a string of
single-byte commands in the form FFh,....FFh,FEh. SPI
mode communications can be synchronized by sending a
synchronizing data string to the part. This string should consist of at least two SSB bytes of FFh, followed by one SSB
byte of FEh. At the end of the FEh byte, the port is ready
for use.
Table 12. Basic Serial Commands
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XDS Display Mode and 16-Second Erase Timer
Commands
XDS DISP = 20h–27h. XDS Display commands are one-
byte commands. These commands control the selection of
XDS display modes and the state of the 16-Second Erase
Timer. The 16-Second Erase Timer is active only for caption and XDS display modes. The 16-Second Erase Timer
has no affect on Text mode displays.
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ZiLOG
Table 14. XDS Display Commands*
7
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Note: For XDS data recovery, when the XDS Filter Register
Note: *Changing the ON/OFF state of the 16-Second Erase
Timer has no affect on the current display mode in operation.
READ1 = F8h. This command reads one byte in the SPI mode.
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(see Internal Register section) is enabled for the packets,
the Z86229 automatically establishes the two-byte recovery mode, moving the recovered data bytes to the output
register.
Reading Data From The Z86229
READ2 = F9h. This command reads two bytes in the SPI mode.
Read And Write Commands
Read Selects. There are two Read Select commands
Bit 7
6
5
4
3
2
1
0
1
1
1
1
1
0
0
RD2
W
W
W
W
W
W
W
(RDS1 and RDS2) in the Z86229. Each command is one
byte in size and indicates that a read should take place.
RDS1 specifies that one byte is read from the Z86229; likewise, RDS2 indicates that two bytes are read.
W
Figure 15. READx–Read x Bytes
(READ1/2 = F8h/F9h)
RDS1 = 40h–47h. RDS1 is a one-byte command used to
initiate a one-byte read sequence. This action is performed
by moving the contents of the register identified by the address field (AD00:02) of the command to the output register.
Addresses 0h–7h are valid in the RDS1 command field
AD00:02.
CM6
CM5
CM4
0
1
0
0
W
W
W
W
Bit CM7
CM3 CM2
CM1
CM0
AD03 AD02 AD01 AD00
W
W
W
W
Figure 13. RDS1–Read One Byte
(RDS1 = 40h–47h)
RDS2 = 60h–66h. RDS2 is a one-byte command which is
used to initiate a two-byte read sequence. This action is performed by moving the contents of the two consecutive registers, starting with the one identified by the address portion
of the command (AD00:AD02), to the output registers, setting the RD2 bit in the SS register. Only Addresses 0h–6h
are valid in the RDS2 command field AD00:02.
The READx commands do not affect the status of the RDY
bit in the Serial Status (SS) register, and can be executed
independent of the RDY status.
In both serial communications modes, the DAV bit in the
SS register indicates when the data is available. When the
RD2 bit is Low, the DAV is cleared on the rising edge of
SCK at the LSB of the first data byte. When the RD2 bit is
High, the DAV is cleared on the rising edge of SCK at the
LSB of the second data byte. The RD2 bit is only valid if
the DAV is High.
Reading in the I2C mode is selected by the R/NW bit in the
Slave Address byte. The first byte after the Slave Address
byte is SS followed by the data in output buffers (A and B,
respectively). If the instruction being executed is a one-byte
read, then buffer A contains the read data and buffer B contains all ones.
Writing to the Z86229
WRxx = C0h–DFh
Bit
Bit
7
6
5
4
3
0
1
1
0
0
W
W
W
W
W
2
1
0
AD02 AD01 AD00
W
W
7
6
5
4
3
1
1
0
0
0
W
W
W
W
W
W
Figure 14. RSD2–Read Two Bytes
(RDS2 = 60h–66h)
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AD02 AD01 AD00
W
W
W
Figure 16. WRxx–Write Register xx
(WRx = C0h–DFh)
()*++,
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ZiLOG
The WRITE commands require two bytes to execute. The
first byte is the write command. This byte includes the
Z86229 register address (AD00:04). The second byte is the
data to be written.
OSD Display Mode Commands
presentation to the screen. Normally, the OSD display mode
uses 15 TV lines per display row to enhance the screen appearance. The following tables summarize the single- and
two-byte control commands for the Z86229 On-Screen Display.
OSD commands are one and two-byte commands. They are
used to control the loading of data for OSD display and their
Table 15. Single-Byte OSD Display Mode Commands
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Table 16. Two-Byte OSD Display Mode Commands
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Figure 17 illustrates the two different character sets, Graphics or Extended, that share the address space C0h–FFh. The
Graphics Character set is in force when the OSD display is
in Drop-Shadow mode (the default condition).
!"
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ZiLOG
The two-byte commands (GRAPHICS and EXTENDED)
above can be used to switch from the Graphics Characters
to the Extended Characters and vice versa.
Note: An OSD screen can only use one set at a time.
Figure 17. Z86229 Graphics or Extended Character Set
!"
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-.+/
ZiLOG
INTERNAL REGISTERS
Information controlling the setup and operation of the
Z86229 are maintained in several registers. The user may
read or alter the contents of these registers as required.
Serial Status (SS) Register Address = Not Required
D6
D5
DAV
RD2
Bit D 7
RDY
R
R
R
D4
D3
D2
D1
D0
WOVR INTR ROVR FLD
R
R
LOCK
R
R
R
Figure 18. Serial Status Register
(Address not required)
When PAL is selected, the display defaults to 15 TV scan
lines per display row.
D 1–MONO. This bit selects monochrome operation. Active
High indicates that the character luminance is output on all
three color pins (RGB). The default is Low, selecting COLOR operation.
D 2–HLK. This bit selects the horizontal signal source to be
used to lock the VCO (Low = Internal, High = HIN). The
default is Internal.
D 3–VLK. This bit selects the vertical signal source to be used
D0–LOCK. Active High, indicating that the internal sync
circuits are locked. This bit may be used as an indication
of the presence of a video signal.
D1–FLD. This bit signals the current video field. Low =
Field 2, High = Field 1.
D2–ROVR. Active High, indicating that the data available
in the output buffer has not been read out and, new data has
been written over it.
to establish a vertical sync lock (Low = Internal, High =
V IN). The default is Internal. When the Internal lock is enabled, the VIN/INTRO pin defaults to the INTRO output
mode. Interrupts should not be selected in the Interrupt
Mask register if the VLK mode is used.
D 4–D7. Reserved.
Display Register Address = 01h
Bit D7
O15
D3–INTR. Active High, indicating that an interrupt other
than DAV is pending.
R/W
D5
D4
ODRP CENH
C15
R/W
D6
R/W
R/W
D3
D2
D1
D0
CDRP TENH
T15
TDRP
R/W
R/W
R/W
R/W
Figure 20. Display Register (Address = 01h)
D4–WOVR. Active High, indicating a serial input data over-
run has occurred.
D5–RD2. Signals the number of bytes available for output.
D 0–TDRP. This bit selects Drop Shadow or Full Box in Text
Low = 1 byte, High = 2 bytes.
mode (High = DROP SHADOW and Low = BOX). The default is Low.
D6–DAV. Active High, indicating that data is available to
D 1–T15. This bit selects the number of TV lines per char-
be read out.
D7–RDY. Active High, indicating that the port input buffer
is empty. Only the NOP, RESET, and READ instructions
may be sent if RDY is Low.
Configuration Register Address = 00h
Bit
D7
D6
D5
D4
D3
D2
D1
D0
res
res
res
res
VLK
HLK
MONO
TVS
R/W
R/W
R/W
R/W
acter row in a Text display (High = 15 lines/row and Low
= 13 lines/row). The default is Low.
D 2–TENH. This bit enables Enhanced Attributes for a Text
display (High = Disabled, Low = Enabled). The default is
Low.
D 3–CDRP. This bit selects Drop Shadow or Full Box in
CAPTION mode (High = DROP SHADOW and Low =
BOX). The default is Low.
D 4–C15. This bit selects the number of TV lines per char-
Figure 19. Configuration Register (Address = 00h)
acter row in a CAPTION display (High = 15 lines/row and
Low = 13 lines/row). The default is Low.
D0–TVS. This bit selects the television standard. High se-
D 5–CENH. This bit enables Enhanced Attributes for a CAP-
lects PAL and Low selects NTSC. The default is NTSC.
TION display (High = Disabled, Low = Enabled). The default is Low.
!"
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ZiLOG
Note: OSD and XDS display modes always have Enhanced At-
tributes enabled.
D6–ODRP. This bit selects the Drop Shadow or Full Box
mode in the OSD and XDS displays (High = DROP SHADOW and Low = BOX). The default is High.
D7–O15. This bit selects the number of TV lines per character row in the OSD and XDS display modes (High = 15
lines/row and Low = 13 lines/row). The default is High.
H Position Register Address = 02h
Bit
D7
D6
BLUBX HPO
R/W
R/W
with a base row of 12, this register should be set to C8h. If
the value of the x and y bits result in a display where Text
rows are off the top of the screen, then the first row of the
Text display starts in row 1, having the number of rows determined by the x value.
Line 21 Activity Register Address = 04h
Bit D7
D6
D5
D4
D3
D2
D1
D0
res
res
res
res
res
res
XDS
SCH
R
R
Figure 23. Line 21 Activity Register (Address = 04h)
D5
D4
D3
D2
D1
D0
h5
h4
h3
h2
h1
h0
R/W
R/W
R/W
R/W
R/W
R/W
Figure 21. H Position Register (Address = 02h)
D0–D5–h0–h5. This bit is used to set the Horizontal Timing
of the display. The default value in this register is 26h. Each
count change represents an incremental timing change of
330 ns. Decreasing the value of this field moves the display
to the RIGHT. Conversely, increasing the value of this field
moves the display to the LEFT.
D6–HPO. This bit sets the polarity to be used for locking to
D 0–SCH. This bit indicates data being processed in the Data
Channel selected for display. The display becomes inactive
if no data is received for the selected channel within the previous 16 seconds (High = Active, Low = Inactive). The reset
state is Low.
D 1–XDS. This bit indicates that XDS data is being pro-
cessed. The display becomes inactive if no XDS data is received within the previous 16 seconds (High = Active, Low
= Inactive). The reset state is Low.
D 2–D7. Reserved.
XDS Filter Register Address = 05h
the HIN signal when in the EXT HLK mode (Low = Rising
Edge, High = Falling Edge). The default is Low.
Bit D7
D6
D5
D4
s2
s1
s0
PUBL
MISC CHAN
D7–BLUBX. This bit designates the color of BOX (High =
R/W
R/W
R/W
R/W
R/W
Blue Box and Low = Black Box). The default is Low.
D3
D2
R/W
D1
D0
FUTR CURR
R/W
R/W
Figure 24. XDS Filter Register (Address = 05h)
Text Position Register Address = 03h
Bit D7
D6
D5
D4
D3
D2
D1
D0
y3
y2
y1
y0
x3
x2
x1
x0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
D 0–CURR. This bit selects the Current Class packets for
output through the Serial Control port when XDS recovery
has been enabled.
Figure 22. Text Position Register (Address = 03h)
D 1–FUTR. This bit selects the Future Class packets for output through the Serial Control port when XDS recovery has
been enabled.
D0–D3–x0–x3. This bit sets the Number Of Rows in the Text
D 2–CHAN. This bit selects the Channel Information Class
display. The default is 15 rows.
D4–D7–y0–y3. This bit sets the Base Row of the Text dis-
play.
The default value in this register is set to FFh, which produces a 15-row display with base row 15. Entering a new
value in this register can alter the size and placement of the
Text display. For example, to produce an 8-row Text display
packets for output through the Serial Control port when
XDS recovery has been enabled.
D 3–MISC. This bit selects the Miscellaneous Class packets
for output through the Serial Control port when XDS recovery has been enabled.
!"
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ZiLOG
D4–PUBL. This bit selects Public Service Class packets for
D 3–dLOK. Active High, indicating that the state of the
output through the Serial Control port when XDS recovery
has been enabled.
LOCK signal has changed. The SS register must be read to
determine the current state.
D5–D7–s0–s2. This bit selects a set of secondary parame-
D 4–dSCH. Active High, indicating that a change in selected
ters, tabulated below, to be used in filtering the XDS data
when XDS recovery has been enabled.
channel activity has occurred. The Line 21 Activity register
must be read in order to determine if the selected data channel is active.
Table 17. XDS Secondary Filter Settings1
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Notes:
1. Setting this register to 00h turns XDS data recovery off.
Setting bits D 0 through D 4 enables XDS recovery for the
classes selected, as qualified by the secondary filter (bits
D5–D7). If bits D0–D4 are all set to “1”, all classes of XDS
data will be output, even the reserved and undefined
classes.
2. The Time Information includes the Time of Day (TOD) and
Local Time Zone (LTZ) packets.
3. The VCR Information selects TOD, LTZ, Net ID, Local Call
Letters, Impulse Capture, Tape Delay, Composite 2, and
Out-of-Band Channel Number packets for recovery.
D5
D4
D3
D2
D1
D0
dTXT dCAP
dXDS
dSCH
dLOK
EOF
DLE
res
R/W
R/W
R/W
R/W
R
R
R
D7
D6
R/W
Figure 25. Interrupt Request Register (Address = 06h)
D0–res. Reserved.
D1–DLE. Active High, indicating that the data line has end-
ed. This bit clears in each field a few lines after row 15.
D2–EOF. Active High, indicating that the video signal is
currently at the end of a field. This bit clears in each field
a few lines after row 15.
tivity has occurred. The Line 21 Activity register must be
read to determine if XDS data is active.
D 5–dXDS. Active High, indicating that a change in XDS ac-
tivity has occurred. The Line 21 Activity register must be
read to determine if XDS data is active.
D 6–dCAP. Active High, indicating that a change in a cap-
tion data channel activity has occurred. The Caption Activity Register (Address 08h) must be read to determine exactly which caption channels are now active.
D 7–dTXT. Active High, indicating that a change in a Text
data channel activity has occurred. The Caption Activity
Register (Address 08h) must be read to determine exactly
which text channels are now active.
Note: Except as noted for the case of D1 and D2 above, the mas-
ter device must write a 1 to the appropriate bit in the Interrupt Request Register to clear the Interrupt. Writing a
1 to any valid bit position, the Interrupt Request Register
is equivalent to CLEARing a interrupt request on that bit.
Interrupt Mask Register Address = 07h
Interrupt Request Register Address = 06h
Bit
D 5–dXDS. Active High, indicating that a change in XDS ac-
Bit D7
D6
D5
dTXT
dCAP
R/W
R/W
D4
D3
D2
D1
dXDS
dSCH dLOK
EOF
DLE
DAV
R/W
R/W
R/W
R/W
R/W
R/W
D0
Figure 26. Interrupt Mask Register Address = 07h
This register identifies which activities in the Interrupt Request Register are used to cause an interrupt. Setting a bit
to a 1 enables the interrupt when the corresponding event
becomes active. Setting all bits of this register to zero disables interrupts. The Caption Activity Register Address =
08h.
!"
()*++,
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ZiLOG
Caption Activity Register Address = 08h
Bit
D7
D6
D5
D4
D3
D2
D1
D0
T4
T3
T2
T1
CC4
CC3
CC2
CC1
R
R
R
R
R
R
R
R
Figure 27. Caption Activity Register (Address = 08h)
D0–D7–Activity Bits. These locations indicate the activity
bits for the Line 21 data channels CC1–T4. Each bit is set
High when a mode setting command for its data channel has
been received on Line 21. The bit is cleared to the Low state
if no activity is detected in that data channel during the next
12–16 seconds or if there is a loss of lock.
XDS Data Recovery
The Z86229 is able to recover Extended Data Services
(XDS) information from the input video signal. This data,
formatted according to EIA–608 specification, can contain
a wide variety of information about current and future programs, the channel currently tuned, other channels, and miscellaneous data including time of day.
bytes. The external TV control processor is not required to
send a READ SELECT command in order to read these data
bytes.
When the XDS Filter register is set to 00h (the default state),
XDS recovery is disabled.
Caution: When XDS data recovery is enabled, the external con-
troller should never perform any other read operation,
except for SS reads in the beginning of field 2. This
situation is most easily accomplished by using the end
of field (EOF) or data line end (DLE) interrupt to locate the end of field 2 or the vertical blanking interval
(VBI) of field 1. From that point, the controller can
perform the READ SELECT and READ functions
during this portion of the video frame. Commands other than READ SELECTS do not interfere with XDS
data recovery regardless of their position in the video
frame.
Some examples of the WRITE commands used to set the
XDS Filter Register in the Z86229 are indicated in Table
18. The XDS Filter Register bit assignments are defined in
the Z86229 Internal Register section of this specification
(see page 30 for details).
Note: XDS data is only present in the even field.
Table 18. XDS Data Extraction—
Example Filter Settings
The Z86229 can recover XDS data even while performing
its normal caption decoder or OSD functions.
XDS data packets are tagged according to a Class/Type system defined by the EIA–608 specification. The Z86229 can
be programmed to filter the XDS data stream to extract only
the classes of interest to the application. An additional level
of filtering is provided that permits selection of certain
groups of packets that are useful in specific applications.
XDS filtering not only reduces the traffic on the serial bus,
but it also reduces the load of the TV/VCR control processor, thereby simplifying external XDS decoding.
XDS data recovery is enabled by selecting one or more
classes in the XDS Filter register. Optionally, a secondary
filter code can be specified which further limits the packets
to be recovered. When XDS recovery is enabled, filtered
data pairs are loaded into the serial output registers of the
Z86229 immediately upon receipt and in the order received.
The DAV and RD2 bits of the Serial Status (SS) register
then goes High, indicating the availability of two output
;5
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1%= 7
1%#
P-Q
"%%+.#($$%.'.&>
$&A$#9
PQ
$:$.2.:($$%.'.&>
$&A$#9
<C5%$2.3/(#5$Program
Blocking#..'.&>$&A$39
P4Q
"%%?'.&>$&A$#9
PQ
"%%($$%.'.&>$&A$#9
P
Q
<25$2.$&A$#9<C5%$
F$.&C<25.36<7.#
&.%<26<7'.&>5$2C
&%%.(%.#..9
<C5%$2.3/(#2'%2
"(%&>:<*.#*
P4Q
*5$2.$&A$#9%&
<<!&.%.%%$
2'(%.'($<.'%.3
2'.#(5+.#C.%
!(2/$'.&>5$$&A$39
!"
()*++,
-.+/
ZiLOG
Filtered XDS Data Format
Filtered XDS data is output from the Z86229 in the order
it is received on Line 21. The XDS filter function is essentially creating a new, smaller stream of XDS data packets.
This new data stream looks exactly as though the Class and
Type specified in the XDS Filter Register (05h) are the only
data encoded on Line 21 of field 2. The filtered data output
from the Z86229 is in full compliance with EIA–608 specifications for XDS data streams (headers and control codes
intact). See the Note paragraph in the next column for a special exception to this rule.
XDS data and header information (including START,
CONTINUE, and END commands) are passed through the
filter for the XDS class and type specified in the XDS Filter
Register. All other Line 21 data is filtered out. This data is
neither output nor used to generate a data available flag
(DAV) in the Serial Status Register.
To properly read filtered XDS data from the Z86229, the
master device must first write the XDS Filter Register (05h)
with its required XDS Class and Type information. For example in Z86229, in order to extract ONLY the Line 21 Program Rating information, the master must write the value
61h to the XDS Filter Register. The master should then poll
the state of the DAV bit in the SSR until DAV = 1.
As soon as DAV=1, the master may initiate a 3-byte read
in the normal manner (XDS data bytes always arrive in
pairs, so it is safe to assume that RD2=1 when DAV=1 in
the SSB). A 3-byte read always yields two data bytes, which
in this case is the first two bytes of the Current Class, Program Rating Type XDS data stream encountered on Line21
field 2. The master device must then interpret those two
-
bytes according to the EIA–608 specifications for Current
Class, Program Rating Type data. Refer to EIA–608 for data
formats.
The XDS filters on the Z86229 greatly reduce the amount
of field 2 data passed on to the master device for further processing and interpretation; however, the master device must
still interpret the filtered data stream in accordance with
EIA–608. The filtered data stream from the Z86229 is in
full compliance with the EIA–608 specification. In other
words, the filtered data stream contains all the XDS command and data packets, in standard EIA–608 format, but
only for the selected XDS Class and Type(s).
Note: The Z86229 XDS filter for Program Rating information
behaves differently than all other Z86229 predefined
XDS filters. This change has been made to minimize the
amount of data passed through the Program Rating XDS
filter, thereby minimizing the interpretation and communications load on the master device. When the XDS Filter
Register is set to 61h (Class=01h (Current), Type=05h
(Program Rating) is the only data from the Line 21 field 2
that passes through the filter.
1. Program Rating Packet: [xxh,xxh]. The Current Class
Program Rating data byte pair as defined in EIA–608.
The program’s rating is encoded per EIA–608 in the xxh
byte pair.
2. The END Packet [0Fh,CHKSUM]. A two-byte packet
that includes a CHKSUM computed per EIA–608. The
checksum calculation includes the START packet
[01h,05h], even though this value was not passed through
the filter.
!"
()*++,
-.+/
ZiLOG
Z86229 COMMANDS AND REGISTER SUMMARY
Table 19. Z86229 Summary of Control Commands
-
<
!
+
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"
"
BFF
1
4+C4CC <.C$/3&22.#K(&$2#9<C<
&22.#./%C.%%C'&5##5.(%:C#A&/(#
$C$.%'$%59<CK(&&./$#8C(/:
9
C
!./3&22.#5$($2#9<C!&22.##
.55&C.(5C/C$.%.(67$:$.#&./
F&(##'#5C.(9
44C9994C4C $.%3&+36+7.$(#2#%39<C&22.#.&(.%%3
&5.$:5:%/3&22.#C5$244C999944C4C9
2#&22(&.&./3&C$1#/3#:.3&C$1:#..$:
C'.$9<C$:C(%#&5.%.8+/3544C5%%8#
/3+/354C9"C#5C4C/3C'$$.#35$(9
[email protected]
<?%&.%#.'[email protected]$<F6<@<-7#..&C.%5$
'$&:$#'%.39
[email protected]
C
%&.'$'$:$.22#?&$2'%.5$#'%.38C$8C(.
&#$.2$./%#9
[email protected]
./3&22.#(#../3$.#K(&/32A:
C&5C$:$#5#/3C.##$5%#6"I75C
&22.#C('($:$9"##[email protected]$A.%#C
&22.#5%#"I9
[email protected]
./3&22.#8C&C(#..8/3$.#K(&
/32A:C&5C8&&(A$:$.$:8CC
#5#/3C.##$'$5C&22.#6"I"7C('(
$:$.#:C/C$:$9%3"##[email protected]$
A.%#C&22.#5%#"I9
4
C
"&22.#$.#/3C2#9
4C
"&22.#$.#8/3C2#9
[email protected]
<CB<&22.#$K($8/3F&(9<C5$/3C8$
??C
&22.#.#&%(#C
$:$.##$6"I-7/:8$9<C
&#/36??C7C#../8$9
!"
()*++,
-.+/
ZiLOG
Table 20. Z86229 OSD Display Mode Commands
-
<,!
<?<<
<
4
!
B
68C(/%
0:C'7
C
C
C
C
C
C
C
"C$$C
1
.$$.:$($5$8C<?<<2#
K(A.%5#%#5$867
./%C.<F3'5#'%.3
./%C.''3'5#'%.3
K(A.%5''&.'#5&.'67
K(A.%5$.#'%.3#22$3
K(A.%5$.#'%.3#22$3
<C&22.#C#'%.3$8.#2AC&($$&C.$&%(29
<C%8$#$//%5 rr #:.C#'%.3$89+5 rr '&5.
(/%0:C$894$F.2'%$$DC8(%#%&#'%.3$8-O$$DC
8(%#%&#'%.3$8C$(/%0:C9
<C&22.#C'C3&.%$88C$C%8$#$//%5 rr
#:.C'C3&.%$8 rr A.%(5$2C4C9
<C&22.#'%.&C&($$.C&C.$.&$&%(2'#:.#
/3&&8C&C&./.3A.%(5$2CC6&%([email protected]$C
"'.&9
<C&22.#8$C#../3##C&($$&($$%&..#
C&$2C&($$9
<C&22.#2.'C&($$'C3&.%$8C#'%.3$8#:.#
/3C%8//%5C rr /39+-5$$D./%#'%.35C$89+
5$$D#&..(/%0:C$89
<C&22.#C.2.C"&22.#/('&5.(/%B#
&C.$.&$9
<C&22.#C/5C$/3('#:C$.%
&22.#F&(5$.''$F2.%3C(2/$55$.2#:.#/3
C/39
<C&22.#C)$.'C&C.$.&$5$&9
<C&22.#CF##C.$.&$5$&9
0B "C$$C
,<
"C&&C
B<0"
"C##C
B< "
"-C$$C
B<0"
+B
B"<
"##C
"CC
)"0
?<!
-CC
CC
Table 21. Summary of Z86229 Internal Registers
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C
C
C
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C
C
C
C
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+,+?
3
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0
3
$
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D1
D0
B*
4
=
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C
3
$
#?
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C
3
$
,+
#0
#0
<
*=
C
F
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#=
#=
-
0=
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C
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4
4
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-.+/
ZiLOG
ON-SCREEN DISPLAY
OSD Operation
The Z86229 has a fully programmable, general purpose OnScreen Display (OSD) built in. The user can supply information for display through the serial port. In addition to all
the normal and extended features of the VBI data display
modes, the OSD mode also has available added graphics
characters, Double-High and Double-Wide characters, and
the ability to position the display anywhere on the screen
with an adjustable (vertical) box size. The Double-High and
Double-Wide characters are especially useful for creating
OSD screens for display inside a Picture-in-Picture (PiP)
window. The OSD display mode can use either 13 or 15
lines per row, with a box or drop shadow. The default is 15
scan lines per row in addition to the drop shadow. Enhanced
attributes are always enabled.
The 15 scan line per row display can only show 13 rows
on-screen when in the NTSC mode. Rows 14 and 15 is offscreen and should not be addressed. In the PAL mode all
rows are visible.
The 15 scan lines per row mode display can show the full
graphic characters and accented capital letters and descenders without the potential overlap that would result from the
13 scan line per row display. If the OSD display mode is
changed to a 13 scan line per row mode, the top two scan
lines of any graphics or accented capital letter is “ORed”
together with the bottom two scan lines from the row above.
In 13 line-drop-shadow mode, it also results in a side shadow effect. Graphics characters should not be used in the 13line drop-shadow mode.
OSD Character Set
There are 256 possible addresses in the OSD character set.
Figure 28 illustrates the address map in the range 00h–BFh.
This portion of the addressable space contains the control
bytes and regular character set. The address map in the range
C0h–FFh is illustrated in Figure 17.
These addresses are shared by the Extended Character set
and the Graphics Character set. Any particular OSD screen
can use one or the other of these sets of characters but not
both.
The character set in force is controlled by the type of display
mode being invoked. When the Drop Shadow is being used,
by default, the Graphics Character set is displayed in response to an address in the C0h–FFh range; however, if a
BOX display is used, the Extended Character set is invoked.
In either case the user can switch to the other set by means
of the appropriate command (GRAPHICS or EXTENDED).
The VIN/INTRO pin serves as the input for a Vertical Pulse
from the TV receiver when V Lock = VIN mode is enabled.
This condition permits an OSD display even when no video
input is present. If this mode is not required, the default state
V Lock = VIDEO should be active. This pin then carries
the INTRO output signal.
OSD Commands
OSD commands are one- and two-byte commands. They are
used to control the loading of data for OSD display and their
presentation to the screen. Normally, the OSD display mode
uses 15 TV lines per display row to enhance the OSD presentation.
The two-byte commands enable direct access to any location on the display screen. The user can customize displays
by using these commands. Each command byte pair consists
of an instruction byte followed by a data byte. (See A Sample OSD Program on page 39.)
Note: In this product specification, one- and two-byte com-
mands are written as one or two two-digit Hex values,
separated by a comma, within curly braces. For example,
the WRITE CHAR command for entering the letter A as
a single-width character would be shown in this document as {A3,41}. This command would write the letter A
to the current cursor position of the display row being addressed. Refer to the Serial Communications Interface
and Commands sections for further details of the serial
communications and the OSD commands (see pages 22
and 26, respectively).
The one-byte commands provide a simple means of creating
OSD displays using preset screen formats built into the part.
These built-in modes provide the user with a simple way to
generate OSD screens. Two preset display modes are available called POPSET and TEXTSET.
!"
()*++,
-.+/
ZiLOG
Figure 28. OSD Character Set
!"
()*++,
-.+/
ZiLOG
Using POPSET
POPSET provides an OSD mode that operates in a fashion
similar to the Caption Pop-on mode. The POPSET command organizes the memory into two eight row blocks, one
visible on-screen and the other off-screen. An OSD screen
can then be created by loading the off-screen memory by
the command sequence POP ROW SEL, WRITE CHAR ..
WRITE CHAR .. POP ROW SEL .. WRITE CHAR .. WRITE
CHAR. The data can then be presented for on-screen display
with the FLIP command.
The following is an example of a command sequence that
creates an OSD screen using the POPSET mode. It creates
a typical menu screen used in television receivers. It should
be noted that in this document, commands are written as either a one- or two-byte HEX value, separated by a comma,
within curly braces (that is, a sample two-byte OSD command: {A1,00}).
In the sample programs below, a comment field can be written following the command to describe the action of the
command or sequence of commands, where appropriate.
The comment field is identified by an asterisk (*), and any
text following the * is taken as a “comment”. Therefore, to
include a comment in the program, simply add the * at the
beginning of the function description.
A Sample OSD Program
#
1
PQ
%&<2#9
<C5$/%&>5&22.##'%.3
*(/%B#&C.$9.&C
&C.$.&$$#8CCB<
0"&22.#9
P"Q
%&B&($$.&C.$.&$
&%(2
P"Q
A&($$
P"
Q
P"Q
P"Q
P"Q
P"-Q
P"--Q
P"-Q
P"-4Q
"5$&C.$8$"
%&.9
)$2#&#8$&C.$&%
R*S8$&C.$&%-N9
RS
RS
RS
RS
The next block of commands displays AUDIO in row 4 with
Double-Width.
P"-Q
P"Q
P"Q
P"-Q
P"Q
P"--Q
P"-Q
P"-4Q
%&B-&($$&C.$&%
($$&C.$&%
)$2#&#8$&C.$&%
R"S8$&C.$&%-N9
R,S
RS
RS
RS
The next set of commands displays the word “TIME” in row 6
with Double-Wide characters. Spacing is obtained without the
A2 Cursor Set command to illustrate an alternate means of
column alignment.
P"Q
%&B&($$&C.$&%
#
1
P"Q
)$2#&#8$&C.$.&$&%
P"Q
(/%B#'.&&C.$8$
&C.$.&$&%(2N
P"-Q
R<S8$&C.$&%-N9
P"-Q
RS
P"-#Q
R S
P"-Q
RS
P"Q
%&B&($$&C.$&%
SET UP is displayed in row 8 using Double-Wide chars.
P"
Q
P"Q
P"Q
P"Q
P"-Q
P"-Q
P"Q
P"Q
P"Q
%&B
($$
)$&C.$.&$
RS
RS
R<S
RS
R,S
RS
CLOSED CAPTION displayed in row 10 using Double-Wide
characters. The last letter, N, appears in character column 30
and 31.
P""Q
P"Q
P"Q
P"-Q
P"-Q
P"-4Q
P"Q
P"-Q
P"--Q
P"Q
P"-Q
!"
%&B.
($$
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RS
RS
RS
RS
RS
RS
RS
RS
()*++,
-.+/
ZiLOG
#
P"-Q
P"Q
P"-Q
P"-Q
P"-4Q
P"-Q
1
R"S
RS
R<S
RS
RS
R!S
The line, Select: ENTER EXIT: MENU, appears in row 12,
starting in character column 2. These are displayed as singlewide characters.
P"Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"-Q
P""Q
P"Q
P"-Q
P"-Q
P"-Q
P"-Q
P"Q
P"Q
P"Q
P"-Q
P"
Q
P"Q
P"-Q
P""Q
P"Q
P"-Q
P"-Q
P"-Q
P"Q
PQ
%&B&
"!&C.$
RS
RS
R%S
RS
R&S
RS
RIS
RS
RS
R!S
R<S
RS
RS
RS
RS
RS
RFS
RS
RS
RIS
RS
R S
RS
R!S
R,S
4&22.#5%'22$''':
C5(%%2(&$9
Using Textset
TEXTSET features an OSD mode that paints on the screen
in a manner similar to a Text Mode display. The memory
is organized using the current information in the Text Position register, and the display follows the current setting
-
in the Display register. The default display parameters for
the OSD are 15 lines per row, Drop-Shadow mode. The
TEXTSET command can be followed by successive
WRITE CHAR commands interspersed with the RETURN
command at the appropriate points to paint on an OSD display starting at the top of the Text window. These commands are set by the Text Position register, moving to the
next line at each RETURN command. The display scrolls
if a RETURN command is sent when at the bottom of the
Text window. A subsequent TEXTSET command clears the
screen, thereby generating a new OSD screen.
The following example shows an OSD display generated
using TEXTSET. This screen is a paint-on rather than popon. Features like flash are included in the command sequence for demonstration purposes.
The Text display is first set to 4 rows at the bottom of the
screen.
#
1
P-Q
<F'$:5$/.$8-$8
P
Q
#'%.35$+?2#
%;$8
P"Q
+?+%(>'0(&C.:#
PQ
%&<?<<2#
The next two commands are used for positioning and color.
P"Q
P"
Q
P"+Q
P"Q
P"-Q
P"Q
P"-Q
P"-Q
P"-Q
P"-Q
P"Q
PQ
P"Q
P""Q
P"-Q
P"
Q
P"Q
!"
($$&C.$'
#&#2.>#&C.$9($$
2A
#&#.$4%.C($$2A
RBS(/%B#&C.$&%
R"S(/%B#&C.$&%
RS(/%B#&C.$&%
R!S(/%B#&C.$&%RS(/%B#&C.$&%
R!S(/%B#&C.$&%
R)S(/%B#&C.$&%
RS(/%B#&C.$&%
($$&C.$'
"&%$%%8&($$2A
&C.$'
R<S:%8#C&($$2A&C.$
'
RCS
RS
()*++,
-.+/
ZiLOG
#
1
P"Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"-Q
P"4Q
P"Q
P"Q
P"Q
P"-Q
P"4Q
P"Q
P"Q
P"Q
P"Q
P"-Q
P"
Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"Q
PQ
R$S
RS
RS
RS
RS
RS
R.S
RS
RS
RS
R$S
RS
R.S
R#S
RS
RS
RS
RS
RS
RS
RCS
RS
RS
R.S
R$S
RS
R.S
R9S
P"Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"-Q
P"Q
P"+Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"Q
RS
R%S
RS
R.S
RS
RS
RS
RS
R.S
R>S
RS
RS
R.S
R%S
R%S
RS
#
1
P"Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"Q
PQ
P"Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"-Q
P"Q
P"4Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"-Q
P"Q
P"Q
P"-Q
P"Q
P"Q
P"Q
P"Q
RS
RS
R&S
RS
RS
RS
R.S
R$S
R3S
R'S
R$S
RS
R&S
R.S
R(S
RS
RS
RS
RS
RS
RS
RS
R2S
R2S
RS
R#S
RS
R.S
RS
RS
R%S
R3S
R9S
At this point all 4 rows are on-screen. The following wait
command holds the display for a period = (12x16)/30 seconds.
P"Q
B.5$9-&#
Create a smooth scroll to clear the screen with the following 4row sequence.
PQ
P"4Q
PQ
P"4Q
PQ
P"4Q
PQ
!"
($5$$89
8.5$.2
($&#$89
($C$#$89
($5($C$89
-
()*++,
-.+/
ZiLOG
The WAIT command can also be used to control the appearance of two OSD displays in sequence without tying
up the master device for the total display time. In the following example, the POPSET mode is used to pop on two
sequential menu screens with a built-in pause between the
two displays. In this case, the WAIT is placed just before
the most recent FLIP command. This condition allows the
entire command sequence to be sent to the Z86229 at one
time. Because the RDY bit is set by the WAIT command,
this condition also allows the FLIP to be input as well.
#
1
P"4Q
P"-Q
P"
Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"4Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"-Q
P"Q
P"Q
P"-Q
PQ
P"-Q
P"4Q
P"Q
P"Q
P"-Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"Q
$..8&$#'%.39
RS
RCS
RS
RS
RS
R8S
R.S
RS
RS
RS
RS
T%T
R3S
RS
R.S
RS
RS
RS
RS
RS
($
R#S
RS
RS
RSS
RS
RS
R'S
R.S
RS
RS
R&S
R9S
The command sequence would be as follows:
#
1
PQ
P99Q
P99Q
P99Q
PQ
P
Q
P99Q
P99Q
P99Q
P"Q
PQ
4&22.#94%'22$''':
C5$2(&$9
! ($#'%.3#22$3
$.#9
&$:$.&22.#5$&#
#'%.3
B.&#
4&22.#5%'22$''':
C&#2(&$9
Using The Graphics Character Set
The following example creates an OSD screen which illustrates several features of the Z86229 including the use of
the Graphics character set to generate a large font word. The
particular features shown are purely for demonstration purposes and are not intended to suggest a particular application.
Using the WAIT Command
The WAIT command suspends serial port communications
for a period of time. The TEXTSET example above used
the WAIT command in two ways: first, to hold a display
on-screen for a period of time before taking a second action,
and second, it was used to create a smooth scroll by timing
the wait to the scroll rate.
-
%&''2#
&$:$.&22.#5$5$
#'%.3
For the sake of brevity, the “text” to be displayed is shown
as a string within quotes rather than as the actual command
sequences required. Single quotes (‘ ’) signifies standard
characters, while double quotes (“ ”) signifies Double-Wide
characters.
PQ
P"Q
P"Q
!"
%&''2#
%&B
A&($$
()*++,
-.+/
ZiLOG
PQ
P"&Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"Q
P".Q
P".Q
P"Q
P"/Q
P"Q
P"/Q
P"Q
P"/Q
P"Q
P"/Q
P"#Q
PQ
PQ
%&''2#
P"Q
")!&C.$
R<0" !<"<!4S
P"Q
%&B
P"Q
($$
P"
Q
"&C.$
R<C
C.2.35.($S
P"-Q
%&BP"Q
($$
P"-Q
+%(&C.$
R/##'%.3:.'9S
P"Q
%&B
P"Q
A&($$
P"Q
"3.,#$%#
R%$.#,#$%2.3/(#S
P"
Q
%&B
P"Q
A&($$
P".Q
"%%8&C.$
R(/%B#S
P"Q
%&B
P"Q
A&($$
P"&Q
" .:.&C.$
R)$.'C&&./&$.#%>S
The next group of commands use Graphic Char patterns to
make the two row word HELLO. The data byte of the WRITE
CHAR command is the address location for the graphic cell
required as illustrated in Figure 5.
P"/Q
P"Q
P"Q
P
-Q
P"Q
P"Q
P"Q
P"Q
P"Q
P"/Q
P".Q
P"Q
P"5/Q
P"Q
P".Q
P"Q
P".Q
P"Q
P"5.Q
P"5Q
%&B
A&($$
"3.&C.$
)$.'C&2#&..C$($
C.#&C.:#.$%$9
RS
RS
RS
RS
RS
)$.'C&%%
)$.'C&%%
RS
)$.'C&%%
RS
)$.'C&%%
RS
)$.'C&%%
RS
)$.'C&%%
)$.'C&%%
%&''2#
%&B
A&($$
"3.&C.$
RS
RS
RS
RS
RS
)$.'C&%%
)$.'C&%%
RS
)$.'C&%%
RS
)$.'C&%%
RS
)$.'C&%%
RS
)$.'C&%%
)$.'C&%%
5%'
Manual Row Mapping and Control
For most OSD displays, the POPSET, POP ROW SEL,
FLIP, TEXTSET, and RETURN commands should be used
to control row positioning.
TEXTSET mode provides automatic row allocation from
the top to bottom of a screen with all rows continuously visible. Additionally, TEXTSET screens have a definable vertical window size and position, allowing support of automatic text scrolling at the bottom of the window.
POPSET screens are created in off-screen memory while
the previous screen is displaying. Up to 8 rows of characters
can be defined. These rows can be mapped to any of 15 display rows using the POP ROW SEL command. Doublehigh rows may also be defined with POP ROW SEL. The
FLIP command is then used to “pop-on” up to 8 rows of
characters replacing the previous screen. The off-screen
rows may be mapped to the same row numbers as the onscreen rows.
In some applications, it may be necessary to access the display hardware at a lower level to achieve special screen effects. Examples of these special situations include the following:
1. More than 8 on-screen rows required in a “pop-on”
style screen.
!"
-
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-.+/
ZiLOG
2. Characters must be added dynamically to an on-screen
display.
is moved to a new display row, the original third row is disabled, and the new third row is mapped and enabled.
3. On-screen rows must be dynamically moved, disabled,
or enabled.
#
The Z86229 supports manual screen mapping and display
control commands to handle these special applications.
These commands allow each of the 16 physical rows of
character memory implemented in the device to be mapped
to any of 15 display row positions.
Additionally, the 16 physical rows can be set for single or
double height and independently enabled and disabled.
Manual row mapping and control commands should only
be used in the POPSET OSD mode.
The procedure for manual row control is as follows:
1. Use the POPSET command to select the OSD pop-up
mode. This command prepares the Z86229 for OSD
input, clears the row maps, and erases character
memory.
2. Select a physical row (0 through 15) using the PHY
ROW SEL command.
3. Use the WRITE MAP command to set the display row
(1 through 15), Double-High bit, and enable bit of the
selected physical row.
The CURSOR SET, WRITE CHAR and WRITE CHARD
commands are used to position the cursor and write the characters in the selected physical row.
A physical row may be re-selected at any time to change
its characters, row maps, Double-High mode, or enable status. For example, it may be desirable to load several rows
of characters into physical memory without enabling them.
All of the rows could then be made to “pop” onto the screen
simultaneously by setting their enable bits.
The following example uses manual row mapping and control to write three rows of characters. The first row is a Double-High row that is enabled before the characters are sent.
This condition allows the characters to “paint” onto the
screen as they are received. The second and third row are
not initially mapped or enabled when the characters are
written. They are then mapped and enabled after a two second pause. A new row is then created off-screen to replace
the third row. Finally, after a 2 second pause, the second row
--
PQ
P"Q
P"-Q
1
%&<2#
%&'C3&.%$8
.'#'%.3$8./%
#(/%
P"Q
($$
P"Q
)$
(/%B#F
R<C4$8S
P"Q
%&'C3&.%$8
P"Q
($$
P".Q
%%8
:%8#F
R<C8$8.$S
P"Q
%&'$8
P"Q
($$
P"Q
3.
R:%8#F./%#.5$.'.(S
P"-Q
B.&#
C2.'.#./%
P"Q
%&'C3&.%$8
P"-Q
.'#'%.3$8./%
P"Q
%&'$8
P"-Q
.'#$8./%
$'.$.8$8$'%.&$8
P"
Q
%&'C3&.%$8
P"Q
($$
P"Q
3.
:%8#F
R A#.5$.'.(S
P"-Q
B.&#
.>C2#5##'%.3
P"Q
%&'C3&.%$8
P"-"Q
.'#'%.3$8./%
#(/%
P"Q
%&'$8
P"-Q
./%
P"
Q
%&'$8
P"-+Q
.'$8./%#(/%
!"
()*++,
-.+/
ZiLOG
DEMONSTRATION PROGRAMS
Communicating with the Z86229
Communications with the Z86229 is accomplished using its
serial communications interface. Through hardware setup,
this interface can be configured into either of two serial protocols, I2C or SPI. The details of hardware setup have been
provided in the Serial Communications Interface section
(page 22) and are not dealt with here. It is assumed that the
user is familiar with the serial protocol requirements.
and LOCK bits are High. This condition indicates that the
serial port is ready for further input, that the input video signal was in Field 1 at the time the status was read, and that
the part is operating in video-lock mode.
The IICO program is exited by entering a Control+C (^C)
character.
For example, entering the following single byte commands
would generate the following:
Note: In the following descriptions <ENTER> means press the
Enter key.
I2C Operation
The Z86229 is configurable as an I2C slave device. The PC
communicates with the Z86229 through its parallel port.
These programs are not intended as examples of how to program the application, but are only provided as a means of
illustrating the serial control process and the capability of
the Z86229.
C'.$
C'.$#'%.32#
#&#$!9
C.:C?)$.1#'%.3
2#&#<2$!9
($C#'%.32#
#&#$!9
General Commands
IICO Program
%
C
C
<
!
+
4+C4CC
C
44C99944C4C
Caption/Text Display Mode Commands
IIC Command Byte >
The user may enter any valid one-byte command such as
FBh (Reset) or 00h (NOP) and then hit the ENTER key. The
screen then displays the byte entered and the SS register
contents read:
IIC Byte = 00
IIC Status = 83h
The text above shows that the NOP command was entered.
The SS register contents, 83h, indicates that the RDY, FLD,
4+4
C
The commands that control most of the display capability
of the Z86229 are all one-byte commands which can be entered using the IICO program. These commands are tabulated below for convenience.
The three programs available are titled IICO, SCRIPTI, and
XDSCAP. These programs have been compiled and run satisfactorily with the Z86229 in a test board. Compiled versions are available on disk. Contact your local ZiLOG sales
office for further information on these programs.
This program sends one byte to the Z86229 without checking the status of the READY bit. The program returns the
contents of the Serial Status (SS) Register after the command has been entered. When the program is active the
screen displays:
7
<
<
<
<-
!"
CPTX Command Code
#-
C
C
4C
C
C
C
+C
C
#11
C
-C
C
C
C
C
"
-
()*++,
-.+/
ZiLOG
XDS & Miscellaneous Display Mode
Commands
Script Files
XDS Command
8 C
C
C
C
C
-C
7
?)
?)
?4
?4
!
!
/*>
!
44
!
44
!
44
Note: *Changing the ON/OFF state of the 16-Second Erase
Timer has no affect on the current display mode in operation.
Script files can be generated to perform all of the setup and
control functions required to use the part in an application.
The script files that follow are examples of such files used
to setup the Z86229 for different operating conditions.
Some of the files contain only a single command, while others include several commands. The user should refer to the
Command and Registers section for details. Although the
following examples are organized according to a particular
register, some of the files contain information for several
registers.
Configuration Register Script Files
1%
-
SCRIPTI Program
This program is designed to send any number of one or twobyte commands to the Z86229. The list of commands to be
executed are contained in Script files that have the extension
.SER. Examples of such files are presented in the following
paragraphs. SCRIPTI can be used to control the display
modes in the same manner as the IICO program, except that
the one-byte command to be sent must be in a Script file.
For example, a file called CC1.SER would contain the onebyte command:
4)
4)*0
4)!
4)"
1
PQ
PQ
PQ
P
Q
PQ
PQ
PQ
PQ
P44Q
{17}* send CC1, decoder ON
PQ
The program is invoked by typing:
&5:2
!< .>$:$&%.$
&5:F*=N0=
+F*'(%5$'
$C#'%.3
&5:/.&>#5.(%.
($C#'%.3&$
C.:#'%.3$:$
N<
C.:F'$:$
/.$8$8
&5:$:$<*D
C.:*+%"
SI File_name<ENTER>
Display Register Script Files
Note: Enter the file_name without the .SER extension.
!
The screen displays:
EEG CCD2 Serial
Version x.xx
1%
-
Interface
Script
Player
<
Slave Address is 28h
<
Script File Done
<
The responding slave address is reported to the screen.
When all the commands in the file have been successfully
sent to the Z86229, the PC returns to the system prompt.
The program checks the RDY status before sending each
byte. If, during the entry of a command, the RDY bit is not
found to be a “one” after an extended wait, the program reports the contents of the SS register and then continue
checking for RDY Script Files.
-
<"
!"
1
PQ
#'%.3$:$#5.(%
&#
PQ #'%.3$:$<F#$'
C.#8
PQ #'%.3$:$<F
%'$$8
PQ #'%.3$:$<F#$'
C.#8%
PQ A%.##$'F
PQ $85F/.$8
PQ ./%"C.&#2#
()*++,
-.+/
ZiLOG
H Position Register Script Files
XDS Filter Register Script Files
1%-
1%
-
1
4"
PQ
4
P-Q
44"
40
4
4< 4*
PQ
P-Q
P
Q
P
Q
PQ
0
0
PQ
PQ
0
PQ
0+
P.Q
1
$/F
A/F$:C9G
65$2&$7
2A/F%59G65$2
&$7
&$/FN2.>+F+%(
Text Position Register Script Files
1%-
<
<
<
<"
P44Q
P4Q
P4"Q
P+"Q
1
<F/.$8$8
<F/.$8$8
<F/.$8$8
<F/.$8$8
4"
4
P4Q
PQ
?5%$.%%
?5%$9<($
55?$&A$3
?5%$.%%&($$
&%.
?5%$&($$
/.#&%.
?5%$.%%5(($&%.
?5%$&C.%&%.
?5%$5$2&95
?5%$2%3
?5%$A&$5
Using Interrupts
XDSCAP Program
This program performs the application’s task of XDS data
recovery. XDS recovery must first have been enabled
through the appropriate XDS Filter command. Script file
examples for setting the XDS Filter are shown below.
Interrupts involve the use of the Line 21 Activity Register,
the Interrupt Request Register, and the Interrupt Mask Register. The Z86229 must be configured for VLK internal so
that the VIN signal (Pin 13) is an output providing the interrupt output signal.
The interrupt status can be polled through bit D3 of the Serial
Status (SS) Register if the interrupt signal cannot be used.
The program is invoked by typing:
xdscap<ENTER>
When the program is invoked the PC screen shows:
EEG CCD2 XDS Data Recovery Test Program
Version x.xx
Slave Address is 28h
The responding slave address is reported to the screen.
After communication is acknowledged, the program displays all XDS data recovered from those packets that were
enabled through the XDS Filter command:
{01,03}Current Program{00}{0F,7F}....etc
The ASCII characters are shown as ASCII characters while
the non-printing characters are displayed by their Hex value
within curly braces. Byte pairs, such as Class,Type, are
shown as pairs within the curly braces, separated by a comma (that is, {01,03}).
Interrupts are disabled when the Interrupt Mask Register
has been set to all zeros. Conversely, interrupts are enabled
by setting one or more of the active bits to a “1”. When enabled, the INTRO signal becomes a “1” when the enabled
mask event(s) becomes active. If more than one event has
been activated, the Interrupt Request Register must be queried to determine which event has occurred. The DLE and
EOF interrupts are cleared at the end of the field in which
they occurred.
Interrupt Mask Register Script Files
1%-
!<
!<=
!<?
!<
PQ
P
Q
PQ
PQ
1
.&A
#=.&A
#?.&A
N#;<.&A
If no data is received within approximately 45 seconds, the
program times out, reports “Data Not Available”, and exits.
Note: The XDSCAP program can also be exited by entering a
Control C (^C) character.
!"
-
()*++,
-.+/
ZiLOG
SPI Operation
The serial port of the Z86229 may be configured to operate
as an I2C or SPI interface. The Z86229 always acts as the
slave device with the master generating the required clock
and input data signals. Two C language programs available
from ZiLOG enable a PC to perform as the I2C or SPI master
device of an application. The PC communicates with the
Z86229 through it's parallel port. These programs are not
intended as examples of how to program the application, but
are only provided as a means of illustrating the serial control
process.
The two programs available, SEROUT and SCRIPT, are the
SPI equivalent to the I2C programs IICO and SCRIPTI, respectively.
SEROUT Program
This program sends one byte to the Z86229 without checking the status of the READY bit. The program returns the
contents of the Serial Status (SS) Register after the command has been entered. When the program is active the
screen displays:
FLD, and LOCK bits are “ones”. This condition indicates
that the serial port is ready for further input, that the input
video signal was in Field 1 at the time the status was read,
and that the part is operating in the video-lock mode.
When this program is used, only a modified version of the
RESET can be used. It is entered as two, one-byte commands (FBh and 00h).
The SEROUT program is exited by entering a Control C
(^C) character.
Script Program
This program is designed to send any number of one or twobyte commands to the Z86229. The list of commands to be
executed are contained in Script files that have the extension
.SER. The Script files used with the I2C version, SCRIPTI,
can be used with this program.
The program is invoked by typing:
SI File_name<ENTER>
Note: Enter the file_name without the .SER extension.
SPI Command Byte >
The screen displays:
SPI Command Byte
The user may enter any valid one-byte command, such as
00h (NOP), and then hit the ENTER key. The screen then
displays the byte entered and the SS register contents as follows:
SPI Byte = 00
SPI Return Val = 83h
The illustration above shows the NOP command was entered. The SS register contents, 83h, indicates that the RDY,
-
EEG CCD2 Serial
Version x.xx
Interface
Script
Player
Script File Done
When all the commands in the file have been successfully
sent to the Z86229, the PC returns to the system prompt.
The program checks the RDY status before sending each
byte. If, during the entry of a command, the RDY bit is not
found to be a “one”, the program reports the contents of the
SS register and then continue checking for RDY.
!"
()*++,
-.+/
ZiLOG
APPLICATION INFORMATION
The recommended schematic, component placement, and
PCB layout for a single-sided DIP design are provided in
the following figures. EMI and noise in the video frequency
range is kept to an absolute minimum by running the ground
plane underneath the entire Z86229 package length. This
design is recommended for both SOIC and DIP package
styles. Though it is not shown in the following application
information, the SMS (pin 6) must be grounded for I2C application. If necessary, please contact your local ZiLOG
sales office with any questions regarding this or other information represented in this document.
RD
GN
BOX
BL
SDO
SEN
HIN
SMS
SCK
SDAOUT
VIN/INTRO
VDD(+5V)
VIDEO
VSS
.
Z86229
1
C2
9
C5 8
7
C1
R2
C3
SMS
BOX
VDD
HIN
17
12
CA1
LPF
CSYNC
RREF
VIDEO
+5V
L1
CB1
L1
10
C3
R1
VSS(A)
11
C2
R3
C4
5
R3
SDO
R2
6
C4
SEN
C1
4
To select 1st
I2C Address
Figure 29. Z86229 Application Circuit with I2C
U1
CB1
I2 C SEL
CA1
15 SCK
14
I2C Bus
R1
18
2
3
VIN/INTRO
C5
SDA
R
G
B
13
Figure 30. Z86229 Application Circuit with I2C
Table 22. Recommended Component Values
for the Z86229 Application Circuit
"
+
,
2%
-
9
9
9
9
9
9
/.#
3
=Ω
Ω
=Ω
µ4
µ4
'4
'4
µ4
µ4
µ4
<+
!;"
!"
-
()*++,
-.+/
ZiLOG
PACKAGING INFORMATION
Figure 31. 18-Lead DIP Package Diagram
Figure 32. 18-Lead SOIC Package Diagram
!"
()*++,
-.+/
ZiLOG
ORDERING INFORMATION
()*++,/+
For fast results, contact your local ZiLOG sales office for
assistance in ordering the part required.
Package
Temperature
Speed
Environmental
D%.&
D%.&
DUU
D 01
D%.&.#.$#
Example:
Z 86229 12 P S C
is a Z86229, 12 MHz, DIP, 0ºC to + 70ºC, Plastic Standard Flow
Environmental Flow
Temperature
Package
Speed
Product Number
ZiLOG Prefix
!"
()*++,
-.+/
ZiLOG
Pre-Characterization Product
The product represented by this document is newly introduced and ZiLOG has not completed the full characterization of the product.
The document states what ZiLOG knows about this product at this time, but additional features or nonconformance with some aspects
of the document may be found, either by ZiLOG or its customers in the course of further application and characterization work. In
addition, ZiLOG cautions that delivery may be uncertain at times, due to start-up yield issues.
Development Projects
Customer is cautioned that while reasonable efforts will be employed to meet performance objectives and milestone dates, development
is subject to unanticipated problems and delays. No production release is authorized or committed until the Customer and ZiLOG
have agreed upon a Product Specification for this product.
Low Margin
Customer is advised that this product does not meet ZiLOG’s internal guardbanded test policies for the specification requested and is
supplied on an exception basis. Customer is cautioned that delivery may be uncertain and that, in addition to all other limitations on
ZiLOG liability stated on the front and back of the acknowledgment, ZiLOG makes no claim as to quality and reliability according
to the Data Sheet. The product remains subject to standard warranty for replacement due to defects in materials and workmanship.
Document Disclaimer
©2001 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described
is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A
REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT.
ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO
USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are
covered by warranty and limitation of liability provisions appearing in the ZiLOG, Inc. Terms and Conditions of Sale. ZiLOG, Inc. makes
no warranty of merchantability or fitness for any purpose. Except with the express written approval of ZiLOG, use of information,
devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or
otherwise, by this document under any intellectual property rights.
!"