100353 Low Power 8-Bit Register General Description Features The 100353 contains eight D-type edge triggered, master/ slave flip-flops with individual inputs (Dn), true outputs (Qn), a clock input (CP), and a common clock enable pin (CEN). Data enters the master when CP is LOW and transfers to the slave when CP goes HIGH. When the CEN input goes HIGH it overrides all other inputs, disables the clock, and the Q outputs maintain the last state. n n n n Low power operation 2000V ESD protection Voltage compensated operating range = −4.2V to −5.7V Available to MIL-STD-883 The 100353 output drivers are designed to drive 50Ω termination to −2.0V. All inputs have 50 kΩ pull-down resistors. Logic Symbol Pin Names D0–D7 Description Data Inputs CEN Clock Enable Input CP Clock Input (Active Rising Edge) Q0–Q7 Data Outputs NC No Connect DS100316-4 © 1998 National Semiconductor Corporation DS100316 www.national.com 100353 Low Power 8-Bit Register August 1998 Connection Diagrams 24-Pin Quad Cerpak 24-Pin DIP DS100316-2 DS100316-1 Logic Diagram DS100316-5 Truth Table Inputs Outputs Dn CEN CP L L N L H L N H X X L NC X X H NC X H X NC H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care NC = No Change N = LOW to HIGH Transition www.national.com 2 Qn Absolute Maximum Ratings (Note 1) ≥2000V ESD (Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Recommended Operating Conditions Above which the useful life may be impared Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic VEE Pin Potential to Ground Pin Input Voltage (DC) Output Current (DC Output HIGH) Case Temperature (TC) Military Supply Voltage (VEE) −65˚C to +150˚C +175˚C −7.0V to +0.5V VEE to + 0.5V −50 mA −55˚C to +125˚C −5.7V to −4.2V Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Military Version DC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −55˚C to +125˚C Symbol VOH Parameter Output HIGH Voltage Conditions Notes Min Max Units TC −1025 −870 mV 0˚C to −1085 −870 mV −55˚C VIN = VIH (Max) Loading with −1830 −1620 mV 0˚C to or VIL (Min) 50Ω to −2.0V −1830 −1555 mV −55˚C −1035 mV 0˚C to −1085 mV −55˚C VIN = VIH (Min) Loading with −1610 mV 0˚C to or VIL (Max) 50Ω to −2.0V −1555 mV −55˚C −870 mV −55˚C to +125˚C VOL Output LOW Voltage (Notes 3, 4, 5) +125˚C VOHC Output HIGH Voltage +125˚C VOLC Output LOW Voltage (Notes 3, 4, 5) +125˚C VIH Input HIGH Voltage −1165 Guaranteed HIGH Signal for all Inputs (Notes 3, 4, 5, 6) Guaranteed LOW Signal for all Inputs (Notes 3, 4, 5, 6) VEE = −4.2V VIN = VIL (Min) VEE = −5.7V VIN = VIH (Max) (Notes 3, 4, 5) +125˚C VIL Input LOW Voltage −1830 −1475 mV −55˚C to +125˚C IIL Input LOW Current 0.50 µA −55˚C to +125˚C IIH Input HIGH Current 240 µA 0˚C to +125˚C 340 IEE µA Power Supply Current −55˚C −55˚C to −132 −42 mA (Notes 3, 4, 5) +125˚C Inputs Open VEE = −4.2V to −5.7V (Notes 3, 4, 5) Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 4: Screen tested 100% on each device at −55˚C, +25˚C, and +125˚C, Subgroups 1, 2, 3, 7, and 8. Note 5: Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, and +125˚C, Subgroups A1, 2, 3, 7, and 8. Note 6: Guaranteed by applying specified input condition and testing VOH/VOL. AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol fmax Parameter Toggle Frequency TC = −55˚C TC = +25˚C TC = +125˚C Min Min Min 400 Max Max 400 400 3 Units Conditions Notes MHz Figures 1, 2 (Note 10) Max www.national.com AC Electrical Characteristics (Continued) VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter tPLH Propagation Delay tPHL CP to Output TC = −55˚C TC = +25˚C TC = +125˚C Min Max Min Max Min Max 0.70 3.30 0.80 3.10 0.80 3.50 tTLH Transition Time 20% to 80%, 80% to 20% ts Setup Time 0.40 2.20 0.40 2.20 0.40 Dn 0.30 0.30 0.30 CEN (Disable Time) 0.60 0.60 0.60 CEN (Release Time) 1.40 1.40 1.40 1.50 1.50 2.00 2.00 th Hold Time Pulse Width HIGH Conditions ns Figures 1, 2 tTHL tpw(H) Units Dn CP 2.20 ns Notes (Notes 7, 8, 9, 11) (Note 10) ns Figures 1, 3 (Note 10) 1.50 ns Figures 1, 4 (Note 10) 2.00 ns Figures 1, 2 (Note 10) Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 8: Screen tested 100% on each device at +25˚C temperature only, Subgroup A9. Note 9: Sample tested (Method 5005, Table I) on each manufactured lot at +25˚C, Subgroup A9, and at +125˚C and −55˚C, temperatures, Subgroups A10 and A11. Note 10: Not tested at +25˚C, +125˚C, and −55˚C temperature (design characterization data). Note 11: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. Test Circuitry DS100316-6 Notes: VCC, VCCA = +2V, VEE = −2.5V L1 and L2 = equal length 50Ω impedance linesRT = 50Ω terminator internal to scopeDecoupling 0.1 µF from GND to VCC and VEE All unused outputs are loaded with 50Ω to GNDCL = Fixture and stray capacitance ≤ 3 pF FIGURE 1. AC, Toggle Frequency Test Circuit www.national.com 4 Switching Waveforms DS100316-8 FIGURE 2. Propagation Delay (Clock) and Transition Times DS100316-9 FIGURE 3. Setup and Pulse Width Times DS100316-10 Note 12: ts is the minimum time before the transition of the clock that information must be present at the data input. Note 13: th is the minimum time after the transition of the clock that information must remain unchanged at the data input. FIGURE 4. Data Setup and Hold Time 5 www.national.com 6 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Ceramic Dual-In-Line Package (0.400" Wide) (D) NS Package Number J24E 24 Lead Quad Cerpak (F) NS Package Number W24B 7 www.national.com 100353 Low Power 8-Bit Register LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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